diff options
Diffstat (limited to 'src/regsmi.h')
| -rw-r--r-- | src/regsmi.h | 164 |
1 files changed, 159 insertions, 5 deletions
diff --git a/src/regsmi.h b/src/regsmi.h index c5af8cc..3a6d0e1 100644 --- a/src/regsmi.h +++ b/src/regsmi.h @@ -30,11 +30,16 @@ authorization from the XFree86 Project and SIlicon Motion. #ifndef _REGSMI_H #define _REGSMI_H +#ifndef PCI_CHIP_SMI501 +#define PCI_CHIP_SMI501 0x0501 +#endif + #define SMI_LYNX_SERIES(chip) ((chip & 0xF0F0) == 0x0010) #define SMI_LYNX3D_SERIES(chip) ((chip & 0xF0F0) == 0x0020) #define SMI_COUGAR_SERIES(chip) ((chip & 0xF0F0) == 0x0030) #define SMI_LYNXEM_SERIES(chip) ((chip & 0xFFF0) == 0x0710) #define SMI_LYNXM_SERIES(chip) ((chip & 0xFF00) == 0x0700) +#define SMI_MSOC_SERIES(chip) ((chip & 0xFF00) == 0x0500) /* Chip tags */ #define PCI_SMI_VENDOR_ID PCI_VENDOR_SMI @@ -46,6 +51,10 @@ authorization from the XFree86 Project and SIlicon Motion. #define SMI_LYNXEMplus PCI_CHIP_SMI712 #define SMI_LYNX3DM PCI_CHIP_SMI720 #define SMI_COUGAR3DR PCI_CHIP_SMI731 +#define SMI_MSOC PCI_CHIP_SMI501 + +/* Mobile-System-on-a-Chip */ +#define IS_MSOC(pSmi) ((pSmi)->Chipset == SMI_MSOC) /* I/O Functions */ static __inline__ CARD8 @@ -105,6 +114,20 @@ VGAOUT8(SMIPtr pSmi, int port, CARD8 data) #define READ_CPR(pSmi, cpr) MMIO_IN32(pSmi->CPRBase, cpr) #define WRITE_FPR(pSmi, fpr, data) MMIO_OUT32(pSmi->FPRBase, fpr, data); DEBUG((VERBLEV, "FPR%02X = %08X\n", fpr, data)) #define READ_FPR(pSmi, fpr) MMIO_IN32(pSmi->FPRBase, fpr) +#define WRITE_DCR(pSmi, dcr, data) MMIO_OUT32(pSmi->DCRBase, dcr, data); DEBUG((VERBLEV, "DCR%02X = %08X\n", dcr, data)) +#define READ_DCR(pSmi, dcr) MMIO_IN32(pSmi->DCRBase, dcr) +#define WRITE_SCR(pSmi, scr, data) MMIO_OUT32(pSmi->SCRBase, scr, data); DEBUG((VERBLEV, "SCR%02X = %08X\n", scr, data)) +#define READ_SCR(pSmi, scr) MMIO_IN32(pSmi->SCRBase, scr) + +#define CHECK_SECONDARY(pSmi) \ + if (IS_MSOC(pSmi) && !(pSmi)->IsSecondary) { \ + WRITE_DPR(pSmi, 0x40, 0); \ + WRITE_DPR(pSmi, 0x44, 0); \ + } \ + else { \ + WRITE_DPR(pSmi, 0x40, pScrn->fbOffset / 16 << 4); \ + WRITE_DPR(pSmi, 0x44, pScrn->fbOffset / 16 << 4); \ + } /* 2D Engine commands */ #define SMI_TRANSPARENT_SRC 0x00000100 @@ -152,15 +175,24 @@ VGAOUT8(SMIPtr pSmi, int port, CARD8 data) #define MAXLOOP 0x100000 /* timeout value for engine waits */ -#define ENGINE_IDLE() \ - ((VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x16) & 0x08) == 0) -#define FIFO_EMPTY() \ - ((VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x16) & 0x10) != 0) +#define ENGINE_IDLE() \ + IS_MSOC(pSmi) ? \ + (READ_SCR(pSmi, SCR00) & 0x00080000) == 0 : \ + (VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x16) & 0x08) == 0 +#define FIFO_EMPTY() \ + IS_MSOC(pSmi) ? \ + READ_SCR(pSmi, SCR00) & 0x00100000 : \ + VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x16) & 0x10 /* Wait until "v" queue entries are free */ +/**** FIXME + **** This is completely ilogical. Argument "v" is ignored, and + **** pSmi->NoPCIRetry defaults to true (but on smi sources this + **** macro is a noop and will get stuck on engine reset timeouts if enabled...) + ***/ #define WaitQueue(v) \ do { \ - if (pSmi->NoPCIRetry) { \ + if (!IS_MSOC(pSmi) && pSmi->NoPCIRetry) { \ int loop = MAXLOOP; mem_barrier(); \ while (!FIFO_EMPTY()) \ if (loop-- == 0) break; \ @@ -240,6 +272,128 @@ VGAOUT8(SMIPtr pSmi, int port, CARD8 data) #define FPR15C_MASK_HWCADDREN 0xFFFF0000 #define FPR15C_MASK_HWCENABLE 0x80000000 +/* SM501 System Configuration Registers */ +#define SCR00 0x0000 +#define SCR04 0x0004 +#define SCR08 0x0008 +#define SCR0C 0x000C +#define SCR10 0x0010 +#define SCR10_LOCAL_MEM_SIZE 0x0000E000 +#define SCR10_LOCAL_MEM_SIZE_SHIFT 13 +#define SCR14 0x0014 +#define SCR18 0x0018 +#define SCR1C 0x001C +#define SCR20 0x0020 +#define SCR24 0x0024 +#define SCR28 0x0028 +#define SCR2C 0x002C +#define SCR30 0x0030 +#define SCR34 0x0034 +#define SCR38 0x0038 +#define SCR3C 0x003C +#define SCR40 0x0040 +#define SCR44 0x0044 +#define SCR48 0x0048 +#define SCR4C 0x004C +#define SCR50 0x0050 +#define SCR54 0x0054 +#define SCR58 0x0058 +#define SCR5C 0x005C +#define SCR60 0x0060 +#define SCR64 0x0064 +#define SCR68 0x0068 +#define SCR6C 0x006C + +/* SM501 Panel Graphics Control */ +#define DCR00 0x0000 +#define DCR04 0x0004 +#define DCR08 0x0008 +#define DCR0C 0x000C +#define DCR10 0x0010 +#define DCR14 0x0014 +#define DCR18 0x0018 +#define DCR1C 0x001C +#define DCR20 0x0020 +#define DCR24 0x0024 +#define DCR28 0x0028 +#define DCR2c 0x002c +#define DCR30 0x0030 +#define DCR34 0x0034 + +/* SM 501 Video Control */ +#define DCR40 0x0040 +#define DCR44 0x0044 +#define DCR48 0x0048 +#define DCR4C 0x004C +#define DCR50 0x0050 +#define DCR54 0x0054 +#define DCR58 0x0058 +#define DCR5C 0x005C +#define DCR60 0x0060 +#define DCR64 0x0064 +#define DCR68 0x0068 + +/* SM501 Video Alpha Control */ +#define DCR80 0x0080 +#define DCR84 0x0084 +#define DCR88 0x0088 +#define DCR8C 0x008C +#define DCR90 0x0090 +#define DCR94 0x0094 +#define DCR98 0x0098 +#define DCR9C 0x009C +#define DCRA0 0x00A0 +#define DCRA4 0x00A4 + +/* SM501 Panel Cursor Control */ +#define DCRF0 0x00F0 +#define DCRF4 0x00F4 +#define DCRF8 0x00F8 +#define DCRFC 0x00FC + +/* SM 501 Alpha Control */ +#define DCR100 0x0100 +#define DCR104 0x0104 +#define DCR108 0x0108 +#define DCR10C 0x010C +#define DCR110 0x0110 +#define DCR114 0x0114 +#define DCR118 0x0118 + +/* SM 501 CRT Graphics Control */ +#define DCR200 0x0200 +#define DCR200_CRT_BLANK 0x00000400 +#define DCR200_CRT_GRAPHICS_PLN_FMT 0x00000003 +#define CRT_GRAPHICS_PLN_FMT_8 0x00 +#define CRT_GRAPHICS_PLN_FMT_16 0x01 +#define CRT_GRAPHICS_PLN_FMT_32 0x10 +#define DCR204 0x0204 +#define DCR208 0x0208 +#define DCR20C 0x020C +#define DCR210 0x0210 +#define DCR214 0x0214 +#define DCR218 0x0218 +#define DCR21C 0x021C +#define DCR220 0x0220 +#define DCR224 0x0224 + +/* SM 501 CRT Cursor Control */ +#define DCR230 0x0230 +#define DCR234 0x0234 +#define DCR238 0x0238 +#define DCR23C 0x023C + +/* SM 501 Palette Ram */ +#define DCR400 0x0400 /* Panel */ +#define DCR800 0x0800 /* Video */ +#define DCRC00 0x0C00 /* CRT */ + +/* HWCursor definitons for Panel AND CRT */ +#define SMI501_MASK_HWCENABLE 0x80000000 +#define SMI501_MASK_MAXBITS 0x000007FF +#define SMI501_MASK_BOUNDARY 0x00000800 +#define SMI501_HWCFBADDR_MASK 0x0CFFFFFF + /* panel sizes returned by the bios */ #define PANEL_640x480 0x00 |