diff options
Diffstat (limited to 'src/regsmi.h')
| -rw-r--r-- | src/regsmi.h | 139 |
1 files changed, 13 insertions, 126 deletions
diff --git a/src/regsmi.h b/src/regsmi.h index e359de9..bdf4035 100644 --- a/src/regsmi.h +++ b/src/regsmi.h @@ -198,11 +198,11 @@ VGAOUT8(SMIPtr pSmi, int port, CARD8 data) #define ENGINE_IDLE() \ (IS_MSOC(pSmi) ? \ - (READ_SCR(pSmi, SCR00) & 0x00080000) == 0 : \ + (READ_SCR(pSmi, 0x0000) & 0x00080000) == 0 : \ (VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x16) & 0x08) == 0) #define FIFO_EMPTY() \ (IS_MSOC(pSmi) ? \ - READ_SCR(pSmi, SCR00) & 0x00100000 : \ + READ_SCR(pSmi, 0x0000) & 0x00100000 : \ VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x16) & 0x10) /* Wait until "v" queue entries are free */ @@ -211,14 +211,17 @@ VGAOUT8(SMIPtr pSmi, int port, CARD8 data) **** pSmi->PCIRetry defaults to false (but on smi sources this **** macro is a noop and will get stuck on engine reset timeouts if enabled...) ***/ -#define WaitQueue(v) \ - do { \ - if (!IS_MSOC(pSmi) && !pSmi->PCIRetry) { \ - int loop = MAXLOOP; mem_barrier(); \ - while (!FIFO_EMPTY()) \ - if (loop-- == 0) break; \ - if (loop <= 0) SMI_GEReset(pScrn, 1, __LINE__, __FILE__); \ - } \ +#define WaitQueue(v) \ + do { \ + if (!IS_MSOC(pSmi)) { \ + int loop = MAXLOOP; \ + \ + mem_barrier(); \ + while (!FIFO_EMPTY()) \ + if (loop-- <= 0) \ + break; \ + if (loop <= 0) SMI_GEReset(pScrn, 1, __LINE__, __FILE__); \ + } \ } while (0) /* Wait until GP is idle */ @@ -293,122 +296,6 @@ VGAOUT8(SMIPtr pSmi, int port, CARD8 data) #define FPR15C_MASK_HWCADDREN 0xFFFF0000 #define FPR15C_MASK_HWCENABLE 0x80000000 -/* SM501 System Configuration Registers */ -#define SCR00 0x0000 -#define SCR04 0x0004 -#define SCR08 0x0008 -#define SCR0C 0x000C -#define SCR10 0x0010 -#define SCR10_LOCAL_MEM_SIZE 0x0000E000 -#define SCR10_LOCAL_MEM_SIZE_SHIFT 13 -#define SCR14 0x0014 -#define SCR18 0x0018 -#define SCR1C 0x001C -#define SCR20 0x0020 -#define SCR24 0x0024 -#define SCR28 0x0028 -#define SCR2C 0x002C -#define SCR30 0x0030 -#define SCR34 0x0034 -#define SCR38 0x0038 -#define SCR3C 0x003C -#define SCR40 0x0040 -#define SCR44 0x0044 -#define SCR48 0x0048 -#define SCR4C 0x004C -#define SCR50 0x0050 -#define SCR54 0x0054 -#define SCR58 0x0058 -#define SCR5C 0x005C -#define SCR60 0x0060 -#define SCR64 0x0064 -#define SCR68 0x0068 -#define SCR6C 0x006C - -/* SM501 Panel Graphics Control */ -#define DCR00 0x0000 -#define DCR04 0x0004 -#define DCR08 0x0008 -#define DCR0C 0x000C -#define DCR10 0x0010 -#define DCR14 0x0014 -#define DCR18 0x0018 -#define DCR1C 0x001C -#define DCR20 0x0020 -#define DCR24 0x0024 -#define DCR28 0x0028 -#define DCR2c 0x002c -#define DCR30 0x0030 -#define DCR34 0x0034 - -/* SM 501 Video Control */ -#define DCR40 0x0040 -#define DCR44 0x0044 -#define DCR48 0x0048 -#define DCR4C 0x004C -#define DCR50 0x0050 -#define DCR54 0x0054 -#define DCR58 0x0058 -#define DCR5C 0x005C -#define DCR60 0x0060 -#define DCR64 0x0064 -#define DCR68 0x0068 - -/* SM501 Video Alpha Control */ -#define DCR80 0x0080 -#define DCR84 0x0084 -#define DCR88 0x0088 -#define DCR8C 0x008C -#define DCR90 0x0090 -#define DCR94 0x0094 -#define DCR98 0x0098 -#define DCR9C 0x009C -#define DCRA0 0x00A0 -#define DCRA4 0x00A4 - -/* SM501 Panel Cursor Control */ -#define DCRF0 0x00F0 -#define DCRF4 0x00F4 -#define DCRF8 0x00F8 -#define DCRFC 0x00FC - -/* SM 501 Alpha Control */ -#define DCR100 0x0100 -#define DCR104 0x0104 -#define DCR108 0x0108 -#define DCR10C 0x010C -#define DCR110 0x0110 -#define DCR114 0x0114 -#define DCR118 0x0118 - -/* SM 501 CRT Graphics Control */ -#define DCR200 0x0200 -#define DCR200_CRT_BLANK 0x00000400 -#define DCR200_CRT_GRAPHICS_PLN_FMT 0x00000003 -#define CRT_GRAPHICS_PLN_FMT_8 0x00 -#define CRT_GRAPHICS_PLN_FMT_16 0x01 -#define CRT_GRAPHICS_PLN_FMT_32 0x10 -#define DCR204 0x0204 -#define DCR208 0x0208 -#define DCR20C 0x020C -#define DCR210 0x0210 -#define DCR214 0x0214 -#define DCR218 0x0218 -#define DCR21C 0x021C -#define DCR220 0x0220 -#define DCR224 0x0224 - -/* SM 501 CRT Cursor Control */ -#define DCR230 0x0230 -#define DCR234 0x0234 -#define DCR238 0x0238 -#define DCR23C 0x023C - -/* SM 501 Palette Ram */ -#define DCR400 0x0400 /* Panel */ -#define DCR800 0x0800 /* Video */ -#define DCRC00 0x0C00 /* CRT */ - /* HWCursor definitons for Panel AND CRT */ #define SMI501_MASK_HWCENABLE 0x80000000 #define SMI501_MASK_MAXBITS 0x000007FF |