Xv extension for VMware's video driver

This patch implements the Xv extension for VMware's X video driver.

The Xv specification can be found here
http://www.xfree86.org/current/DESIGN16.html

I've written a trivial offscreen memory manager that allocates memory from the
bottom part of the Video RAM and it can handle only 1 video-stream. Eventually
we intend to support upto 32 video-streams (there is already support for
multiple video streams in respective backends).

1 files changed, 336 insertions, 16 deletions

diff --git a/src/svga_reg.h b/src/svga_reg.h
index 871a8ff..4560fe7 100644
--- a/src/svga_reg.h
+++ b/src/svga_reg.h
@@ -1,7 +1,5 @@
 /* **********************************************************
- * Copyright (C) 1998-2001 VMware, Inc.
- * All Rights Reserved
- * $Id$
+ * Copyright 1998 VMware, Inc.  All rights reserved.
  * **********************************************************/
 
 /*
@@ -9,13 +7,13 @@
  *
  * SVGA hardware definitions
  */
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/vmware/svga_reg.h,v 1.7 2002/12/10 04:17:19 dawes Exp $ */
 
 #ifndef _SVGA_REG_H_
 #define _SVGA_REG_H_
 
 #define INCLUDE_ALLOW_USERLEVEL
 #define INCLUDE_ALLOW_VMMEXT
+#define INCLUDE_ALLOW_VMCORE
 #include "includeCheck.h"
 
 /*
@@ -30,7 +28,17 @@
 #define SVGA_MAX_HEIGHT			1770
 #define SVGA_MAX_BITS_PER_PIXEL		32
 #define SVGA_MAX_DEPTH                  24
+#define SVGA_MAX_DISPLAYS               10
 
+/*
+ * The maximum size of the onscreen framebuffer.  The size of the
+ * changeMap in the monitor is proportional to this number since it's
+ * the amount of memory we need to trace in VESA mode.  Therefore, we'd
+ * like to keep it as small as possible to reduce monitor overhead (using
+ * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area
+ * by over 4k!).
+ */
+ 
 #define SVGA_FB_MAX_SIZE \
    ((((SVGA_MAX_WIDTH * SVGA_MAX_HEIGHT *                                    \
        SVGA_MAX_BITS_PER_PIXEL / 8) >> PAGE_SHIFT) + 1) << PAGE_SHIFT)
@@ -67,6 +75,17 @@
 #define SVGA_VALUE_PORT		0x1
 #define SVGA_BIOS_PORT		0x2
 #define SVGA_NUM_PORTS		0x3
+#define SVGA_IRQSTATUS_PORT	0x8
+
+/*
+ * Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
+ *
+ * Interrupts are only supported when the
+ * SVGA_CAP_IRQMASK capability is present.
+ */
+#define SVGA_IRQFLAG_ANY_FENCE            0x1    /* Any fence was passed */
+#define SVGA_IRQFLAG_FIFO_PROGRESS        0x2    /* Made forward progress in the FIFO */
+#define SVGA_IRQFLAG_FENCE_GOAL           0x4    /* SVGA_FIFO_FENCE_GOAL reached */
 
 /* This port is deprecated, but retained because of old drivers. */
 #define SVGA_LEGACY_ACCEL_PORT	0x3
@@ -106,8 +125,8 @@ enum {
    SVGA_REG_MEM_START = 18,	   /* Memory for command FIFO and bitmaps */
    SVGA_REG_MEM_SIZE = 19,
    SVGA_REG_CONFIG_DONE = 20,      /* Set when memory area configured */
-   SVGA_REG_SYNC = 21,             /* Write to force synchronization */
-   SVGA_REG_BUSY = 22,             /* Read to check if sync is done */
+   SVGA_REG_SYNC = 21,             /* See "FIFO Synchronization Registers" */
+   SVGA_REG_BUSY = 22,             /* See "FIFO Synchronization Registers" */
    SVGA_REG_GUEST_ID = 23,	   /* Set guest OS identifier */
    SVGA_REG_CURSOR_ID = 24,	   /* ID of cursor */
    SVGA_REG_CURSOR_X = 25,	   /* Set cursor X position */
@@ -118,7 +137,8 @@ enum {
    SVGA_REG_MEM_REGS = 30,         /* Number of FIFO registers */
    SVGA_REG_NUM_DISPLAYS = 31,     /* Number of guest displays */
    SVGA_REG_PITCHLOCK = 32,        /* Fixed pitch for all modes */
-   SVGA_REG_TOP = 33,		   /* Must be 1 more than the last register */
+   SVGA_REG_IRQMASK = 33,          /* Interrupt mask */
+   SVGA_REG_TOP = 34,		   /* Must be 1 more than the last register */
 
    SVGA_PALETTE_BASE = 1024,	   /* Base of SVGA color map */
    /* Next 768 (== 256*3) registers exist for colormap */
@@ -153,6 +173,7 @@ enum {
 #define SVGA_CAP_EXTENDED_FIFO      0x08000
 #define SVGA_CAP_MULTIMON           0x10000
 #define SVGA_CAP_PITCHLOCK          0x20000
+#define SVGA_CAP_IRQMASK            0x40000
 
 /*
  *  Raster op codes (same encoding as X) used by FIFO drivers.
@@ -247,12 +268,24 @@ enum {
 
 
 /*
- *  FIFO offsets (viewed as an array of 32-bit words)
+ * FIFO register indices.
+ *
+ * The FIFO is a chunk of device memory mapped into guest physmem.  It
+ * is always treated as 32-bit words.
+ *
+ * The guest driver gets to decide how to partition it between
+ * - FIFO registers (there are always at least 4, specifying where the
+ *   following data area is and how much data it contains; there may be
+ *   more registers following these, depending on the FIFO protocol
+ *   version in use)
+ * - FIFO data, written by the guest and slurped out by the VMX.
+ * These indices are 32-bit word offsets into the FIFO.
  */
 
 enum {
    /*
-    * The original defined FIFO offsets
+    * Block 1 (basic registers): The originally defined FIFO registers.
+    * These exist and are valid for all versions of the FIFO protocol.
     */
 
    SVGA_FIFO_MIN = 0,
@@ -261,35 +294,244 @@ enum {
    SVGA_FIFO_STOP,
 
    /*
-    * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
+    * Block 2 (extended registers): Mandatory registers for the extended
+    * FIFO.  These exist if the SVGA caps register includes
+    * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
+    * associated capability bit is enabled.
+    *
+    * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
+    * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
+    * This means that the guest has to test individually (in most cases
+    * using FIFO caps) for the presence of registers after this; the VMX
+    * can define "extended FIFO" to mean whatever it wants, and currently
+    * won't enable it unless there's room for that set and much more.
     */
 
    SVGA_FIFO_CAPABILITIES = 4,
    SVGA_FIFO_FLAGS,
+   // Valid with SVGA_FIFO_CAP_FENCE:
    SVGA_FIFO_FENCE,
-   SVGA_FIFO_3D_HWVERSION,     /* Check SVGA3dHardwareVersion in svga3d_reg.h */
+
+   /*
+    * Block 3a (optional extended registers): Additional registers for the
+    * extended FIFO, whose presence isn't actually implied by
+    * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
+    * leave room for them.
+    *
+    * These in block 3a, the VMX currently considers mandatory for the
+    * extended FIFO.
+    */
+   
+   // Valid if exists (i.e. if extended FIFO enabled):
+   SVGA_FIFO_3D_HWVERSION,       /* See SVGA3dHardwareVersion in svga3d_reg.h */
+   // Valid with SVGA_FIFO_CAP_PITCHLOCK:
    SVGA_FIFO_PITCHLOCK,
+   // Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3:
+   SVGA_FIFO_CURSOR_ON,          /* Cursor bypass 3 show/hide register */
+   SVGA_FIFO_CURSOR_X,           /* Cursor bypass 3 x register */
+   SVGA_FIFO_CURSOR_Y,           /* Cursor bypass 3 y register */
+   SVGA_FIFO_CURSOR_COUNT,       /* Incremented when any of the other 3 change */
+   SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
+   // Valid with SVGA_FIFO_CAP_RESERVE:
+   SVGA_FIFO_RESERVED,           /* Bytes past NEXT_CMD with real contents */
+   /*
+    * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
+    * registers, but this must be done carefully and with judicious use of
+    * capability bits, since comparisons based on SVGA_FIFO_MIN aren't
+    * enough to tell you whether the register exists: we've shipped drivers
+    * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
+    * the earlier ones.  The actual order of introduction was:
+    * - PITCHLOCK
+    * - 3D_CAPS
+    * - CURSOR_* (cursor bypass 3)
+    * - RESERVED
+    * So, code that wants to know whether it can use any of the
+    * aforementioned registers, or anything else added after PITCHLOCK and
+    * before 3D_CAPS, needs to reason about something other than
+    * SVGA_FIFO_MIN.
+    */
+   /*
+    * 3D caps block space; valid with 3D hardware version >=
+    * SVGA3D_HWVERSION_WS6_B1.
+    */
+   SVGA_FIFO_3D_CAPS      = 32,
+   SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
 
    /*
-    * Always keep this last.  It's not an offset with semantic value, but
-    * rather a convenient way to produce the value of fifo[SVGA_FIFO_NUM_REGS]
+    * End of VMX's current definition of "extended-FIFO registers".
+    * Registers before here are always enabled/disabled as a block; either
+    * the extended FIFO is enabled and includes all preceding registers, or
+    * it's disabled entirely.
+    *
+    * Block 3b (truly optional extended registers): Additional registers for
+    * the extended FIFO, which the VMX already knows how to enable and
+    * disable with correct granularity.
+    *
+    * Registers after here exist if and only if the guest SVGA driver
+    * sets SVGA_FIFO_MIN high enough to leave room for them.
     */
 
-   SVGA_FIFO_NUM_REGS
+   // Valid if register exists:
+   SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
+   SVGA_FIFO_FENCE_GOAL,         /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
+   SVGA_FIFO_BUSY,               /* See "FIFO Synchronization Registers" */
+
+   /*
+    * Always keep this last.  This defines the maximum number of
+    * registers we know about.  At power-on, this value is placed in
+    * the SVGA_REG_MEM_REGS register, and we expect the guest driver
+    * to allocate this much space in FIFO memory for registers.
+    */
+    SVGA_FIFO_NUM_REGS
 };
 
+
+/*
+ * Definition of registers included in extended FIFO support.
+ *
+ * The guest SVGA driver gets to allocate the FIFO between registers
+ * and data.  It must always allocate at least 4 registers, but old
+ * drivers stopped there.
+ *
+ * The VMX will enable extended FIFO support if and only if the guest
+ * left enough room for all registers defined as part of the mandatory
+ * set for the extended FIFO.
+ *
+ * Note that the guest drivers typically allocate the FIFO only at
+ * initialization time, not at mode switches, so it's likely that the
+ * number of FIFO registers won't change without a reboot.
+ *
+ * All registers less than this value are guaranteed to be present if
+ * svgaUser->fifo.extended is set. Any later registers must be tested
+ * individually for compatibility at each use (in the VMX).
+ *
+ * This value is used only by the VMX, so it can change without
+ * affecting driver compatibility; keep it that way?
+ */
+#define SVGA_FIFO_EXTENDED_MANDATORY_REGS  (SVGA_FIFO_3D_CAPS_LAST + 1)
+
+
+/*
+ * FIFO Synchronization Registers
+ *
+ *  This explains the relationship between the various FIFO
+ *  sync-related registers in IOSpace and in FIFO space.
+ *
+ *  SVGA_REG_SYNC --
+ *
+ *       The SYNC register can be used in two different ways by the guest:
+ *
+ *         1. If the guest wishes to fully sync (drain) the FIFO,
+ *            it will write once to SYNC then poll on the BUSY
+ *            register. The FIFO is sync'ed once BUSY is zero.
+ *
+ *         2. If the guest wants to asynchronously wake up the host,
+ *            it will write once to SYNC without polling on BUSY.
+ *            Ideally it will do this after some new commands have
+ *            been placed in the FIFO, and after reading a zero
+ *            from SVGA_FIFO_BUSY.
+ *
+ *       (1) is the original behaviour that SYNC was designed to
+ *       support.  Originally, a write to SYNC would implicitly
+ *       trigger a read from BUSY. This causes us to synchronously
+ *       process the FIFO.
+ *
+ *       This behaviour has since been changed so that writing SYNC
+ *       will *not* implicitly cause a read from BUSY. Instead, it
+ *       makes a channel call which asynchronously wakes up the MKS
+ *       thread.
+ *
+ *       New guests can use this new behaviour to implement (2)
+ *       efficiently. This lets guests get the host's attention
+ *       without waiting for the MKS to poll, which gives us much
+ *       better CPU utilization on SMP hosts and on UP hosts while
+ *       we're blocked on the host GPU.
+ *
+ *       Old guests shouldn't notice the behaviour change. SYNC was
+ *       never guaranteed to process the entire FIFO, since it was
+ *       bounded to a particular number of CPU cycles. Old guests will
+ *       still loop on the BUSY register until the FIFO is empty.
+ *
+ *       Writing to SYNC currently has the following side-effects:
+ *
+ *         - Sets SVGA_REG_BUSY to TRUE (in the monitor)
+ *         - Asynchronously wakes up the MKS thread for FIFO processing
+ *         - The value written to SYNC is recorded as a "reason", for
+ *           stats purposes.
+ *
+ *       If SVGA_FIFO_BUSY is available, drivers are advised to only
+ *       write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
+ *       SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
+ *       eventually set SVGA_FIFO_BUSY on its own, but this approach
+ *       lets the driver avoid sending multiple asynchronous wakeup
+ *       messages to the MKS thread.
+ *
+ *  SVGA_REG_BUSY --
+ *
+ *       This register is set to TRUE when SVGA_REG_SYNC is written,
+ *       and it reads as FALSE when the FIFO has been completely
+ *       drained.
+ *
+ *       Every read from this register causes us to synchronously
+ *       process FIFO commands. There is no guarantee as to how many
+ *       commands each read will process.
+ *
+ *       CPU time spent processing FIFO commands will be billed to
+ *       the guest.
+ *
+ *       New drivers should avoid using this register unless they
+ *       need to guarantee that the FIFO is completely drained. It
+ *       is overkill for performing a sync-to-fence. Older drivers
+ *       will use this register for any type of synchronization.
+ *
+ *  SVGA_FIFO_BUSY --
+ *
+ *       This register is a fast way for the guest driver to check
+ *       whether the FIFO is already being processed. It reads and
+ *       writes at normal RAM speeds, with no monitor intervention.
+ *
+ *       If this register reads as TRUE, the host is guaranteeing that
+ *       any new commands written into the FIFO will be noticed before
+ *       the MKS goes back to sleep.
+ *
+ *       If this register reads as FALSE, no such guarantee can be
+ *       made.
+ *
+ *       The guest should use this register to quickly determine
+ *       whether or not it needs to wake up the host. If the guest
+ *       just wrote a command or group of commands that it would like
+ *       the host to begin processing, it should:
+ *
+ *         1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
+ *            action is necessary.
+ *
+ *         2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
+ *            code that we've already sent a SYNC to the host and we
+ *            don't need to send a duplicate.
+ *
+ *         3. Write a reason to SVGA_REG_SYNC. This will send an
+ *            asynchronous wakeup to the MKS thread.
+ */
+
+
 /*
  * FIFO Capabilities
  *
  *      Fence -- Fence register and command are supported
  *      Accel Front -- Front buffer only commands are supported
  *      Pitch Lock -- Pitch lock register is supported
+ *      Video -- SVGA Video overlay units are supported
+ *      Escape -- Escape command is supported
  */
 
 #define SVGA_FIFO_CAP_NONE                  0
 #define SVGA_FIFO_CAP_FENCE             (1<<0)
 #define SVGA_FIFO_CAP_ACCELFRONT        (1<<1)
 #define SVGA_FIFO_CAP_PITCHLOCK         (1<<2)
+#define SVGA_FIFO_CAP_VIDEO             (1<<3)
+#define SVGA_FIFO_CAP_CURSOR_BYPASS_3   (1<<4)
+#define SVGA_FIFO_CAP_ESCAPE            (1<<5)
+#define SVGA_FIFO_CAP_RESERVE           (1<<6)
 
 
 /*
@@ -300,6 +542,72 @@ enum {
 
 #define SVGA_FIFO_FLAG_NONE                 0
 #define SVGA_FIFO_FLAG_ACCELFRONT       (1<<0)
+#define SVGA_FIFO_FLAG_RESERVED        (1<<31) // Internal use only
+
+/*
+ * FIFO reservation sentinel value
+ */
+
+#define SVGA_FIFO_RESERVED_UNKNOWN      0xffffffff
+
+
+/*
+ * Video overlay support
+ */
+
+#define SVGA_NUM_OVERLAY_UNITS 32
+
+
+/*
+ * Video capabilities that the guest is currently using
+ */
+
+#define SVGA_VIDEO_FLAG_COLORKEY        0x0001
+
+
+/*
+ * Offsets for the video overlay registers
+ */
+
+enum {
+   SVGA_VIDEO_ENABLED = 0,
+   SVGA_VIDEO_FLAGS,
+   SVGA_VIDEO_DATA_OFFSET,
+   SVGA_VIDEO_FORMAT,
+   SVGA_VIDEO_COLORKEY,
+   SVGA_VIDEO_SIZE,
+   SVGA_VIDEO_X,
+   SVGA_VIDEO_Y,
+   SVGA_VIDEO_SRC_WIDTH,
+   SVGA_VIDEO_SRC_HEIGHT,
+   SVGA_VIDEO_DST_WIDTH,
+   SVGA_VIDEO_DST_HEIGHT,
+   SVGA_VIDEO_PITCH_1,
+   SVGA_VIDEO_PITCH_2,
+   SVGA_VIDEO_PITCH_3,
+   SVGA_VIDEO_NUM_REGS
+};
+
+
+/*
+ * SVGA Overlay Units
+ */
+
+typedef struct SVGAOverlayUnit {
+   uint32 enabled;
+   uint32 flags;
+   uint32 dataOffset; 
+   uint32 format;
+   uint32 colorKey;
+   uint32 size;
+   uint32 x;
+   uint32 y;
+   uint32 srcWidth;
+   uint32 srcHeight;
+   uint32 dstWidth;
+   uint32 dstHeight;
+   uint32 pitches[3];
+} SVGAOverlayUnit;
 
 
 /*
@@ -319,6 +627,7 @@ enum {
 #define SVGA_PIXMAP_SCANLINE_SIZE(w,bpp) (( ((w)*(bpp))+31 ) >> 5)
 #define SVGA_GLYPH_SIZE(w,h) ((((((w) + 7) >> 3) * (h)) + 3) >> 2)
 #define SVGA_GLYPH_SCANLINE_SIZE(w) (((w) + 7) >> 3)
+#define SVGA_ESCAPE_SIZE(s) (((s) + 3) >> 2)
 
 /*
  *  Increment from one scanline to the next of a bitmap or pixmap
@@ -468,14 +777,25 @@ enum {
          /* FIFO layout:
             Fence value */
 
-#define	SVGA_CMD_MAX			  31
+#define SVGA_CMD_VIDEO_PLAY_OBSOLETE      31
+         /* Obsolete; do not use. */
+
+#define SVGA_CMD_VIDEO_END_OBSOLETE       32
+         /* Obsolete; do not use. */
+
+#define SVGA_CMD_ESCAPE                   33
+         /* FIFO layout:
+            Namespace ID, size(bytes), data */
+
+#define	SVGA_CMD_MAX                      34
 
 #define SVGA_CMD_MAX_ARGS                 64
 
 /*
  * Location and size of SVGA frame buffer and the FIFO.
  */
-#define SVGA_VRAM_MAX_SIZE     (16 * 1024 * 1024)
+#define SVGA_VRAM_MIN_SIZE   (4 * 640 * 480)  // bytes
+#define SVGA_VRAM_MAX_SIZE   (128 * 1024 * 1024)
 
 #define SVGA_VRAM_SIZE_WS       (16 * 1024 * 1024) // 16 MB
 #define SVGA_MEM_SIZE_WS        (2  * 1024 * 1024) // 2  MB