diff options
| author | Mike Larkin <mlarkin@cvs.openbsd.org> | 2018-01-15 06:53:03 +0000 |
|---|---|---|
| committer | Mike Larkin <mlarkin@cvs.openbsd.org> | 2018-01-15 06:53:03 +0000 |
| commit | 286a366c1e58f6551d6d2341b550642b10b758f7 (patch) | |
| tree | bd59c8538ad88fc1f68ba115b2296de8a56e6850 | |
| parent | 92a7d34845d7693c487811a4931c87955c81a4ff (diff) | |
Add some AVX512 CPUID flags.
discussed with sf and kettenis
| -rw-r--r-- | sys/arch/amd64/amd64/identcpu.c | 4 | ||||
| -rw-r--r-- | sys/arch/amd64/include/specialreg.h | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c index 3e4cd032b38..554b0a55625 100644 --- a/sys/arch/amd64/amd64/identcpu.c +++ b/sys/arch/amd64/amd64/identcpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: identcpu.c,v 1.92 2018/01/12 08:21:30 mlarkin Exp $ */ +/* $OpenBSD: identcpu.c,v 1.93 2018/01/15 06:53:02 mlarkin Exp $ */ /* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */ /* @@ -198,6 +198,8 @@ const struct { { SEFF0ECX_UMIP, "UMIP" }, { SEFF0ECX_PKU, "PKU" }, }, cpu_seff0_edxfeatures[] = { + { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" }, + { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, { SEFF0EDX_IBRS, "IBRS,IBPB" }, { SEFF0EDX_STIBP, "STIBP" }, }, cpu_tpm_eaxfeatures[] = { diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 85a8ecdc2a7..c3319c7271e 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.64 2018/01/11 22:31:09 patrick Exp $ */ +/* $OpenBSD: specialreg.h,v 1.65 2018/01/15 06:53:02 mlarkin Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -215,6 +215,8 @@ #define SEFF0ECX_UMIP 0x00000004 /* UMIP support */ #define SEFF0ECX_PKU 0x00000008 /* Page prot keys for user mode */ /* SEFF EDX bits */ +#define SEFF0EDX_AVX512_4FNNIW 0x00000004 /* AVX-512 neural network insns */ +#define SEFF0EDX_AVX512_4FMAPS 0x00000008 /* AVX-512 mult accum single prec */ #define SEFF0EDX_IBRS 0x04000000 /* IBRS / IBPB Speculation Control */ #define SEFF0EDX_STIBP 0x08000000 /* STIBP Speculation Control */ |