fenv for amd64; from matthew@

feedback & ok guenther@, matthew@

3 files changed, 587 insertions, 0 deletions

diff --git a/include/fenv.h b/include/fenv.h
new file mode 100644
index 00000000000..9d7197173b3
--- /dev/null
+++ b/include/fenv.h
@@ -0,0 +1,59 @@
+/*	$OpenBSD: fenv.h,v 1.1 2011/04/21 21:12:56 martynas Exp $	*/
+/*	$NetBSD: fenv.h,v 1.2.4.1 2011/02/08 16:18:55 bouyer Exp $	*/
+
+/*
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef	_FENV_H_
+#define	_FENV_H_
+
+#include <sys/cdefs.h>
+#include <machine/fenv.h>
+
+__BEGIN_DECLS
+
+int	feclearexcept(int);
+int	fegetexceptflag(fexcept_t *, int);
+int	feraiseexcept(int);
+int	fesetexceptflag(const fexcept_t *, int);
+int	fetestexcept(int);
+
+int	fegetround(void);
+int	fesetround(int);
+int	fegetenv(fenv_t *);
+int	feholdexcept(fenv_t *);
+int	fesetenv(const fenv_t *);
+int	feupdateenv(const fenv_t *);
+
+#if	__BSD_VISIBLE
+int	feenableexcept(int);
+int	fedisableexcept(int);
+int	fegetexcept(void);
+#endif	/* __BSD_VISIBLE */
+
+__END_DECLS
+
+#endif	/* ! _FENV_H_ */
diff --git a/lib/libm/arch/amd64/fenv.c b/lib/libm/arch/amd64/fenv.c
new file mode 100644
index 00000000000..781d8a39d92
--- /dev/null
+++ b/lib/libm/arch/amd64/fenv.c
@@ -0,0 +1,423 @@
+/*	$OpenBSD: fenv.c,v 1.1 2011/04/21 21:12:55 martynas Exp $	*/
+/* $NetBSD: fenv.c,v 1.1 2010/07/31 21:47:53 joerg Exp $ */
+
+/*-
+ * Copyright (c) 2004-2005 David Schultz <das (at) FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+#include <machine/fpu.h>
+
+#include <fenv.h>
+
+/*
+ * The following constant represents the default floating-point environment
+ * (that is, the one installed at program startup) and has type pointer to
+ * const-qualified fenv_t.
+ *
+ * It can be used as an argument to the functions within the <fenv.h> header
+ * that manage the floating-point environment, namely fesetenv() and
+ * feupdateenv().
+ *
+ * x87 fpu registers are 16bit wide. The upper bits, 31-16, are marked as
+ * RESERVED.
+ */
+fenv_t __fe_dfl_env = {
+	{
+		0xffff0000 | __INITIAL_NPXCW__,	/* Control word register */
+		0xffff0000,			/* Status word register */
+		0xffffffff,			/* Tag word register */
+		{
+			0x00000000,
+			0x00000000,
+			0x00000000,
+			0xffff0000,
+		},
+	},
+	__INITIAL_MXCSR__			/* MXCSR register */
+};
+
+
+/*
+ * The feclearexcept() function clears the supported floating-point exceptions
+ * represented by `excepts'.
+ */
+int
+feclearexcept(int excepts)
+{
+	fenv_t fenv;
+	unsigned int mxcsr;
+
+	excepts &= FE_ALL_EXCEPT;
+
+	/* Store the current x87 floating-point environment */
+	__asm__ __volatile__ ("fnstenv %0" : "=m" (fenv));
+
+	/* Clear the requested floating-point exceptions */
+	fenv.__x87.__status &= ~excepts;
+
+	/* Load the x87 floating-point environent */
+	__asm__ __volatile__ ("fldenv %0" : : "m" (fenv));
+
+	/* Same for SSE environment */
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
+	mxcsr &= ~excepts;
+	__asm__ __volatile__ ("ldmxcsr %0" : : "m" (mxcsr));
+
+	return (0);
+}
+
+/*
+ * The fegetexceptflag() function stores an implementation-defined
+ * representation of the states of the floating-point status flags indicated by
+ * the argument excepts in the object pointed to by the argument flagp.
+ */
+int
+fegetexceptflag(fexcept_t *flagp, int excepts)
+{
+	unsigned short x87_status;
+	unsigned int mxcsr;
+
+	excepts &= FE_ALL_EXCEPT;
+
+	/* Store the current x87 status register */
+	__asm__ __volatile__ ("fnstsw %0" : "=am" (x87_status));
+
+	/* Store the MXCSR register */
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
+
+	/* Store the results in flagp */
+	*flagp = (x87_status | mxcsr) & excepts;
+
+	return (0);
+}
+
+/*
+ * The feraiseexcept() function raises the supported floating-point exceptions
+ * represented by the argument `excepts'.
+ *
+ * The standard explicitly allows us to execute an instruction that has the
+ * exception as a side effect, but we choose to manipulate the status register
+ * directly.
+ *
+ * The validation of input is being deferred to fesetexceptflag().
+ */
+int
+feraiseexcept(int excepts)
+{
+	excepts &= FE_ALL_EXCEPT;
+
+	fesetexceptflag((fexcept_t *)&excepts, excepts);
+	__asm__ __volatile__ ("fwait");
+
+	return (0);
+}
+
+/*
+ * This function sets the floating-point status flags indicated by the argument
+ * `excepts' to the states stored in the object pointed to by `flagp'. It does
+ * NOT raise any floating-point exceptions, but only sets the state of the flags.
+ */
+int
+fesetexceptflag(const fexcept_t *flagp, int excepts)
+{
+	fenv_t fenv;
+	unsigned int mxcsr;
+
+	excepts &= FE_ALL_EXCEPT;
+
+	/* Store the current x87 floating-point environment */
+	__asm__ __volatile__ ("fnstenv %0" : "=m" (fenv));
+
+	/* Set the requested status flags */
+	fenv.__x87.__status &= ~excepts;
+	fenv.__x87.__status |= *flagp & excepts;
+
+	/* Load the x87 floating-point environent */
+	__asm__ __volatile__ ("fldenv %0" : : "m" (fenv));
+
+	/* Same for SSE environment */
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
+	mxcsr &= ~excepts;
+	mxcsr |= *flagp & excepts;
+	__asm__ __volatile__ ("ldmxcsr %0" : : "m" (mxcsr));
+
+	return (0);
+}
+
+/*
+ * The fetestexcept() function determines which of a specified subset of the
+ * floating-point exception flags are currently set. The `excepts' argument
+ * specifies the floating-point status flags to be queried.
+ */
+int
+fetestexcept(int excepts)
+{
+	unsigned short x87_status;
+	unsigned int mxcsr;
+
+	excepts &= FE_ALL_EXCEPT;
+
+	/* Store the current x87 status register */
+	__asm__ __volatile__ ("fnstsw %0" : "=am" (x87_status));
+
+	/* Store the MXCSR register state */
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
+
+	return ((x87_status | mxcsr) & excepts);
+}
+
+/*
+ * The fegetround() function gets the current rounding direction.
+ */
+int
+fegetround(void)
+{
+	unsigned short control;
+	unsigned int mxcsr;
+
+	/*
+	 * We check both the x87 floating-point unit _and_ the SSE unit.
+	 * Normally, those two must agree with respect to each other. If they
+	 * don't, it's not our fault and the result is non-determinable, in
+	 * which case POSIX says that a negative value should be returned.
+	 */
+	__asm__ __volatile__ ("fnstcw %0" : "=m" (control));
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
+
+	if ((control & _X87_ROUND_MASK)
+	    != ((mxcsr & _SSE_ROUND_MASK) >> 3)) {
+		return (-1);
+	}
+
+	return (control & _X87_ROUND_MASK);
+}
+
+/*
+ * The fesetround() function establishes the rounding direction represented by
+ * its argument `round'. If the argument is not equal to the value of a rounding
+ * direction macro, the rounding direction is not changed.
+ */
+int
+fesetround(int round)
+{
+	unsigned short control;
+	unsigned int mxcsr;
+
+	/* Check whether requested rounding direction is supported */
+	if (round & ~_X87_ROUND_MASK)
+		return (-1);
+
+	/* Store the current x87 control word register  */
+	__asm__ __volatile__ ("fnstcw %0" : "=m" (control));
+
+	/*
+	 * Set the rounding direction
+	 * Rounding Control is bits 10-11, so shift appropriately
+	 */
+	control &= ~_X87_ROUND_MASK;
+	control |= round;
+
+	/* Load the x87 control word register */
+	__asm__ __volatile__ ("fldcw %0" : : "m" (control));
+
+	/*
+	 * Same for the SSE environment
+	 * Rounding Control is bits 13-14, so shift appropriately
+	 */
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
+	mxcsr &= ~_SSE_ROUND_MASK;
+	mxcsr |= (round << _SSE_ROUND_SHIFT);
+	__asm__ __volatile__ ("ldmxcsr %0" : : "m" (mxcsr));
+
+	return (0);
+}
+
+/*
+ * The fegetenv() function attempts to store the current floating-point
+ * environment in the object pointed to by envp.
+ */
+int
+fegetenv(fenv_t *envp)
+{
+	/* Store the current x87 floating-point environment */
+	__asm__ __volatile__ ("fnstenv %0" : "=m" (*envp));
+
+	/* Store the MXCSR register state */
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (envp->__mxcsr));
+
+	/*
+	 * When an FNSTENV instruction is executed, all pending exceptions are
+	 * essentially lost (either the x87 FPU status register is cleared or
+	 * all exceptions are masked).
+	 *
+	 * 8.6 X87 FPU EXCEPTION SYNCHRONIZATION -
+	 * Intel(R) 64 and IA-32 Architectures Softare Developer's Manual - Vol1
+	 */
+	__asm__ __volatile__ ("fldcw %0" : : "m" (envp->__x87.__control));
+
+	return (0);
+}
+
+/*
+ * The feholdexcept() function saves the current floating-point environment
+ * in the object pointed to by envp, clears the floating-point status flags, and
+ * then installs a non-stop (continue on floating-point exceptions) mode, if
+ * available, for all floating-point exceptions.
+ */
+int
+feholdexcept(fenv_t *envp)
+{
+	unsigned int mxcsr;
+
+	/* Store the current x87 floating-point environment */
+	__asm__ __volatile__ ("fnstenv %0" : "=m" (*envp));
+
+	/* Clear all exception flags in FPU */
+	__asm__ __volatile__ ("fnclex");
+
+	/* Store the MXCSR register state */
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (envp->__mxcsr));
+
+	/* Clear exception flags in MXCSR XXX */
+	mxcsr = envp->__mxcsr;
+	mxcsr &= ~FE_ALL_EXCEPT;
+
+	/* Mask all exceptions */
+	mxcsr |= FE_ALL_EXCEPT << _SSE_EMASK_SHIFT;
+
+	__asm__ __volatile__ ("ldmxcsr %0" : : "m" (mxcsr));
+
+	return (0);
+}
+
+/*
+ * The fesetenv() function attempts to establish the floating-point environment
+ * represented by the object pointed to by envp. The argument `envp' points
+ * to an object set by a call to fegetenv() or feholdexcept(), or equal a
+ * floating-point environment macro. The fesetenv() function does not raise
+ * floating-point exceptions, but only installs the state of the floating-point
+ * status flags represented through its argument.
+ */
+int
+fesetenv(const fenv_t *envp)
+{
+	/* Load the x87 floating-point environent */
+	__asm__ __volatile__ ("fldenv %0" : : "m" (*envp));
+
+	/* Store the MXCSR register */
+	__asm__ __volatile__ ("ldmxcsr %0" : : "m" (envp->__mxcsr));
+
+	return (0);
+}
+
+/*
+ * The feupdateenv() function saves the currently raised floating-point
+ * exceptions in its automatic storage, installs the floating-point environment
+ * represented by the object pointed to by `envp', and then raises the saved
+ * floating-point exceptions. The argument `envp' shall point to an object set
+ * by a call to feholdexcept() or fegetenv(), or equal a floating-point
+ * environment macro.
+ */
+int
+feupdateenv(const fenv_t *envp)
+{
+	unsigned short x87_status;
+	unsigned int mxcsr;
+
+	/* Store the x87 status register */
+	__asm__ __volatile__ ("fnstsw %0" : "=am" (x87_status));
+
+	/* Store the MXCSR register */
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
+
+	/* Install new floating-point environment */
+	fesetenv(envp);
+
+	/* Raise any previously accumulated exceptions */
+	feraiseexcept(x87_status | mxcsr);
+
+	return (0);
+}
+
+/*
+ * The following functions are extentions to the standard
+ */
+int
+feenableexcept(int mask)
+{
+	unsigned int mxcsr, omask;
+	unsigned short control;
+
+	mask &= FE_ALL_EXCEPT;
+
+	__asm__ __volatile__ ("fnstcw %0" : "=m" (control));
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
+
+	omask = ~(control | (mxcsr >> _SSE_EMASK_SHIFT)) & FE_ALL_EXCEPT;
+	control &= ~mask;
+	__asm__ __volatile__ ("fldcw %0" : : "m" (control));
+
+	mxcsr &= ~(mask << _SSE_EMASK_SHIFT);
+	__asm__ __volatile__ ("ldmxcsr %0" : : "m" (mxcsr));
+
+	return (omask);
+
+}
+
+int
+fedisableexcept(int mask)
+{
+	unsigned int mxcsr, omask;
+	unsigned short control;
+
+	mask &= FE_ALL_EXCEPT;
+
+	__asm__ __volatile__ ("fnstcw %0" : "=m" (control));
+	__asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
+
+	omask = ~(control | (mxcsr >> _SSE_EMASK_SHIFT)) & FE_ALL_EXCEPT;
+	control |= mask;
+	__asm__ __volatile__ ("fldcw %0" : : "m" (control));
+
+	mxcsr |= mask << _SSE_EMASK_SHIFT;
+	__asm__ __volatile__ ("ldmxcsr %0" : : "m" (mxcsr));
+
+	return (omask);
+}
+
+int
+fegetexcept(void)
+{
+	unsigned short control;
+
+	/*
+	 * We assume that the masks for the x87 and the SSE unit are
+	 * the same.
+	 */
+	__asm__ __volatile__ ("fnstcw %0" : "=m" (control));
+
+	return (~control & FE_ALL_EXCEPT);
+}
diff --git a/sys/arch/amd64/include/fenv.h b/sys/arch/amd64/include/fenv.h
new file mode 100644
index 00000000000..9f9af5f52bf
--- /dev/null
+++ b/sys/arch/amd64/include/fenv.h
@@ -0,0 +1,105 @@
+/*	$OpenBSD: fenv.h,v 1.1 2011/04/21 21:12:56 martynas Exp $	*/
+/*	$NetBSD: fenv.h,v 1.1 2010/07/31 21:47:54 joerg Exp $	*/
+
+/*-
+ * Copyright (c) 2004-2005 David Schultz <das (at) FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef	_AMD64_FENV_H_
+#define	_AMD64_FENV_H_
+
+/*
+ * Each symbol representing a floating point exception expands to an integer
+ * constant expression with values, such that bitwise-inclusive ORs of _all
+ * combinations_ of the constants result in distinct values.
+ *
+ * We use such values that allow direct bitwise operations on FPU/SSE registers.
+ */
+#define	FE_INVALID		0x01
+#define	FE_DENORMAL		0x02
+#define	FE_DIVBYZERO		0x04
+#define	FE_OVERFLOW		0x08
+#define	FE_UNDERFLOW		0x10
+#define	FE_INEXACT		0x20
+
+/*
+ * The following symbol is simply the bitwise-inclusive OR of all floating-point
+ * exception constants defined above.
+ */
+#define	FE_ALL_EXCEPT		\
+	(FE_DIVBYZERO | FE_INEXACT | FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
+
+/*
+ * Each symbol representing the rounding direction, expands to an integer
+ * constant expression whose value is distinct non-negative value.
+ *
+ * We use such values that allow direct bitwise operations on FPU/SSE registers.
+ */
+#define	FE_TONEAREST		0x000
+#define	FE_DOWNWARD		0x400
+#define	FE_UPWARD		0x800
+#define	FE_TOWARDZERO		0xC00
+
+/*
+ * As compared to the x87 control word, the SSE unit's control word
+ * has the rounding control bits offset by 3 and the exception mask
+ * bits offset by 7.
+ */
+#define	_X87_ROUND_MASK		0xC00
+#define	_SSE_ROUND_MASK		(0xC00 << 3)
+#define	_SSE_ROUND_SHIFT	3
+#define	_SSE_EMASK_SHIFT	7
+
+/*
+ * fenv_t represents the entire floating-point environment
+ */
+typedef struct {
+	struct {
+		unsigned int __control;		/* Control word register */
+		unsigned int __status;		/* Status word register */
+		unsigned int __tag;		/* Tag word register */
+		unsigned int __others[4];	/* EIP, Pointer Selector, etc */
+	} __x87;
+	unsigned int __mxcsr;			/* Control, status register */
+} fenv_t;
+
+extern fenv_t			__fe_dfl_env;
+#define	FE_DFL_ENV		((const fenv_t *) &__fe_dfl_env)
+
+/*
+ * fexcept_t represents the floating-point status flags collectively, including
+ * any status the implementation associates with the flags.
+ *
+ * A floating-point status flag is a system variable whose value is set (but
+ * never cleared) when a floating-point exception is raised, which occurs as a
+ * side effect of exceptional floating-point arithmetic to provide auxiliary
+ * information.
+ *
+ * A floating-point control mode is a system variable whose value may be set by
+ * the user to affect the subsequent behavior of floating-point arithmetic.
+ */
+typedef unsigned int fexcept_t;
+
+#endif	/* ! _AMD64_FENV_H_ */