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authorJonathan Gray <jsg@cvs.openbsd.org>2016-05-07 00:18:24 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2016-05-07 00:18:24 +0000
commit43527fb0c88b50646a467483b142ce5ba8bb1fcf (patch)
tree2897ac15065daf9ed89da212f7af09fcc734402a
parent915b4b7c1d8c66dce578cc9d74a426cc894fd286 (diff)
set the high speed enable bit if the timing isn't SDMMC_TIMING_LEGACY
ok patrick@ kettenis@
-rw-r--r--sys/arch/armv7/omap/ommmc.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/sys/arch/armv7/omap/ommmc.c b/sys/arch/armv7/omap/ommmc.c
index 1e7329375e5..a38fa89d358 100644
--- a/sys/arch/armv7/omap/ommmc.c
+++ b/sys/arch/armv7/omap/ommmc.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ommmc.c,v 1.19 2016/05/05 11:01:08 kettenis Exp $ */
+/* $OpenBSD: ommmc.c,v 1.20 2016/05/07 00:18:23 jsg Exp $ */
/*
* Copyright (c) 2009 Dale Rahn <drahn@openbsd.org>
@@ -674,6 +674,11 @@ ommmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)
reg |= div << MMCHS_SYSCTL_CLKD_SH;
HWRITE4(sc, MMCHS_SYSCTL, reg);
+ if (timing == SDMMC_TIMING_LEGACY)
+ HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE);
+ else
+ HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE);
+
/*
* Start internal clock. Wait 10ms for stabilization.
*/