spaces/tabs cleanup

2 files changed, 95 insertions, 101 deletions

diff --git a/sys/dev/ic/wdcreg.h b/sys/dev/ic/wdcreg.h
index a4a46a05a61..f913da83b83 100644
--- a/sys/dev/ic/wdcreg.h
+++ b/sys/dev/ic/wdcreg.h
@@ -1,4 +1,4 @@
-/*      $OpenBSD: wdcreg.h,v 1.9 2003/09/28 21:01:43 grange Exp $     */
+/*      $OpenBSD: wdcreg.h,v 1.10 2003/10/16 14:15:41 grange Exp $     */
 /*	$NetBSD: wdcreg.h,v 1.22 1999/03/07 14:02:54 bouyer Exp $	*/
 
 /*-
@@ -38,68 +38,65 @@
 /*
  * Controller register (wdr_ctlr)
  */
-#define  WDCTL_4BIT	 0x08	/* use four head bits (wd1003) */
-#define  WDCTL_RST	 0x04	/* reset the controller */
-#define  WDCTL_IDS	 0x02	/* disable controller interrupts */
-#if 0 /* NOT MAPPED; fd uses this register on PCs */
-#define	wd_digin	1	/* disk controller input (R) */
-#endif
+#define WDCTL_4BIT	0x08	/* use four head bits (wd1003) */
+#define WDCTL_RST	0x04	/* reset the controller */
+#define WDCTL_IDS	0x02	/* disable controller interrupts */
 
 /*
  * Status bits.
  */
-#define	WDCS_BSY	0x80	/* busy */
-#define	WDCS_DRDY	0x40	/* drive ready */
-#define	WDCS_DWF	0x20	/* drive write fault */
-#define	WDCS_DSC	0x10	/* drive seek complete */
-#define	WDCS_DRQ	0x08	/* data request */
-#define	WDCS_CORR	0x04	/* corrected data */
-#define	WDCS_IDX	0x02	/* index */
-#define	WDCS_ERR	0x01	/* error */
+#define WDCS_BSY	0x80	/* busy */
+#define WDCS_DRDY	0x40	/* drive ready */
+#define WDCS_DWF	0x20	/* drive write fault */
+#define WDCS_DSC	0x10	/* drive seek complete */
+#define WDCS_DRQ	0x08	/* data request */
+#define WDCS_CORR	0x04	/* corrected data */
+#define WDCS_IDX	0x02	/* index */
+#define WDCS_ERR	0x01	/* error */
 #define WDCS_BITS	"\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err"
 
 /*
  * Error bits.
  */
-#define	WDCE_BBK	0x80	/* bad block detected */
-#define	WDCE_CRC	0x80	/* CRC error (Ultra-DMA only) */
-#define	WDCE_UNC	0x40	/* uncorrectable data error */
-#define	WDCE_MC		0x20	/* media changed */
-#define	WDCE_IDNF	0x10	/* id not found */
-#define	WDCE_MCR	0x08	/* media change requested */
-#define	WDCE_ABRT	0x04	/* aborted command */
-#define	WDCE_TK0NF	0x02	/* track 0 not found */
-#define	WDCE_AMNF	0x01	/* address mark not found */
+#define WDCE_BBK	0x80	/* bad block detected */
+#define WDCE_CRC	0x80	/* CRC error (Ultra-DMA only) */
+#define WDCE_UNC	0x40	/* uncorrectable data error */
+#define WDCE_MC		0x20	/* media changed */
+#define WDCE_IDNF	0x10	/* id not found */
+#define WDCE_MCR	0x08	/* media change requested */
+#define WDCE_ABRT	0x04	/* aborted command */
+#define WDCE_TK0NF	0x02	/* track 0 not found */
+#define WDCE_AMNF	0x01	/* address mark not found */
 
 /*
  * Commands for Disk Controller.
  */
 #define WDCC_NOP	0x00	/* NOP - Always fail with "aborted command" */
-#define	WDCC_RECAL	0x10	/* disk restore code -- resets cntlr */
+#define WDCC_RECAL	0x10	/* disk restore code -- resets cntlr */
 
-#define	WDCC_READ	0x20	/* disk read code */
-#define	WDCC_WRITE	0x30	/* disk write code */
-#define	 WDCC__LONG	 0x02	 /* modifier -- access ecc bytes */
-#define	 WDCC__NORETRY	 0x01	 /* modifier -- no retrys */
+#define WDCC_READ	0x20	/* disk read code */
+#define WDCC_WRITE	0x30	/* disk write code */
+#define WDCC__LONG	0x02	/* modifier -- access ecc bytes */
+#define WDCC__NORETRY	0x01	/* modifier -- no retrys */
 
-#define	WDCC_FORMAT	0x50	/* disk format code */
-#define	WDCC_DIAGNOSE	0x90	/* controller diagnostic */
-#define	WDCC_IDP	0x91	/* initialize drive parameters */
+#define WDCC_FORMAT	0x50	/* disk format code */
+#define WDCC_DIAGNOSE	0x90	/* controller diagnostic */
+#define WDCC_IDP	0x91	/* initialize drive parameters */
 
-#define	WDCC_READMULTI	0xc4	/* read multiple */
-#define	WDCC_WRITEMULTI	0xc5	/* write multiple */
-#define	WDCC_SETMULTI	0xc6	/* set multiple mode */
+#define WDCC_READMULTI	0xc4	/* read multiple */
+#define WDCC_WRITEMULTI	0xc5	/* write multiple */
+#define WDCC_SETMULTI	0xc6	/* set multiple mode */
 
-#define	WDCC_READDMA	0xc8	/* read with DMA */
-#define	WDCC_WRITEDMA	0xca	/* write with DMA */
+#define WDCC_READDMA	0xc8	/* read with DMA */
+#define WDCC_WRITEDMA	0xca	/* write with DMA */
 
-#define	WDCC_ACKMC	0xdb	/* acknowledge media change */
-#define	WDCC_LOCK	0xde	/* lock drawer */
-#define	WDCC_UNLOCK	0xdf	/* unlock drawer */
+#define WDCC_ACKMC	0xdb	/* acknowledge media change */
+#define WDCC_LOCK	0xde	/* lock drawer */
+#define WDCC_UNLOCK	0xdf	/* unlock drawer */
 
-#define	WDCC_FLUSHCACHE	0xe7	/* Flush cache */
-#define	WDCC_IDENTIFY	0xec	/* read parameters from controller */
-#define	SET_FEATURES	0xef	/* set features */
+#define WDCC_FLUSHCACHE	0xe7	/* Flush cache */
+#define WDCC_IDENTIFY	0xec	/* read parameters from controller */
+#define SET_FEATURES	0xef	/* set features */
 
 #define WDCC_IDLE	0xe3	/* set idle timer & enter idle mode */
 #define WDCC_IDLE_IMMED	0xe1	/* enter idle mode */
@@ -120,7 +117,7 @@
 /* Subcommands for SET_FEATURES (features register ) */
 #define WDSF_8BIT_PIO_EN	0x01 /* Enable 8bit PIO (CFA featureset) */
 #define WDSF_EN_WR_CACHE	0x02
-#define WDSF_SET_MODE    	0x03
+#define WDSF_SET_MODE		0x03
 #define WDSF_REASSIGN_EN	0x04 /* Obsolete in ATA-6 */
 #define WDSF_APM_EN		0x05 /* Enable Adv. Power Management */
 #define WDSF_PUIS_EN		0x06 /* Enable Power-Up In Standby */
@@ -148,14 +145,14 @@
 #define WDSF_READAHEAD_EN	0xAA
 #define WDSF_PREFETCH_SET	0xAB /* Obsolete in ATA-6 */
 #define WDSF_AAM_DS		0xC2 /* Disable Autom. Acoustic Management */
-#define WDSF_POD_EN             0xCC
+#define WDSF_POD_EN		0xCC
 #define WDSF_RLSE_DS		0xDD /* Disable release interrupt */
 #define WDSF_SRV_DS		0xDE /* Disable SERVICE interrupt */
 
 /* parameters uploaded to device/heads register */
-#define	WDSD_IBM	0xa0	/* forced to 512 byte sector, ecc */
-#define	WDSD_CHS	0x00	/* cylinder/head/sector addressing */
-#define	WDSD_LBA	0x40	/* logical block addressing */
+#define WDSD_IBM	0xa0	/* forced to 512 byte sector, ecc */
+#define WDSD_CHS	0x00	/* cylinder/head/sector addressing */
+#define WDSD_LBA	0x40	/* logical block addressing */
 
 /* Commands for ATAPI devices */
 #define ATAPI_CHECK_POWER_MODE	0xe5
@@ -165,7 +162,7 @@
 #define ATAPI_PKT_CMD		0xa0
 #define ATAPI_IDENTIFY_DEVICE	0xa1
 #define ATAPI_SOFT_RESET	0x08
-#define ATAPI_DEVICE_RESET      0x08 /* ATA/ATAPI-5 name for soft reset */
+#define ATAPI_DEVICE_RESET	0x08 /* ATA/ATAPI-5 name for soft reset */
 #define ATAPI_SLEEP		0xe6
 #define ATAPI_STANDBY_IMMEDIATE	0xe0
 #define ATAPI_SMART		0xB0 /* SMART operations */
@@ -175,18 +172,16 @@
 #define ATAPI_WRITEMULTIEXT	0x39 /* Write Multi Ext */
 
 /* Bytes used by ATAPI_PACKET_COMMAND ( feature register) */
-#define ATAPI_PKT_CMD_FTRE_DMA 0x01
-#define ATAPI_PKT_CMD_FTRE_OVL 0x02
+#define ATAPI_PKT_CMD_FTRE_DMA	0x01
+#define ATAPI_PKT_CMD_FTRE_OVL	0x02
 
 /* ireason */
-#define WDCI_CMD         0x01    /* command(1) or data(0) */
-#define WDCI_IN          0x02    /* transfer to(1) or from(0) the host */
-#define WDCI_RELEASE     0x04    /* bus released until completion */
-
-#define PHASE_CMDOUT    (WDCS_DRQ | WDCI_CMD)
-#define PHASE_DATAIN    (WDCS_DRQ | WDCI_IN)
-#define PHASE_DATAOUT   WDCS_DRQ
-#define PHASE_COMPLETED (WDCI_IN | WDCI_CMD)
-#define PHASE_ABORTED   0
-
-
+#define WDCI_CMD	0x01 /* command(1) or data(0) */
+#define WDCI_IN		0x02 /* transfer to(1) or from(0) the host */
+#define WDCI_RELEASE	0x04 /* bus released until completion */
+
+#define PHASE_CMDOUT	(WDCS_DRQ | WDCI_CMD)
+#define PHASE_DATAIN	(WDCS_DRQ | WDCI_IN)
+#define PHASE_DATAOUT	WDCS_DRQ
+#define PHASE_COMPLETED	(WDCI_IN | WDCI_CMD)
+#define PHASE_ABORTED	0
diff --git a/sys/dev/ic/wdcvar.h b/sys/dev/ic/wdcvar.h
index ae01770b1bf..6970e8ba61b 100644
--- a/sys/dev/ic/wdcvar.h
+++ b/sys/dev/ic/wdcvar.h
@@ -1,4 +1,4 @@
-/*      $OpenBSD: wdcvar.h,v 1.28 2003/09/28 21:01:43 grange Exp $     */
+/*      $OpenBSD: wdcvar.h,v 1.29 2003/10/16 14:15:41 grange Exp $     */
 /*	$NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $	*/
 
 /*-
@@ -65,10 +65,10 @@ struct channel_softc { /* Per channel data */
 	bus_space_handle_t      data32ioh;
 	/* Our state */
 	int ch_flags;
-#define WDCF_ACTIVE   0x01	/* channel is active */
-#define WDCF_ONESLAVE 0x02      /* slave-only channel */
-#define WDCF_IRQ_WAIT 0x10	/* controller is waiting for irq */
-#define WDCF_VERBOSE_PROBE 0x40 /* verbose probe */
+#define WDCF_ACTIVE		0x01 /* channel is active */
+#define WDCF_ONESLAVE		0x02 /* slave-only channel */
+#define WDCF_IRQ_WAIT		0x10 /* controller is waiting for irq */
+#define WDCF_VERBOSE_PROBE	0x40 /* verbose probe */
 	u_int8_t ch_status;         /* copy of status register */
 	u_int8_t ch_prev_log_status; /* previous logged value of status reg */
 	u_int8_t ch_log_idx;
@@ -88,7 +88,7 @@ struct channel_softc { /* Per channel data */
  * Disk Controller register definitions.
  */
 #define _WDC_REGMASK 7
-#define _WDC_AUX 8
+#define _WDC_AUX     8
 #define _WDC_RDONLY  16
 #define _WDC_WRONLY  32
 enum wdc_regs {
@@ -130,9 +130,9 @@ struct channel_softc_vtbl {
 #define CHP_READ_REG(chp, a)  ((chp)->_vtbl->read_reg)(chp, a)
 #define CHP_WRITE_REG(chp, a, b)  ((chp)->_vtbl->write_reg)(chp, a, b)
 #define CHP_READ_RAW_MULTI_2(chp, a, b)  \
-        ((chp)->_vtbl->read_raw_multi_2)(chp, a, b)
+	((chp)->_vtbl->read_raw_multi_2)(chp, a, b)
 #define CHP_WRITE_RAW_MULTI_2(chp, a, b)  \
-        ((chp)->_vtbl->write_raw_multi_2)(chp, a, b)
+	((chp)->_vtbl->write_raw_multi_2)(chp, a, b)
 #define CHP_READ_RAW_MULTI_4(chp, a, b)  \
 	((chp)->_vtbl->read_raw_multi_4)(chp, a, b)
 #define CHP_WRITE_RAW_MULTI_4(chp, a, b)  \
@@ -143,17 +143,17 @@ struct wdc_softc { /* Per controller state */
 	/* mandatory fields */
 	int           cap;
 /* Capabilities supported by the controller */
-#define	WDC_CAPABILITY_DATA16 0x0001    /* can do  16-bit data access */
-#define	WDC_CAPABILITY_DATA32 0x0002    /* can do 32-bit data access */
+#define WDC_CAPABILITY_DATA16 0x0001	/* can do  16-bit data access */
+#define WDC_CAPABILITY_DATA32 0x0002	/* can do 32-bit data access */
 #define WDC_CAPABILITY_MODE   0x0004	/* controller knows its PIO/DMA modes */
-#define	WDC_CAPABILITY_DMA    0x0008	/* DMA */
-#define	WDC_CAPABILITY_UDMA   0x0010	/* Ultra-DMA/33 */
-#define	WDC_CAPABILITY_HWLOCK 0x0020	/* Needs to lock HW */
-#define	WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */
-#define	WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */
+#define WDC_CAPABILITY_DMA    0x0008	/* DMA */
+#define WDC_CAPABILITY_UDMA   0x0010	/* Ultra-DMA/33 */
+#define WDC_CAPABILITY_HWLOCK 0x0020	/* Needs to lock HW */
+#define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */
+#define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */
 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
-#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
-#define WDC_CAPABILITY_IRQACK 0x0400    /* callback to ack interrupt */
+#define WDC_CAPABILITY_PREATA 0x0200	/* ctrl can be a pre-ata one */
+#define WDC_CAPABILITY_IRQACK 0x0400	/* callback to ack interrupt */
 #define WDC_CAPABILITY_SINGLE_DRIVE 0x800 /* Don't proble second drive */
 #define WDC_CAPABILITY_NO_ATAPI_DMA 0x1000 /* Don't do DMA with ATAPI */
 	u_int8_t      PIO_cap; /* highest PIO mode supported */
@@ -180,16 +180,16 @@ struct wdc_softc { /* Per controller state */
 #define WDC_DMA_IRQW	0x02
 #define WDC_DMA_LBA48	0x04
 	int             dma_status; /* status return from dma_finish() */
-#define WDC_DMAST_NOIRQ 0x01    /* missing IRQ */
-#define WDC_DMAST_ERR   0x02    /* DMA error */
-#define WDC_DMAST_UNDER 0x04    /* DMA underrun */
+#define WDC_DMAST_NOIRQ	0x01 /* missing IRQ */
+#define WDC_DMAST_ERR	0x02 /* DMA error */
+#define WDC_DMAST_UNDER	0x04 /* DMA underrun */
 
 	/* if WDC_CAPABILITY_HWLOCK set in 'cap' */
-	int            (*claim_hw)(void *, int);
+	int             (*claim_hw)(void *, int);
 	void            (*free_hw)(void *);
 
 	/* if WDC_CAPABILITY_MODE set in 'cap' */
-	void 		(*set_modes)(struct channel_softc *);
+	void            (*set_modes)(struct channel_softc *);
 
 	/* if WDC_CAPABILITY_IRQACK set in 'cap' */
 	void            (*irqack)(struct channel_softc *);
@@ -203,14 +203,14 @@ struct atapi_return_args;
 
 struct wdc_xfer {
 	volatile u_int c_flags;
-#define C_ATAPI  	0x0002 /* xfer is ATAPI request */
-#define C_TIMEOU  	0x0004 /* xfer processing timed out */
-#define C_NEEDDONE  	0x0010 /* need to call upper-level done */
+#define C_ATAPI		0x0002 /* xfer is ATAPI request */
+#define C_TIMEOU	0x0004 /* xfer processing timed out */
+#define C_NEEDDONE	0x0010 /* need to call upper-level done */
 #define C_POLL		0x0020 /* cmd is polled */
 #define C_DMA		0x0040 /* cmd uses DMA */
 #define C_SENSE		0x0080 /* cmd is a internal command */
-#define C_MEDIA_ACCESS  0x0100 /* is a media access command */
-#define C_POLL_MACHINE  0x0200 /* machine has a poll hander */
+#define C_MEDIA_ACCESS	0x0100 /* is a media access command */
+#define C_POLL_MACHINE	0x0200 /* machine has a poll hander */
 
 	/* Informations about our location */
 	struct channel_softc *chp;
@@ -228,7 +228,7 @@ struct wdc_xfer {
         void (*c_kill_xfer)(struct channel_softc *, struct wdc_xfer *);
 
 	/* Used by ATAPISCSI */
- 	volatile int endticks;
+	volatile int endticks;
 	struct timeout atapi_poll_to;
 	void (*next)(struct channel_softc *, struct wdc_xfer *, int,
 			 struct atapi_return_args *);
@@ -251,27 +251,27 @@ int   wdcactivate(struct device *, enum devact);
 int   wdcintr(void *);
 void  wdc_exec_xfer(struct channel_softc *, struct wdc_xfer *);
 struct wdc_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */
-#define WDC_CANSLEEP 0x00
-#define WDC_NOSLEEP 0x01
+#define WDC_CANSLEEP	0x00
+#define WDC_NOSLEEP	0x01
 void   wdc_free_xfer(struct channel_softc *, struct wdc_xfer *);
 void  wdcstart(struct channel_softc *);
 void  wdcrestart(void *);
 int   wdcreset(struct channel_softc *, int);
-#define VERBOSE 1
-#define SILENT 0 /* wdcreset will not print errors */
+#define VERBOSE	1
+#define SILENT	0 /* wdcreset will not print errors */
 int   wdc_wait_for_status(struct channel_softc *, int, int, int);
 int   wdc_dmawait(struct channel_softc *, struct wdc_xfer *, int);
 void  wdcbit_bucket(struct channel_softc *, int);
 
 void  wdccommand(struct channel_softc *, u_int8_t, u_int8_t, u_int16_t,
-	                  u_int8_t, u_int8_t, u_int8_t, u_int8_t);
+	u_int8_t, u_int8_t, u_int8_t, u_int8_t);
 void  wdccommandext(struct channel_softc *, u_int8_t, u_int8_t, u_int64_t,
-		    u_int16_t);
-void   wdccommandshort(struct channel_softc *, int, int);
+	u_int16_t);
+void  wdccommandshort(struct channel_softc *, int, int);
 void  wdctimeout(void *arg);
 
-int	wdc_addref(struct channel_softc *);
-void	wdc_delref(struct channel_softc *);
+int   wdc_addref(struct channel_softc *);
+void  wdc_delref(struct channel_softc *);
 
 /*
  * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
@@ -279,7 +279,7 @@ void	wdc_delref(struct channel_softc *);
  */
 #define wdcwait(chp, status, mask, timeout) ((wdc_wait_for_status((chp), (status), (mask), (timeout)) >= 0) ? 0 : -1)
 #define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout))
-#define wait_for_unbusy(chp, timeout)	wdcwait((chp), 0, 0, (timeout))
+#define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout))
 #define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \
 	WDCS_DRDY, (timeout))
 
@@ -298,4 +298,3 @@ void wdc_input_bytes(struct ata_drive_datas *drvp, void *, unsigned int);
 void wdc_print_current_modes(struct channel_softc *);
 
 int wdc_ioctl(struct ata_drive_datas *, u_long, caddr_t, int, struct proc *);
-