replace strange Linux-style u8/u16/u32/u64/s32 integer types with the

standard C99 uint*_t/int*_t types (i don't get why these drivers
always use their own types when there is a well-defined standard).

7 files changed, 654 insertions, 662 deletions

diff --git a/sys/dev/pci/if_ix.c b/sys/dev/pci/if_ix.c
index 21318c1e697..b0ea80da03d 100644
--- a/sys/dev/pci/if_ix.c
+++ b/sys/dev/pci/if_ix.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_ix.c,v 1.1 2008/06/08 20:01:02 reyk Exp $	*/
+/*	$OpenBSD: if_ix.c,v 1.2 2008/06/08 20:33:51 reyk Exp $	*/
 
 /******************************************************************************
 
@@ -100,9 +100,9 @@ void	ixgbe_free_receive_buffers(struct rx_ring *);
 void	ixgbe_enable_intr(struct ix_softc *);
 void	ixgbe_disable_intr(struct ix_softc *);
 void	ixgbe_update_stats_counters(struct ix_softc *);
-bool	ixgbe_txeof(struct tx_ring *);
-bool	ixgbe_rxeof(struct rx_ring *, int);
-void	ixgbe_rx_checksum(struct ix_softc *, u32, struct mbuf *);
+int	ixgbe_txeof(struct tx_ring *);
+int	ixgbe_rxeof(struct rx_ring *, int);
+void	ixgbe_rx_checksum(struct ix_softc *, uint32_t, struct mbuf *);
 void	ixgbe_set_promisc(struct ix_softc *);
 void	ixgbe_disable_promisc(struct ix_softc *);
 void	ixgbe_set_multi(struct ix_softc *);
@@ -123,12 +123,12 @@ int	ixgbe_dma_malloc(struct ix_softc *, bus_size_t,
 		    struct ixgbe_dma_alloc *, int);
 void	ixgbe_dma_free(struct ix_softc *, struct ixgbe_dma_alloc *);
 #ifdef IX_CSUM_OFFLOAD
-boolean_t ixgbe_tx_ctx_setup(struct tx_ring *, struct mbuf *);
-boolean_t ixgbe_tso_setup(struct tx_ring *, struct mbuf *, u32 *);
+int ixgbe_tx_ctx_setup(struct tx_ring *, struct mbuf *);
+int ixgbe_tso_setup(struct tx_ring *, struct mbuf *, uint32_t *);
 #endif
-void	ixgbe_set_ivar(struct ix_softc *, u16, u8);
+void	ixgbe_set_ivar(struct ix_softc *, uint16_t, uint8_t);
 void	ixgbe_configure_ivars(struct ix_softc *);
-u8	*ixgbe_mc_array_itr(struct ixgbe_hw *, u8 **, u32 *);
+uint8_t	*ixgbe_mc_array_itr(struct ixgbe_hw *, uint8_t **, uint32_t *);
 
 /* Legacy (single vector interrupt handler */
 int	ixgbe_legacy_irq(void *);
@@ -195,7 +195,7 @@ ixgbe_attach(struct device *parent, struct device *self, void *aux)
 	struct pci_attach_args	*pa = (struct pci_attach_args *)aux;
 	struct ix_softc		*sc = (struct ix_softc *)self;
 	int			 error = 0;
-	u32			 ctrl_ext;
+	uint32_t			 ctrl_ext;
 
 	INIT_DEBUGOUT("ixgbe_attach: begin");
 
@@ -286,7 +286,7 @@ ixgbe_detach(struct device *self, int flags)
 {
 	struct ix_softc *sc = (struct ix_softc *)self;
 	struct ifnet *ifp = &sc->arpcom.ac_if;
-	u32	ctrl_ext;
+	uint32_t	ctrl_ext;
 
 	INIT_DEBUGOUT("ixgbe_detach: begin");
 
@@ -389,7 +389,7 @@ ixgbe_start(struct ifnet *ifp)
 {
 	struct ix_softc *sc = ifp->if_softc;
 	struct tx_ring	*txr = sc->tx_rings;
-	u32 queue = 0;
+	uint32_t queue = 0;
 
 #if 0
 	/*
@@ -518,7 +518,7 @@ ixgbe_watchdog(struct ifnet * ifp)
 	struct ix_softc *sc = (struct ix_softc *)ifp->if_softc;
 	struct tx_ring *txr = sc->tx_rings;
 	struct ixgbe_hw *hw = &sc->hw;
-	bool		tx_hang = FALSE;
+	int		tx_hang = FALSE;
 	int		i;
 
         /*
@@ -583,7 +583,7 @@ ixgbe_init(void *arg)
 {
 	struct ix_softc	*sc = (struct ix_softc *)arg;
 	struct ifnet	*ifp = &sc->arpcom.ac_if;
-	u32		 txdctl, rxdctl, mhadd, gpie;
+	uint32_t	 txdctl, rxdctl, mhadd, gpie;
 	int		 i, s;
 
 	INIT_DEBUGOUT("ixgbe_init: begin");
@@ -706,7 +706,7 @@ ixgbe_legacy_irq(void *arg)
 {
 	struct ix_softc	*sc = (struct ix_softc *)arg;
 	struct ifnet	*ifp = &sc->arpcom.ac_if;
-	u32       	 reg_eicr;
+	uint32_t	 reg_eicr;
 	struct tx_ring	*txr = sc->tx_rings;
 	struct rx_ring	*rxr = sc->rx_rings;
 	struct ixgbe_hw	*hw = &sc->hw;
@@ -828,15 +828,15 @@ ixgbe_media_change(struct ifnet * ifp)
 int
 ixgbe_encap(struct tx_ring *txr, struct mbuf *m_head)
 {
-	struct ix_softc  *sc = txr->sc;
-	u32		olinfo_status = 0, cmd_type_len = 0;
+	struct ix_softc *sc = txr->sc;
+	uint32_t	olinfo_status = 0, cmd_type_len = 0;
 	int             i, j, error;
 	int		first, last = 0;
 	bus_dmamap_t	map;
 	struct ixgbe_tx_buf *txbuf, *txbuf_mapped;
 	union ixgbe_adv_tx_desc *txd = NULL;
 #ifdef IX_CSUM_OFFLOAD
-	u32		paylen = 0;
+	uint32_t	paylen = 0;
 #endif
 
 	/* Basic descriptor defines */
@@ -973,7 +973,7 @@ void
 ixgbe_set_promisc(struct ix_softc *sc)
 {
 
-	u_int32_t       reg_rctl;
+	uint32_t       reg_rctl;
 	struct ifnet *ifp = &sc->arpcom.ac_if;
 
 	reg_rctl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL);
@@ -992,7 +992,7 @@ ixgbe_set_promisc(struct ix_softc *sc)
 void
 ixgbe_disable_promisc(struct ix_softc * sc)
 {
-	u_int32_t       reg_rctl;
+	uint32_t       reg_rctl;
 
 	reg_rctl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL);
 
@@ -1015,9 +1015,9 @@ ixgbe_disable_promisc(struct ix_softc * sc)
 void
 ixgbe_set_multi(struct ix_softc *sc)
 {
-	u32	fctrl;
-	u8	mta[MAX_NUM_MULTICAST_ADDRESSES * IXGBE_ETH_LENGTH_OF_ADDRESS];
-	u8	*update_ptr;
+	uint32_t	fctrl;
+	uint8_t	mta[MAX_NUM_MULTICAST_ADDRESSES * IXGBE_ETH_LENGTH_OF_ADDRESS];
+	uint8_t	*update_ptr;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	int	mcnt = 0;
@@ -1064,11 +1064,11 @@ ixgbe_set_multi(struct ix_softc *sc)
  * shared code. It simply feeds the shared code routine the
  * addresses in the array of ixgbe_set_multi() one by one.
  */
-u8 *
-ixgbe_mc_array_itr(struct ixgbe_hw *hw, u8 **update_ptr, u32 *vmdq)
+uint8_t *
+ixgbe_mc_array_itr(struct ixgbe_hw *hw, uint8_t **update_ptr, uint32_t *vmdq)
 {
-	u8 *addr = *update_ptr;
-	u8 *newptr;
+	uint8_t *addr = *update_ptr;
+	uint8_t *newptr;
 	*vmdq = 0;
 
 	newptr = addr + IXGBE_ETH_LENGTH_OF_ADDRESS;
@@ -1113,7 +1113,7 @@ ixgbe_local_timer(void *arg)
 void
 ixgbe_update_link_status(struct ix_softc *sc)
 {
-	boolean_t link_up = FALSE;
+	int link_up = FALSE;
 	struct ifnet *ifp = &sc->arpcom.ac_if;
 	struct tx_ring *txr = sc->tx_rings;
 	int		i;
@@ -1198,7 +1198,7 @@ ixgbe_identify_hardware(struct ix_softc *sc)
 {
 	struct ixgbe_osdep	*os = &sc->osdep;
 	struct pci_attach_args	*pa = os->os_pa;
-	u_int32_t		 reg;
+	uint32_t		 reg;
 
 	/* Save off the information about this board */
 	sc->hw.vendor_id = PCI_VENDOR(pa->pa_id);
@@ -1449,7 +1449,7 @@ ixgbe_allocate_pci_resources(struct ix_softc *sc)
 		printf(": cannot find mem space\n");
 		return (ENXIO);
 	}
-	sc->hw.hw_addr = (u8 *)os->os_membase;
+	sc->hw.hw_addr = (uint8_t *)os->os_membase;
 
 	/*
 	 * Init the resource arrays
@@ -1536,7 +1536,7 @@ int
 ixgbe_hardware_init(struct ix_softc *sc)
 {
 	struct ifnet	*ifp = &sc->arpcom.ac_if;
-	u16 csum;
+	uint16_t csum;
 
 	csum = 0;
 	/* Issue a global reset */
@@ -1773,14 +1773,14 @@ ixgbe_allocate_queues(struct ix_softc *sc)
 		txr->tx_base = (union ixgbe_adv_tx_desc *)txr->txdma.dma_vaddr;
 		bzero((void *)txr->tx_base, tsize);
 
-		if (ixgbe_dma_malloc(sc, sizeof(u_int32_t),
+		if (ixgbe_dma_malloc(sc, sizeof(uint32_t),
 		    &txr->txwbdma, BUS_DMA_NOWAIT)) {
 			printf("%s: Unable to allocate TX Write Back memory\n",
 			    ifp->if_xname);
 			error = ENOMEM;
 			goto err_tx_desc;
 		}
-		txr->tx_hwb = (u_int32_t *)txr->txwbdma.dma_vaddr;
+		txr->tx_hwb = (uint32_t *)txr->txwbdma.dma_vaddr;
 		*txr->tx_hwb = 0;
 
         	/* Now allocate transmit buffers for the ring */
@@ -1957,8 +1957,8 @@ ixgbe_initialize_transmit_units(struct ix_softc *sc)
 	struct tx_ring	*txr;
 	struct ixgbe_hw	*hw = &sc->hw;
 	int		 i;
-	u64		 tdba, txhwb;
-	u32		 txctrl;
+	uint64_t	 tdba, txhwb;
+	uint32_t	 txctrl;
 
 	/* Setup the Base and Length of the Tx Descriptor Ring */
 
@@ -2075,20 +2075,20 @@ ixgbe_free_transmit_buffers(struct tx_ring *txr)
  *
  **********************************************************************/
 
-boolean_t
+int
 ixgbe_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp)
 {
 	struct ix_softc *sc = txr->sc;
 	struct ifnet	*ifp = &sc->arpcom.ac_if;
 	struct ixgbe_adv_tx_context_desc *TXD;
 	struct ixgbe_tx_buf        *tx_buffer;
-	u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
+	uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0;
 	struct ip *ip;
 	struct ip6_hdr *ip6;
 	int  ehdrlen, ip_hlen = 0;
-	u16	etype;
-	u8	ipproto = 0;
-	bool	offload = TRUE;
+	uint16_t etype;
+	uint8_t ipproto = 0;
+	int offload = TRUE;
 	int ctxd = txr->next_avail_tx_desc;
 #if NVLAN > 0
 	struct ether_vlan_header *eh;
@@ -2213,17 +2213,17 @@ ixgbe_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp)
  *  scs using advanced tx descriptors
  *
  **********************************************************************/
-boolean_t
-ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *paylen)
+int
+ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, uint32_t *paylen)
 {
 	struct ix_softc *sc = txr->sc;
 	struct ixgbe_adv_tx_context_desc *TXD;
 	struct ixgbe_tx_buf        *tx_buffer;
-	u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
-	u32 mss_l4len_idx = 0;
+	uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0;
+	uint32_t mss_l4len_idx = 0;
 	int ctxd, ehdrlen,  hdrlen, ip_hlen, tcp_hlen;
 #if NVLAN > 0
-	u16 vtag = 0;
+	uint16_t vtag = 0;
 	struct ether_vlan_header *eh;
 
 	struct ifvlan		*ifv = NULL;
@@ -2320,8 +2320,8 @@ ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *paylen)
 
 #else	/* For 6.2 RELEASE */
 /* This makes it easy to keep the code common */
-boolean_t
-ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *paylen)
+int
+ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, uint32_t *paylen)
 {
 	return (FALSE);
 }
@@ -2335,12 +2335,12 @@ ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *paylen)
  *  tx_buffer is put back on the free queue.
  *
  **********************************************************************/
-boolean_t
+int
 ixgbe_txeof(struct tx_ring *txr)
 {
 	struct ix_softc			*sc = txr->sc;
 	struct ifnet			*ifp = &sc->arpcom.ac_if;
-	u_int				 first, last, done, num_avail;
+	uint				 first, last, done, num_avail;
 	struct ixgbe_tx_buf		*tx_buffer;
 	struct ixgbe_legacy_tx_desc *tx_desc;
 
@@ -2519,7 +2519,7 @@ ixgbe_get_buf(struct rx_ring *rxr, int i, struct mbuf *nmp)
 #ifndef NO_82598_A0_SUPPORT
         /* A0 needs to One's Compliment descriptors */
 	if (sc->hw.revision_id == 0) {
-        	struct dhack {u32 a1; u32 a2; u32 b1; u32 b2;};
+        	struct dhack {uint32_t a1; uint32_t a2; uint32_t b1; uint32_t b2;};
         	struct dhack *d;   
 
         	d = (struct dhack *)&rxr->rx_base[i];
@@ -2741,12 +2741,11 @@ ixgbe_initialize_receive_units(struct ix_softc *sc)
 {
 	struct	rx_ring	*rxr = sc->rx_rings;
 	struct ifnet   *ifp = &sc->arpcom.ac_if;
-	u32		rxctrl, fctrl, srrctl, rxcsum;
-	u32		reta, mrqc, hlreg, linkvec;
-	u32		random[10];
+	uint32_t	rxctrl, fctrl, srrctl, rxcsum;
+	uint32_t	reta, mrqc, hlreg, linkvec;
+	uint32_t	random[10];
 	int		i;
 
-
 	/*
 	 * Make sure receives are disabled while
 	 * setting up the descriptor ring
@@ -2786,7 +2785,7 @@ ixgbe_initialize_receive_units(struct ix_softc *sc)
 	IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(linkvec), LINK_ITR);
 
 	for (i = 0; i < sc->num_rx_queues; i++, rxr++) {
-		u64 rdba = rxr->rxdma.dma_map->dm_segs[0].ds_addr;
+		uint64_t rdba = rxr->rxdma.dma_map->dm_segs[0].ds_addr;
 		/* Setup the Base and Length of the Rx Descriptor Ring */
 		IXGBE_WRITE_REG(&sc->hw, IXGBE_RDBAL(i),
 			       (rdba & 0x00000000ffffffffULL));
@@ -2945,19 +2944,19 @@ ixgbe_free_receive_buffers(struct rx_ring *rxr)
  *  count < 0.
  *
  *********************************************************************/
-bool
+int
 ixgbe_rxeof(struct rx_ring *rxr, int count)
 {
-	struct ix_softc 		*sc = rxr->sc;
+	struct ix_softc 	*sc = rxr->sc;
 	struct ifnet   		*ifp = &sc->arpcom.ac_if;
 #if 0
 	struct lro_ctrl		*lro = &rxr->lro;
 	struct lro_entry	*queued;
 #endif
 	struct mbuf    		*mp;
-	int             	len, i, eop = 0;
-	u8			accept_frame = 0;
-	u32			staterr;
+	int             	 len, i, eop = 0;
+	uint8_t		 accept_frame = 0;
+	uint32_t		 staterr;
 	union ixgbe_adv_rx_desc	*cur;
 
 	i = rxr->next_to_check;
@@ -3125,11 +3124,11 @@ discard:
  *********************************************************************/
 void
 ixgbe_rx_checksum(struct ix_softc *sc,
-    u32 staterr, struct mbuf * mp)
+    uint32_t staterr, struct mbuf * mp)
 {
 	struct ifnet   	*ifp = &sc->arpcom.ac_if;
-	u16 status = (u16) staterr;
-	u8  errors = (u8) (staterr >> 24);
+	uint16_t status = (uint16_t) staterr;
+	uint8_t  errors = (uint8_t) (staterr >> 24);
 
 	/* Not offloading */
 	if ((ifp->if_capabilities & IFCAP_CSUM_IPv4) == 0) {
@@ -3161,7 +3160,7 @@ ixgbe_rx_checksum(struct ix_softc *sc,
 void
 ixgbe_enable_hw_vlans(struct ix_softc *sc)
 {
-	u32        ctrl;
+	uint32_t	ctrl;
 
 	ixgbe_disable_intr(sc);
 	ctrl = IXGBE_READ_REG(&sc->hw, IXGBE_VLNCTRL);
@@ -3176,7 +3175,7 @@ void
 ixgbe_enable_intr(struct ix_softc *sc)
 {
 	struct ixgbe_hw *hw = &sc->hw;
-	u32 mask = IXGBE_EIMS_ENABLE_MASK;
+	uint32_t mask = IXGBE_EIMS_ENABLE_MASK;
 
 	/* Enable Fan Failure detection */
 	if (hw->phy.media_type == ixgbe_media_type_copper)
@@ -3206,11 +3205,11 @@ ixgbe_disable_intr(struct ix_softc *sc)
 	return;
 }
 
-u16
-ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)
+uint16_t
+ixgbe_read_pci_cfg(struct ixgbe_hw *hw, uint32_t reg)
 {
 	struct pci_attach_args	*pa;
-	u16 value;
+	uint16_t value;
 
 	pa = ((struct ixgbe_osdep *)hw->back)->os_pa;
 
@@ -3221,9 +3220,9 @@ ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)
 }
 
 void
-ixgbe_set_ivar(struct ix_softc *sc, u16 entry, u8 vector)
+ixgbe_set_ivar(struct ix_softc *sc, uint16_t entry, uint8_t vector)
 {
-	u32 ivar, index;
+	uint32_t ivar, index;
 
 	vector |= IXGBE_IVAR_ALLOC_VAL;
 	index = (entry >> 2) & 0x1F;
@@ -3266,7 +3265,7 @@ ixgbe_update_stats_counters(struct ix_softc *sc)
 {
 	struct ifnet   *ifp = &sc->arpcom.ac_if;;
 	struct ixgbe_hw *hw = &sc->hw;
-	u32  missed_rx = 0, bprc, lxon, lxoff, total;
+	uint32_t  missed_rx = 0, bprc, lxon, lxoff, total;
 	int	i;
 
 	sc->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
@@ -3426,7 +3425,7 @@ ixgbe_set_flowcntl(SYSCTL_HANDLER_ARGS)
 void
 desc_flip(void *desc)
 {
-        struct dhack {u32 a1; u32 a2; u32 b1; u32 b2;};
+        struct dhack {uint32_t a1; uint32_t a2; uint32_t b1; uint32_t b2;};
         struct dhack *d;
 
         d = (struct dhack *)desc;
diff --git a/sys/dev/pci/if_ix.h b/sys/dev/pci/if_ix.h
index 42ed5f63f00..26b0bc28b87 100644
--- a/sys/dev/pci/if_ix.h
+++ b/sys/dev/pci/if_ix.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_ix.h,v 1.1 2008/06/08 20:01:02 reyk Exp $	*/
+/*	$OpenBSD: if_ix.h,v 1.2 2008/06/08 20:33:51 reyk Exp $	*/
 
 /******************************************************************************
 
@@ -123,8 +123,8 @@
 #else
 #define IXGBE_TSO_SIZE			IXGBE_MAX_FRAME_SIZE
 #endif
-#define IXGBE_TX_BUFFER_SIZE		((u32) 1514)
-#define IXGBE_RX_HDR_SIZE		((u32) 256)
+#define IXGBE_TX_BUFFER_SIZE		((uint32_t) 1514)
+#define IXGBE_RX_HDR_SIZE		((uint32_t) 256)
 #define CSUM_OFFLOAD			7	/* Bits in csum flags */
 
 /* The number of MSIX messages the 82598 supports */
@@ -158,9 +158,9 @@ struct ixgbe_tx_buf {
 
 struct ixgbe_rx_buf {
 	struct mbuf	*m_head;
-	boolean_t	bigbuf;
+	int		 bigbuf;
 	/* one small and one large map */
-	bus_dmamap_t	map[2];
+	bus_dmamap_t	 map[2];
 };
 
 /*
@@ -181,25 +181,25 @@ struct ixgbe_dma_alloc {
 struct tx_ring {
         struct ix_softc		*sc;
 	struct mutex		tx_mtx;
-	u32			me;
-	u32			msix;
-	u32			eims;
-	u32			watchdog_timer;
+	uint32_t		me;
+	uint32_t		msix;
+	uint32_t		eims;
+	uint32_t		watchdog_timer;
 	union ixgbe_adv_tx_desc	*tx_base;
-	u_int32_t		*tx_hwb;
+	uint32_t		*tx_hwb;
 	struct ixgbe_dma_alloc	txdma;
 	struct ixgbe_dma_alloc	txwbdma;
-	u32			next_avail_tx_desc;
-	u32			next_tx_to_clean;
+	uint32_t		next_avail_tx_desc;
+	uint32_t		next_tx_to_clean;
 	struct ixgbe_tx_buf	*tx_buffers;
-	volatile u16		tx_avail;
-	u32			txd_cmd;
+	volatile uint16_t	tx_avail;
+	uint32_t		txd_cmd;
 	bus_dma_tag_t		txtag;
 	/* Soft Stats */
-	u32			no_tx_desc_avail;
-	u32			no_tx_desc_late;
-	u64			tx_irq;
-	u64			tx_packets;
+	uint32_t		no_tx_desc_avail;
+	uint32_t		no_tx_desc_late;
+	uint64_t		tx_irq;
+	uint64_t		tx_packets;
 };
 
 
@@ -209,10 +209,10 @@ struct tx_ring {
 struct rx_ring {
         struct ix_softc		*sc;
 	struct mutex		rx_mtx;
-	u32			me;
-	u32			msix;
-	u32			eims;
-	u32			payload;
+	uint32_t		me;
+	uint32_t		msix;
+	uint32_t		eims;
+	uint32_t		payload;
 	union ixgbe_adv_rx_desc	*rx_base;
 	struct ixgbe_dma_alloc	rxdma;
 #if 0
@@ -226,9 +226,9 @@ struct rx_ring {
 	struct mbuf		*fmp;
 	struct mbuf		*lmp;
 	/* Soft stats */
-	u64			rx_irq;
-	u64			packet_count;
-	u64 			byte_count;
+	uint64_t		rx_irq;
+	uint64_t		packet_count;
+	uint64_t 		byte_count;
 };
 
 /* Our adapter structure */
@@ -252,7 +252,7 @@ struct ix_softc {
 	void		*tag[IXGBE_MSGS];
 	struct resource *res[IXGBE_MSGS];
 	int		rid[IXGBE_MSGS];
-	u32		eims_mask;
+	uint32_t	eims_mask;
 
 	struct ifmedia	media;
 	struct timeout	timer;
@@ -265,17 +265,17 @@ struct ix_softc {
 	workq_fn	link_task;
 
 	/* Info about the board itself */
-	u32		part_num;
-	bool		link_active;
-	u16		max_frame_size;
-	u32		link_speed;
-	u32		tx_int_delay;
-	u32		tx_abs_int_delay;
-	u32		rx_int_delay;
-	u32		rx_abs_int_delay;
+	uint32_t	part_num;
+	int		link_active;
+	uint16_t	max_frame_size;
+	uint32_t	link_speed;
+	uint32_t	tx_int_delay;
+	uint32_t	tx_abs_int_delay;
+	uint32_t	rx_int_delay;
+	uint32_t	rx_abs_int_delay;
 
 	/* Indicates the cluster size to use */
-	bool		bigbufs;
+	int		bigbufs;
 
 	/*
 	 * Transmit rings:
@@ -292,8 +292,8 @@ struct ix_softc {
 	struct rx_ring	*rx_rings;
 	int		num_rx_desc;
 	int		num_rx_queues;
-	u32		rx_process_limit;
-	u_int		optics;
+	uint32_t	rx_process_limit;
+	uint		optics;
 
 	/* Misc stats maintained by the driver */
 	unsigned long   dropped_pkts;
diff --git a/sys/dev/pci/ixgbe.c b/sys/dev/pci/ixgbe.c
index e2c836bc14e..3dad1897262 100644
--- a/sys/dev/pci/ixgbe.c
+++ b/sys/dev/pci/ixgbe.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ixgbe.c,v 1.1 2008/06/08 20:01:02 reyk Exp $	*/
+/*	$OpenBSD: ixgbe.c,v 1.2 2008/06/08 20:33:51 reyk Exp $	*/
 
 /******************************************************************************
 
@@ -36,25 +36,25 @@
 
 #include <dev/pci/ixgbe.h>
 
-static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
-static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
-static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
+static int32_t ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
+static int32_t ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
+static int32_t ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
-static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
+static int32_t ixgbe_ready_eeprom(struct ixgbe_hw *hw);
 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
-static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
-                                        u16 count);
-static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
-static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
-static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
+static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, uint16_t data,
+                                        uint16_t count);
+static uint16_t ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, uint16_t count);
+static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec);
+static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec);
 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
-static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
+static uint16_t ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
 
-static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
-static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
-static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
-void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr);
-void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
+static void ixgbe_enable_rar(struct ixgbe_hw *hw, uint32_t index);
+static void ixgbe_disable_rar(struct ixgbe_hw *hw, uint32_t index);
+static int32_t ixgbe_mta_vector(struct ixgbe_hw *hw, uint8_t *mc_addr);
+void ixgbe_add_mc_addr(struct ixgbe_hw *hw, uint8_t *mc_addr);
+void ixgbe_add_uc_addr(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq);
 
 /**
  *  ixgbe_init_ops_generic - Inits function ptrs
@@ -62,11 +62,11 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
  *
  *  Initialize the function pointers.
  **/
-s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_init_ops_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 	struct ixgbe_mac_info *mac = &hw->mac;
-	u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+	uint32_t eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 
 	/* EEPROM */
 	eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
@@ -130,9 +130,9 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
  *  table, VLAN filter table, calls routine to set up link and flow control
  *  settings, and leaves transmit and receive units disabled and uninitialized
  **/
-s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_start_hw_generic(struct ixgbe_hw *hw)
 {
-	u32 ctrl_ext;
+	uint32_t ctrl_ext;
 
 	/* Set the media type */
 	hw->phy.media_type = hw->mac.ops.get_media_type(hw);
@@ -180,7 +180,7 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
  *  up link and flow control settings, and leaves transmit and receive units
  *  disabled and uninitialized
  **/
-s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_init_hw_generic(struct ixgbe_hw *hw)
 {
 	/* Reset the hardware */
 	hw->mac.ops.reset_hw(hw);
@@ -198,9 +198,9 @@ s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
  *  Clears all hardware statistics counters by reading them from the hardware
  *  Statistics counters are clear on read.
  **/
-s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
 {
-	u16 i = 0;
+	uint16_t i = 0;
 
 	IXGBE_READ_REG(hw, IXGBE_CRCERRS);
 	IXGBE_READ_REG(hw, IXGBE_ILLERRC);
@@ -276,10 +276,10 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
  *
  *  Reads the part number from the EEPROM.
  **/
-s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
+int32_t ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, uint32_t *pba_num)
 {
-	s32 ret_val;
-	u16 data;
+	int32_t ret_val;
+	uint16_t data;
 
 	DEBUGFUNC("ixgbe_read_pba_num_generic");
 
@@ -288,7 +288,7 @@ s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
 		DEBUGOUT("NVM Read Error\n");
 		return ret_val;
 	}
-	*pba_num = (u32)(data << 16);
+	*pba_num = (uint32_t)(data << 16);
 
 	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
 	if (ret_val) {
@@ -309,20 +309,20 @@ s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
  *  A reset of the adapter must be performed prior to calling this function
  *  in order for the MAC address to have been loaded from the EEPROM into RAR0
  **/
-s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
+int32_t ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, uint8_t *mac_addr)
 {
-	u32 rar_high;
-	u32 rar_low;
-	u16 i;
+	uint32_t rar_high;
+	uint32_t rar_low;
+	uint16_t i;
 
 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
 	rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
 
 	for (i = 0; i < 4; i++)
-		mac_addr[i] = (u8)(rar_low >> (i*8));
+		mac_addr[i] = (uint8_t)(rar_low >> (i*8));
 
 	for (i = 0; i < 2; i++)
-		mac_addr[i+4] = (u8)(rar_high >> (i*8));
+		mac_addr[i+4] = (uint8_t)(rar_high >> (i*8));
 
 	return IXGBE_SUCCESS;
 }
@@ -333,9 +333,9 @@ s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
  *
  *  Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
  **/
-s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
 {
-	u16 link_status;
+	uint16_t link_status;
 
 	hw->bus.type = ixgbe_bus_type_pci_express;
 
@@ -384,11 +384,11 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
  *  the shared code and drivers to determine if the adapter is in a stopped
  *  state and should not touch the hardware.
  **/
-s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
 {
-	u32 number_of_queues;
-	u32 reg_val;
-	u16 i;
+	uint32_t number_of_queues;
+	uint32_t reg_val;
+	uint16_t i;
 
 	/*
 	 * Set the adapter_stopped flag so other driver functions stop touching
@@ -435,9 +435,9 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
  *  @hw: pointer to hardware structure
  *  @index: led number to turn on
  **/
-s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
+int32_t ixgbe_led_on_generic(struct ixgbe_hw *hw, uint32_t index)
 {
-	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+	uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 
 	/* To turn on the LED, set mode to ON. */
 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
@@ -453,9 +453,9 @@ s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
  *  @hw: pointer to hardware structure
  *  @index: led number to turn off
  **/
-s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
+int32_t ixgbe_led_off_generic(struct ixgbe_hw *hw, uint32_t index)
 {
-	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+	uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 
 	/* To turn off the LED, set mode to OFF. */
 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
@@ -473,11 +473,11 @@ s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
  *  ixgbe_hw struct in order to set up EEPROM access.
  **/
-s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
-	u32 eec;
-	u16 eeprom_size;
+	uint32_t eec;
+	uint16_t eeprom_size;
 
 	if (eeprom->type == ixgbe_eeprom_uninitialized) {
 		eeprom->type = ixgbe_eeprom_none;
@@ -494,7 +494,7 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
 			 * SPI EEPROM is assumed here.  This code would need to
 			 * change if a future EEPROM is not SPI.
 			 */
-			eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
+			eeprom_size = (uint16_t)((eec & IXGBE_EEC_SIZE) >>
 					    IXGBE_EEC_SIZE_SHIFT);
 			eeprom->word_size = 1 << (eeprom_size +
 						  IXGBE_EEPROM_WORD_SIZE_SHIFT);
@@ -521,10 +521,10 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
  *  If ixgbe_eeprom_update_checksum is not called after this function, the
  *  EEPROM will most likely contain an invalid checksum.
  **/
-s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
+int32_t ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_t data)
 {
-	s32 status;
-	u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
+	int32_t status;
+	uint8_t write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
 
 	hw->eeprom.ops.init_params(hw);
 
@@ -562,7 +562,7 @@ s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
 		/* Send the Write command (8-bit opcode + addr) */
 		ixgbe_shift_out_eeprom_bits(hw, write_opcode,
 		                            IXGBE_EEPROM_OPCODE_BITS);
-		ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
+		ixgbe_shift_out_eeprom_bits(hw, (uint16_t)(offset*2),
 		                            hw->eeprom.address_bits);
 
 		/* Send the data */
@@ -588,12 +588,12 @@ out:
  *
  *  Reads 16 bit value from EEPROM through bit-bang method
  **/
-s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
-                                       u16 *data)
+int32_t ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, uint16_t offset,
+                                       uint16_t *data)
 {
-	s32 status;
-	u16 word_in;
-	u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
+	int32_t status;
+	uint16_t word_in;
+	uint8_t read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
 
 	hw->eeprom.ops.init_params(hw);
 
@@ -625,7 +625,7 @@ s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
 		/* Send the READ command (opcode + addr) */
 		ixgbe_shift_out_eeprom_bits(hw, read_opcode,
 		                            IXGBE_EEPROM_OPCODE_BITS);
-		ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
+		ixgbe_shift_out_eeprom_bits(hw, (uint16_t)(offset*2),
 		                            hw->eeprom.address_bits);
 
 		/* Read the data. */
@@ -648,10 +648,10 @@ out:
  *
  *  Reads a 16 bit word from the EEPROM using the EERD register.
  **/
-s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
+int32_t ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_t *data)
 {
-	u32 eerd;
-	s32 status;
+	uint32_t eerd;
+	int32_t status;
 
 	hw->eeprom.ops.init_params(hw);
 
@@ -682,11 +682,11 @@ out:
  *
  *  Polls the status bit (bit 1) of the EERD to determine when the read is done.
  **/
-static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
+static int32_t ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
 {
-	u32 i;
-	u32 reg;
-	s32 status = IXGBE_ERR_EEPROM;
+	uint32_t i;
+	uint32_t reg;
+	int32_t status = IXGBE_ERR_EEPROM;
 
 	for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
 		reg = IXGBE_READ_REG(hw, IXGBE_EERD);
@@ -706,11 +706,11 @@ static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
  *  Prepares EEPROM for access using bit-bang method. This function should
  *  be called before issuing a command to the EEPROM.
  **/
-static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
+static int32_t ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
 {
-	s32 status = IXGBE_SUCCESS;
-	u32 eec;
-	u32 i;
+	int32_t status = IXGBE_SUCCESS;
+	uint32_t eec;
+	uint32_t i;
 
 	if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS)
 		status = IXGBE_ERR_SWFW_SYNC;
@@ -757,12 +757,12 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
  *
  *  Sets the hardware semaphores so EEPROM access can occur for bit-bang method
  **/
-static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
+static int32_t ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
 {
-	s32 status = IXGBE_ERR_EEPROM;
-	u32 timeout;
-	u32 i;
-	u32 swsm;
+	int32_t status = IXGBE_ERR_EEPROM;
+	uint32_t timeout;
+	uint32_t i;
+	uint32_t swsm;
 
 	/* Set timeout value based on size of EEPROM */
 	timeout = hw->eeprom.word_size + 1;
@@ -824,7 +824,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
  **/
 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
 {
-	u32 swsm;
+	uint32_t swsm;
 
 	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 
@@ -838,11 +838,11 @@ static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
  *  ixgbe_ready_eeprom - Polls for EEPROM ready
  *  @hw: pointer to hardware structure
  **/
-static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
+static int32_t ixgbe_ready_eeprom(struct ixgbe_hw *hw)
 {
-	s32 status = IXGBE_SUCCESS;
-	u16 i;
-	u8 spi_stat_reg;
+	int32_t status = IXGBE_SUCCESS;
+	uint16_t i;
+	uint8_t spi_stat_reg;
 
 	/*
 	 * Read "Status Register" repeatedly until the LSB is cleared.  The
@@ -853,7 +853,7 @@ static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
 	for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
 		ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
 		                            IXGBE_EEPROM_OPCODE_BITS);
-		spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
+		spi_stat_reg = (uint8_t)ixgbe_shift_in_eeprom_bits(hw, 8);
 		if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
 			break;
 
@@ -879,7 +879,7 @@ static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
  **/
 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
 {
-	u32 eec;
+	uint32_t eec;
 
 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 
@@ -900,12 +900,12 @@ static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
  *  @data: data to send to the EEPROM
  *  @count: number of bits to shift out
  **/
-static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
-                                        u16 count)
+static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, uint16_t data,
+                                        uint16_t count)
 {
-	u32 eec;
-	u32 mask;
-	u32 i;
+	uint32_t eec;
+	uint32_t mask;
+	uint32_t i;
 
 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 
@@ -953,11 +953,11 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
  *  ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
  *  @hw: pointer to hardware structure
  **/
-static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
+static uint16_t ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, uint16_t count)
 {
-	u32 eec;
-	u32 i;
-	u16 data = 0;
+	uint32_t eec;
+	uint32_t i;
+	uint16_t data = 0;
 
 	/*
 	 * In order to read a register from the EEPROM, we need to shift
@@ -991,7 +991,7 @@ static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
  *  @hw: pointer to hardware structure
  *  @eec: EEC register's current value
  **/
-static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
+static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec)
 {
 	/*
 	 * Raise the clock input to the EEPROM
@@ -1008,7 +1008,7 @@ static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
  *  @hw: pointer to hardware structure
  *  @eecd: EECD's current value
  **/
-static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
+static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec)
 {
 	/*
 	 * Lower the clock input to the EEPROM (clearing the SK bit), then
@@ -1026,7 +1026,7 @@ static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
  **/
 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
 {
-	u32 eec;
+	uint32_t eec;
 
 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 
@@ -1049,14 +1049,14 @@ static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
  *  ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
  *  @hw: pointer to hardware structure
  **/
-static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
+static uint16_t ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
 {
-	u16 i;
-	u16 j;
-	u16 checksum = 0;
-	u16 length = 0;
-	u16 pointer = 0;
-	u16 word = 0;
+	uint16_t i;
+	uint16_t j;
+	uint16_t checksum = 0;
+	uint16_t length = 0;
+	uint16_t pointer = 0;
+	uint16_t word = 0;
 
 	/* Include 0x0-0x3F in the checksum */
 	for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
@@ -1084,7 +1084,7 @@ static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
 		}
 	}
 
-	checksum = (u16)IXGBE_EEPROM_SUM - checksum;
+	checksum = (uint16_t)IXGBE_EEPROM_SUM - checksum;
 
 	return checksum;
 }
@@ -1097,12 +1097,12 @@ static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
  *  Performs checksum calculation and validates the EEPROM checksum.  If the
  *  caller does not need checksum_val, the value can be NULL.
  **/
-s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
-                                           u16 *checksum_val)
+int32_t ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
+                                           uint16_t *checksum_val)
 {
-	s32 status;
-	u16 checksum;
-	u16 read_checksum = 0;
+	int32_t status;
+	uint16_t checksum;
+	uint16_t read_checksum = 0;
 
 	/*
 	 * Read the first word from the EEPROM. If this times out or fails, do
@@ -1137,10 +1137,10 @@ s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
  *  ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
  *  @hw: pointer to hardware structure
  **/
-s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
 {
-	s32 status;
-	u16 checksum;
+	int32_t status;
+	uint16_t checksum;
 
 	/*
 	 * Read the first word from the EEPROM. If this times out or fails, do
@@ -1166,9 +1166,9 @@ s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
  *
  *  Tests a MAC address to ensure it is a valid Individual Address
  **/
-s32 ixgbe_validate_mac_addr(u8 *mac_addr)
+int32_t ixgbe_validate_mac_addr(uint8_t *mac_addr)
 {
-	s32 status = IXGBE_SUCCESS;
+	int32_t status = IXGBE_SUCCESS;
 
 	/* Make sure it is not a multicast address */
 	if (IXGBE_IS_MULTICAST(mac_addr)) {
@@ -1197,11 +1197,11 @@ s32 ixgbe_validate_mac_addr(u8 *mac_addr)
  *
  *  Puts an ethernet address into a receive address register.
  **/
-s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
-                          u32 enable_addr)
+int32_t ixgbe_set_rar_generic(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr, uint32_t vmdq,
+                          uint32_t enable_addr)
 {
-	u32 rar_low, rar_high;
-	u32 rar_entries = hw->mac.num_rar_entries;
+	uint32_t rar_low, rar_high;
+	uint32_t rar_entries = hw->mac.num_rar_entries;
 
 	/* setup VMDq pool selection before this RAR gets enabled */
 	hw->mac.ops.set_vmdq(hw, index, vmdq);
@@ -1212,10 +1212,10 @@ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
 		 * HW expects these in little endian so we reverse the byte
 		 * order from network order (big endian) to little endian
 		 */
-		rar_low = ((u32)addr[0] |
-		           ((u32)addr[1] << 8) |
-		           ((u32)addr[2] << 16) |
-		           ((u32)addr[3] << 24));
+		rar_low = ((uint32_t)addr[0] |
+		           ((uint32_t)addr[1] << 8) |
+		           ((uint32_t)addr[2] << 16) |
+		           ((uint32_t)addr[3] << 24));
 		/*
 		 * Some parts put the VMDq setting in the extra RAH bits,
 		 * so save everything except the lower 16 bits that hold part
@@ -1223,7 +1223,7 @@ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
 		 */
 		rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
 		rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
-		rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
+		rar_high |= ((uint32_t)addr[4] | ((uint32_t)addr[5] << 8));
 
 		if (enable_addr != 0)
 			rar_high |= IXGBE_RAH_AV;
@@ -1244,9 +1244,9 @@ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
  *
  *  Enables the select receive address register.
  **/
-static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
+static void ixgbe_enable_rar(struct ixgbe_hw *hw, uint32_t index)
 {
-	u32 rar_high;
+	uint32_t rar_high;
 
 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
 	rar_high |= IXGBE_RAH_AV;
@@ -1260,9 +1260,9 @@ static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
  *
  *  Disables the select receive address register.
  **/
-static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
+static void ixgbe_disable_rar(struct ixgbe_hw *hw, uint32_t index)
 {
-	u32 rar_high;
+	uint32_t rar_high;
 
 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
 	rar_high &= (~IXGBE_RAH_AV);
@@ -1277,10 +1277,10 @@ static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
  *  of the receive address registers. Clears the multicast table. Assumes
  *  the receiver is in reset when the routine is called.
  **/
-s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
 {
-	u32 i;
-	u32 rar_entries = hw->mac.num_rar_entries;
+	uint32_t i;
+	uint32_t rar_entries = hw->mac.num_rar_entries;
 
 	/*
 	 * If the current mac address is valid, assume it is a software override
@@ -1338,10 +1338,10 @@ s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
  *
  *  Adds it to unused receive address register or goes into promiscuous mode.
  **/
-void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
+void ixgbe_add_uc_addr(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq)
 {
-	u32 rar_entries = hw->mac.num_rar_entries;
-	u32 rar;
+	uint32_t rar_entries = hw->mac.num_rar_entries;
+	uint32_t rar;
 
 	DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
 	          addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
@@ -1377,15 +1377,15 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
  *  Drivers using secondary unicast addresses must set user_set_promisc when
  *  manually putting the device into promiscuous mode.
  **/
-s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
-                                      u32 addr_count, ixgbe_mc_addr_itr next)
+int32_t ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *addr_list,
+                                      uint32_t addr_count, ixgbe_mc_addr_itr next)
 {
-	u8 *addr;
-	u32 i;
-	u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
-	u32 uc_addr_in_use;
-	u32 fctrl;
-	u32 vmdq;
+	uint8_t *addr;
+	uint32_t i;
+	uint32_t old_promisc_setting = hw->addr_ctrl.overflow_promisc;
+	uint32_t uc_addr_in_use;
+	uint32_t fctrl;
+	uint32_t vmdq;
 
 	/*
 	 * Clear accounting of old secondary address list,
@@ -1444,22 +1444,22 @@ s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
  *  by the MO field of the MCSTCTRL. The MO field is set during initialization
  *  to mc_filter_type.
  **/
-static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
+static int32_t ixgbe_mta_vector(struct ixgbe_hw *hw, uint8_t *mc_addr)
 {
-	u32 vector = 0;
+	uint32_t vector = 0;
 
 	switch (hw->mac.mc_filter_type) {
 	case 0:   /* use bits [47:36] of the address */
-		vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
+		vector = ((mc_addr[4] >> 4) | (((uint16_t)mc_addr[5]) << 4));
 		break;
 	case 1:   /* use bits [46:35] of the address */
-		vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
+		vector = ((mc_addr[4] >> 3) | (((uint16_t)mc_addr[5]) << 5));
 		break;
 	case 2:   /* use bits [45:34] of the address */
-		vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
+		vector = ((mc_addr[4] >> 2) | (((uint16_t)mc_addr[5]) << 6));
 		break;
 	case 3:   /* use bits [43:32] of the address */
-		vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
+		vector = ((mc_addr[4]) | (((uint16_t)mc_addr[5]) << 8));
 		break;
 	default:  /* Invalid mc_filter_type */
 		DEBUGOUT("MC filter type param set incorrectly\n");
@@ -1479,12 +1479,12 @@ static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
  *
  *  Sets the bit-vector in the multicast table.
  **/
-void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
+void ixgbe_set_mta(struct ixgbe_hw *hw, uint8_t *mc_addr)
 {
-	u32 vector;
-	u32 vector_bit;
-	u32 vector_reg;
-	u32 mta_reg;
+	uint32_t vector;
+	uint32_t vector_bit;
+	uint32_t vector_reg;
+	uint32_t mta_reg;
 
 	hw->addr_ctrl.mta_in_use++;
 
@@ -1514,10 +1514,10 @@ void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
  *
  *  Adds it to unused receive address register or to the multicast table.
  **/
-void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr)
+void ixgbe_add_mc_addr(struct ixgbe_hw *hw, uint8_t *mc_addr)
 {
-	u32 rar_entries = hw->mac.num_rar_entries;
-	u32 rar;
+	uint32_t rar_entries = hw->mac.num_rar_entries;
+	uint32_t rar;
 
 	DEBUGOUT6(" MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n",
 	          mc_addr[0], mc_addr[1], mc_addr[2],
@@ -1553,12 +1553,12 @@ void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr)
  *  registers for the first multicast addresses, and hashes the rest into the
  *  multicast table.
  **/
-s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
-                                      u32 mc_addr_count, ixgbe_mc_addr_itr next)
+int32_t ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *mc_addr_list,
+                                      uint32_t mc_addr_count, ixgbe_mc_addr_itr next)
 {
-	u32 i;
-	u32 rar_entries = hw->mac.num_rar_entries;
-	u32 vmdq;
+	uint32_t i;
+	uint32_t rar_entries = hw->mac.num_rar_entries;
+	uint32_t vmdq;
 
 	/*
 	 * Set the new number of MC addresses that we are being requested to
@@ -1603,10 +1603,10 @@ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
  *
  *  Enables multicast address in RAR and the use of the multicast hash table.
  **/
-s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
 {
-	u32 i;
-	u32 rar_entries = hw->mac.num_rar_entries;
+	uint32_t i;
+	uint32_t rar_entries = hw->mac.num_rar_entries;
 	struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
 
 	if (a->mc_addr_in_rar_count > 0)
@@ -1627,10 +1627,10 @@ s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
  *
  *  Disables multicast address in RAR and the use of the multicast hash table.
  **/
-s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
 {
-	u32 i;
-	u32 rar_entries = hw->mac.num_rar_entries;
+	uint32_t i;
+	uint32_t rar_entries = hw->mac.num_rar_entries;
 	struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
 
 	if (a->mc_addr_in_rar_count > 0)
@@ -1650,10 +1650,10 @@ s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
  *
  *  Clears the VLAN filer table, and the VMDq index associated with the filter
  **/
-s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
 {
-	u32 offset;
-	u32 vlanbyte;
+	uint32_t offset;
+	uint32_t vlanbyte;
 
 	for (offset = 0; offset < hw->mac.vft_size; offset++)
 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
@@ -1671,17 +1671,17 @@ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
  *  @hw: pointer to hardware structure
  *  @vlan: VLAN id to write to VLAN filter
  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
- *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
+ *  @vlan_on: intean flag to turn on/off VLAN in VFTA
  *
  *  Turn on/off specified VLAN in the VLAN filter table.
  **/
-s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
-                           bool vlan_on)
+int32_t ixgbe_set_vfta_generic(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind,
+                           int vlan_on)
 {
-	u32 VftaIndex;
-	u32 BitOffset;
-	u32 VftaReg;
-	u32 VftaByte;
+	uint32_t VftaIndex;
+	uint32_t BitOffset;
+	uint32_t VftaReg;
+	uint32_t VftaByte;
 
 	/* Determine 32-bit word position in array */
 	VftaIndex = (vlan >> 5) & 0x7F;   /* upper seven bits */
@@ -1720,11 +1720,11 @@ s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
  *  bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
  *  is returned signifying master requests disabled.
  **/
-s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
+int32_t ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
 {
-	u32 ctrl;
-	s32 i;
-	s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
+	uint32_t ctrl;
+	int32_t i;
+	int32_t status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 
 	ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 	ctrl |= IXGBE_CTRL_GIO_DIS;
@@ -1750,12 +1750,12 @@ s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
  *  Acquires the SWFW semaphore thought the GSSR register for the specified
  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
  **/
-s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
+int32_t ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, uint16_t mask)
 {
-	u32 gssr;
-	u32 swmask = mask;
-	u32 fwmask = mask << 5;
-	s32 timeout = 200;
+	uint32_t gssr;
+	uint32_t swmask = mask;
+	uint32_t fwmask = mask << 5;
+	int32_t timeout = 200;
 
 	while (timeout) {
 		if (ixgbe_get_eeprom_semaphore(hw))
@@ -1794,10 +1794,10 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
  *  Releases the SWFW semaphore thought the GSSR register for the specified
  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
  **/
-void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
+void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, uint16_t mask)
 {
-	u32 gssr;
-	u32 swmask = mask;
+	uint32_t gssr;
+	uint32_t swmask = mask;
 
 	ixgbe_get_eeprom_semaphore(hw);
 
@@ -1816,15 +1816,15 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
  *
  *  Performs read operation to Atlas analog register specified.
  **/
-s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val)
+int32_t ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val)
 {
-	u32  atlas_ctl;
+	uint32_t  atlas_ctl;
 
 	IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
 	IXGBE_WRITE_FLUSH(hw);
 	usec_delay(10);
 	atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
-	*val = (u8)atlas_ctl;
+	*val = (uint8_t)atlas_ctl;
 
 	return IXGBE_SUCCESS;
 }
@@ -1837,9 +1837,9 @@ s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val)
  *
  *  Performs write operation to Atlas analog register specified.
  **/
-s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val)
+int32_t ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, uint32_t reg, uint8_t val)
 {
-	u32  atlas_ctl;
+	uint32_t  atlas_ctl;
 
 	atlas_ctl = (reg << 8) | val;
 	IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
diff --git a/sys/dev/pci/ixgbe.h b/sys/dev/pci/ixgbe.h
index 10b8e818795..c20dc534813 100644
--- a/sys/dev/pci/ixgbe.h
+++ b/sys/dev/pci/ixgbe.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ixgbe.h,v 1.1 2008/06/08 20:01:02 reyk Exp $	*/
+/*	$OpenBSD: ixgbe.h,v 1.2 2008/06/08 20:33:51 reyk Exp $	*/
 
 /******************************************************************************
 
@@ -82,13 +82,6 @@
 
 #include <dev/rndvar.h>
 
-typedef uint8_t  u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-typedef int32_t	 s32;
-typedef uint64_t u64;
-typedef boolean_t bool;
-
 #include <dev/pci/ixgbe_type.h>
 
 #define ASSERT(x) if(!(x)) panic("IXGBE: x")
@@ -127,7 +120,7 @@ typedef struct device device_t;
 
 /* This is needed by the shared code */
 struct ixgbe_hw; 
-extern u16 ixgbe_read_pci_cfg(struct ixgbe_hw *, u32);
+extern uint16_t ixgbe_read_pci_cfg(struct ixgbe_hw *, uint32_t);
 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg
 
 struct ixgbe_osdep {
@@ -162,75 +155,75 @@ struct ixgbe_osdep {
 #define PCIR_BAR(_x)	(0x10 + (_x) * 4)
 #define roundup2(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
 
-s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
-s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
-s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
-s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
-s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
-s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
-s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
-s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
-
-s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
-s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
-
-s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
-s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
-s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
-s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
-                                       u16 *data);
-s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
-                                           u16 *checksum_val);
-s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
-
-s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
-                          u32 enable_addr);
-s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
-s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
-                                      u32 mc_addr_count,
+int32_t ixgbe_init_ops_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_init_hw_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_start_hw_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, uint32_t *pba_num);
+int32_t ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, uint8_t *mac_addr);
+int32_t ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
+
+int32_t ixgbe_led_on_generic(struct ixgbe_hw *hw, uint32_t index);
+int32_t ixgbe_led_off_generic(struct ixgbe_hw *hw, uint32_t index);
+
+int32_t ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_t data);
+int32_t ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_t *data);
+int32_t ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, uint16_t offset,
+                                       uint16_t *data);
+int32_t ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
+                                           uint16_t *checksum_val);
+int32_t ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
+
+int32_t ixgbe_set_rar_generic(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr, uint32_t vmdq,
+                          uint32_t enable_addr);
+int32_t ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *mc_addr_list,
+                                      uint32_t mc_addr_count,
                                       ixgbe_mc_addr_itr func);
-s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
-                                      u32 addr_count, ixgbe_mc_addr_itr func);
-s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
-s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
-s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
-s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
-                           u32 vind, bool vlan_on);
+int32_t ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *addr_list,
+                                      uint32_t addr_count, ixgbe_mc_addr_itr func);
+int32_t ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_set_vfta_generic(struct ixgbe_hw *hw, uint32_t vlan,
+                           uint32_t vind, int vlan_on);
 
-s32 ixgbe_validate_mac_addr(u8 *mac_addr);
-s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
-void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
-s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
+int32_t ixgbe_validate_mac_addr(uint8_t *mac_addr);
+int32_t ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, uint16_t mask);
+void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, uint16_t mask);
+int32_t ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
 
-s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val);
-s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val);
+int32_t ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val);
+int32_t ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, uint32_t reg, uint8_t val);
 
-void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
-s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
+void ixgbe_set_mta(struct ixgbe_hw *hw, uint8_t *mc_addr);
+int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw);
 
 /* PHY */
-s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
-bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
-enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
-s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
-s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
-s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
-s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
-                               u32 device_type, u16 *phy_data);
-s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
-                                u32 device_type, u16 phy_data);
-s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
-s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
+int32_t ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
+int ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr);
+enum ixgbe_phy_type ixgbe_get_phy_type_from_id(uint32_t phy_id);
+int32_t ixgbe_get_phy_id(struct ixgbe_hw *hw);
+int32_t ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr,
+                               uint32_t device_type, uint16_t *phy_data);
+int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr,
+                                uint32_t device_type, uint16_t phy_data);
+int32_t ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
                                        ixgbe_link_speed speed,
-                                       bool autoneg,
-                                       bool autoneg_wait_to_complete);
+                                       int autoneg,
+                                       int autoneg_wait_to_complete);
 
-s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
+int32_t ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
                              ixgbe_link_speed *speed,
-                             bool *link_up);
-s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
-                                       u16 *firmware_version);
+                             int *link_up);
+int32_t ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
+                                       uint16_t *firmware_version);
 
-s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
+int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 
 #endif /* _IXGBE_OS_H_ */
diff --git a/sys/dev/pci/ixgbe_82598.c b/sys/dev/pci/ixgbe_82598.c
index 58e38a27cc1..9f1cad43a6e 100644
--- a/sys/dev/pci/ixgbe_82598.c
+++ b/sys/dev/pci/ixgbe_82598.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ixgbe_82598.c,v 1.1 2008/06/08 20:01:02 reyk Exp $	*/
+/*	$OpenBSD: ixgbe_82598.c,v 1.2 2008/06/08 20:33:51 reyk Exp $	*/
 
 /******************************************************************************
 
@@ -37,37 +37,37 @@
 #include <dev/pci/ixgbe.h>
 #include <dev/pci/ixgbe_type.h>
 
-s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
-s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
+int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw);
+int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
                                       ixgbe_link_speed *speed,
-                                      bool *autoneg);
-s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
+                                      int *autoneg);
+int32_t ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
                                              ixgbe_link_speed *speed,
-                                             bool *autoneg);
+                                             int *autoneg);
 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
-s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
-s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
-s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
+int32_t ixgbe_setup_fc_82598(struct ixgbe_hw *hw, int32_t packetbuf_num);
+int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
+int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
                                ixgbe_link_speed *speed,
-                               bool *link_up, bool link_up_wait_to_complete);
-s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
+                               int *link_up, int link_up_wait_to_complete);
+int32_t ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
                                      ixgbe_link_speed speed,
-                                     bool autoneg,
-                                     bool autoneg_wait_to_complete);
-s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
-s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
+                                     int autoneg,
+                                     int autoneg_wait_to_complete);
+int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
+int32_t ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
                                         ixgbe_link_speed speed,
-                                        bool autoneg,
-                                        bool autoneg_wait_to_complete);
+                                        int autoneg,
+                                        int autoneg_wait_to_complete);
 #ifndef NO_82598_A0_SUPPORT
-s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw);
+int32_t ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw);
 #endif
-s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
-s32 ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw);
-s32 ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw);
-s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
-s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index);
-s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index);
+int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
+int32_t ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw);
+int32_t ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw);
+int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);
+int32_t ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, uint32_t index);
+int32_t ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, uint32_t index);
 
 /**
  *  ixgbe_init_ops_82598 - Inits func ptrs and MAC type
@@ -76,11 +76,11 @@ s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index);
  *  Initialize the function pointers and assign the MAC type for 82598.
  *  Does not touch the hardware.
  **/
-s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
+int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	struct ixgbe_phy_info *phy = &hw->phy;
-	s32 ret_val;
+	int32_t ret_val;
 
 	ret_val = ixgbe_init_phy_ops_generic(hw);
 	ret_val = ixgbe_init_ops_generic(hw);
@@ -151,16 +151,16 @@ s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
  *  @hw: pointer to hardware structure
  *  @speed: pointer to link speed
- *  @autoneg: boolean auto-negotiation value
+ *  @autoneg: intean auto-negotiation value
  *
  *  Determines the link capabilities by reading the AUTOC register.
  **/
-s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
+int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
                                       ixgbe_link_speed *speed,
-                                      bool *autoneg)
+                                      int *autoneg)
 {
-	s32 status = IXGBE_SUCCESS;
-	s32 autoc_reg;
+	int32_t status = IXGBE_SUCCESS;
+	int32_t autoc_reg;
 
 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 
@@ -209,16 +209,16 @@ s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
  *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
  *  @hw: pointer to hardware structure
  *  @speed: pointer to link speed
- *  @autoneg: boolean auto-negotiation value
+ *  @autoneg: intean auto-negotiation value
  *
  *  Determines the link capabilities by reading the AUTOC register.
  **/
-s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
+int32_t ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
                                              ixgbe_link_speed *speed,
-                                             bool *autoneg)
+                                             int *autoneg)
 {
-	s32 status = IXGBE_ERR_LINK_SETUP;
-	u16 speed_ability;
+	int32_t status = IXGBE_ERR_LINK_SETUP;
+	uint16_t speed_ability;
 
 	*speed = 0;
 	*autoneg = TRUE;
@@ -280,10 +280,10 @@ enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
  *  Configures the flow control settings based on SW configuration.  This
  *  function is used for 802.3x flow control configuration only.
  **/
-s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
+int32_t ixgbe_setup_fc_82598(struct ixgbe_hw *hw, int32_t packetbuf_num)
 {
-	u32 frctl_reg;
-	u32 rmcs_reg;
+	uint32_t frctl_reg;
+	uint32_t rmcs_reg;
 
 	if (packetbuf_num < 0 || packetbuf_num > 7) {
 		DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
@@ -397,14 +397,14 @@ s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
  *  Configures link settings based on values in the ixgbe_hw struct.
  *  Restarts the link.  Performs autonegotiation if needed.
  **/
-s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
+int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
 {
 	ixgbe_link_speed speed;
-	bool link_up;
-	u32 autoc_reg;
-	u32 links_reg;
-	u32 i;
-	s32 status = IXGBE_SUCCESS;
+	int link_up;
+	uint32_t autoc_reg;
+	uint32_t links_reg;
+	uint32_t i;
+	int32_t status = IXGBE_SUCCESS;
 
 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 
@@ -468,16 +468,16 @@ s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
  *  @hw: pointer to hardware structure
  *  @speed: pointer to link speed
  *  @link_up: TRUE is link is up, FALSE otherwise
- *  @link_up_wait_to_complete: bool used to wait for link up or not
+ *  @link_up_wait_to_complete: int used to wait for link up or not
  *
  *  Reads the links register to determine if link is up and the current speed
  **/
-s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
-                               bool *link_up, bool link_up_wait_to_complete)
+int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                               int *link_up, int link_up_wait_to_complete)
 {
-	u32 links_reg;
-	u32 i;
-	u16 link_reg, adapt_comp_reg;
+	uint32_t links_reg;
+	uint32_t i;
+	uint16_t link_reg, adapt_comp_reg;
 
 	if (hw->phy.type == ixgbe_phy_nl) {
 		hw->phy.ops.read_reg(hw, 1, IXGBE_TWINAX_DEV, &link_reg);
@@ -547,10 +547,10 @@ out:
  *  Reads PCS registers and sets flow control settings, based on
  *  link-partner's abilities.
  **/
-s32 ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw)
+int32_t ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw)
 {
-	s32 ret_val = IXGBE_SUCCESS;
-	u32 pcs_anadv_reg, pcs_lpab_reg, pcs_lstat_reg, i;
+	int32_t ret_val = IXGBE_SUCCESS;
+	uint32_t pcs_anadv_reg, pcs_lpab_reg, pcs_lstat_reg, i;
 	DEBUGFUNC("ixgbe_configure_fiber_serdes_fc_82598");
 
 	/* Check that autonegotiation has completed */
@@ -639,10 +639,10 @@ out:
  *  Sets up PCS registers and sets flow control settings, based on
  *  link-partner's abilities.
  **/
-s32 ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw)
+int32_t ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw)
 {
-	u32 reg;
-	s32 ret_val;
+	uint32_t reg;
+	int32_t ret_val;
 
 	DEBUGFUNC("ixgbe_setup_fiber_serdes_link_82598");
 
@@ -739,11 +739,11 @@ out:
  *
  *  Set the link speed in the AUTOC register and restarts link.
  **/
-s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
-                                     ixgbe_link_speed speed, bool autoneg,
-                                     bool autoneg_wait_to_complete)
+int32_t ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
+                                     ixgbe_link_speed speed, int autoneg,
+                                     int autoneg_wait_to_complete)
 {
-	s32 status = IXGBE_SUCCESS;
+	int32_t status = IXGBE_SUCCESS;
 
 	/* If speed is 10G, then check for CX4 or XAUI. */
 	if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
@@ -786,9 +786,9 @@ s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
  *  phy and wait for autonegotiate to finish.  Then synchronize the
  *  MAC and PHY.
  **/
-s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
+int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
 {
-	s32 status;
+	int32_t status;
 
 	/* Restart autonegotiation on PHY */
 	status = hw->phy.ops.setup_link(hw);
@@ -812,12 +812,12 @@ s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
  *
  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
  **/
-s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
+int32_t ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
                                         ixgbe_link_speed speed,
-                                        bool autoneg,
-                                        bool autoneg_wait_to_complete)
+                                        int autoneg,
+                                        int autoneg_wait_to_complete)
 {
-	s32 status;
+	int32_t status;
 
 	/* Setup the PHY according to input speed */
 	status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
@@ -842,14 +842,14 @@ s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
  *  reset.
  **/
-s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw)
+int32_t ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw)
 {
-	s32 status = IXGBE_SUCCESS;
-	u32 ctrl;
-	u32 gheccr;
-	u32 autoc;
-	u32 i;
-	u32 resets;
+	int32_t status = IXGBE_SUCCESS;
+	uint32_t ctrl;
+	uint32_t gheccr;
+	uint32_t autoc;
+	uint32_t i;
+	uint32_t resets;
 
 	/* Call adapter stop to disable tx/rx and clear interrupts */
 	hw->mac.ops.stop_adapter(hw);
@@ -934,14 +934,14 @@ s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw)
  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
  *  reset.
  **/
-s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
+int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 {
-	s32 status = IXGBE_SUCCESS;
-	u32 ctrl;
-	u32 gheccr;
-	u32 i;
-	u32 autoc;
-	u8  analog_val;
+	int32_t status = IXGBE_SUCCESS;
+	uint32_t ctrl;
+	uint32_t gheccr;
+	uint32_t i;
+	uint32_t autoc;
+	uint8_t  analog_val;
 
 	/* Call adapter stop to disable tx/rx and clear interrupts */
 	hw->mac.ops.stop_adapter(hw);
@@ -1051,9 +1051,9 @@ s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
  *  @rar: receive address register index to associate with a VMDq index
  *  @vmdq: VMDq set index
  **/
-s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)
 {
-	u32 rar_high;
+	uint32_t rar_high;
 
 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 	rar_high &= ~IXGBE_RAH_VIND_MASK;
@@ -1067,12 +1067,12 @@ s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
  *  @hw: pointer to hardware structure
  *  @index: led number to blink
  **/
-s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
+int32_t ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, uint32_t index)
 {
 	ixgbe_link_speed speed = 0;
-	bool link_up = 0;
-	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
-	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+	int link_up = 0;
+	uint32_t autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+	uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 
 	/*
 	 * Link must be up to auto-blink the LEDs on the 82598EB MAC;
@@ -1099,10 +1099,10 @@ s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
  *  @hw: pointer to hardware structure
  *  @index: led number to stop blinking
  **/
-s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
+int32_t ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, uint32_t index)
 {
-	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
-	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+	uint32_t autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+	uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 
 	autoc_reg &= ~IXGBE_AUTOC_FLU;
 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
diff --git a/sys/dev/pci/ixgbe_phy.c b/sys/dev/pci/ixgbe_phy.c
index 83d59b719c5..2dc09a4a4e8 100644
--- a/sys/dev/pci/ixgbe_phy.c
+++ b/sys/dev/pci/ixgbe_phy.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ixgbe_phy.c,v 1.1 2008/06/08 20:01:02 reyk Exp $	*/
+/*	$OpenBSD: ixgbe_phy.c,v 1.2 2008/06/08 20:33:51 reyk Exp $	*/
 
 /******************************************************************************
 
@@ -42,7 +42,7 @@
  *
  *  Initialize the function pointers.
  **/
-s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_phy_info *phy = &hw->phy;
 
@@ -65,10 +65,10 @@ s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  *
  *  Determines the physical layer module found on the current adapter.
  **/
-s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 {
-	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
-	u32 phy_addr;
+	int32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
+	uint32_t phy_addr;
 
 	if (hw->phy.type == ixgbe_phy_unknown) {
 		for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
@@ -93,10 +93,10 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  *  @hw: pointer to hardware structure
  *
  **/
-bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
+int ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr)
 {
-	u16 phy_id = 0;
-	bool valid = FALSE;
+	uint16_t phy_id = 0;
+	int valid = FALSE;
 
 	hw->phy.addr = phy_addr;
 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
@@ -113,23 +113,23 @@ bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
  *  @hw: pointer to hardware structure
  *
  **/
-s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
+int32_t ixgbe_get_phy_id(struct ixgbe_hw *hw)
 {
-	u32 status;
-	u16 phy_id_high = 0;
-	u16 phy_id_low = 0;
+	uint32_t status;
+	uint16_t phy_id_high = 0;
+	uint16_t phy_id_low = 0;
 
 	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 	                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 	                              &phy_id_high);
 
 	if (status == IXGBE_SUCCESS) {
-		hw->phy.id = (u32)(phy_id_high << 16);
+		hw->phy.id = (uint32_t)(phy_id_high << 16);
 		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 		                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 		                              &phy_id_low);
-		hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
-		hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
+		hw->phy.id |= (uint32_t)(phy_id_low & IXGBE_PHY_REVISION_MASK);
+		hw->phy.revision = (uint32_t)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 	}
 
 	return status;
@@ -140,7 +140,7 @@ s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
  *  @hw: pointer to hardware structure
  *
  **/
-enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
+enum ixgbe_phy_type ixgbe_get_phy_type_from_id(uint32_t phy_id)
 {
 	enum ixgbe_phy_type phy_type;
 
@@ -167,7 +167,7 @@ enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
  *  ixgbe_reset_phy_generic - Performs a PHY reset
  *  @hw: pointer to hardware structure
  **/
-s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 {
 	/*
 	 * Perform soft PHY reset to the PHY_XS.
@@ -184,14 +184,14 @@ s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
  *  @reg_addr: 32 bit address of PHY register to read
  *  @phy_data: Pointer to read data from PHY register
  **/
-s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
-                               u32 device_type, u16 *phy_data)
+int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr,
+                               uint32_t device_type, uint16_t *phy_data)
 {
-	u32 command;
-	u32 i;
-	u32 data;
-	s32 status = IXGBE_SUCCESS;
-	u16 gssr;
+	uint32_t command;
+	uint32_t i;
+	uint32_t data;
+	int32_t status = IXGBE_SUCCESS;
+	uint16_t gssr;
 
 	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 		gssr = IXGBE_GSSR_PHY1_SM;
@@ -266,7 +266,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 				 */
 				data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 				data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
-				*phy_data = (u16)(data);
+				*phy_data = (uint16_t)(data);
 			}
 		}
 
@@ -283,13 +283,13 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
  *  @device_type: 5 bit device type
  *  @phy_data: Data to write to the PHY register
  **/
-s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
-                                u32 device_type, u16 phy_data)
+int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr,
+                                uint32_t device_type, uint16_t phy_data)
 {
-	u32 command;
-	u32 i;
-	s32 status = IXGBE_SUCCESS;
-	u16 gssr;
+	uint32_t command;
+	uint32_t i;
+	int32_t status = IXGBE_SUCCESS;
+	uint16_t gssr;
 
 	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 		gssr = IXGBE_GSSR_PHY1_SM;
@@ -301,7 +301,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 
 	if (status == IXGBE_SUCCESS) {
 		/* Put the data in the MDI single read and write data register*/
-		IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
+		IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (uint32_t)phy_data);
 
 		/* Setup and write the address cycle command */
 		command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
@@ -374,12 +374,12 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
  *
  *  Restart autonegotiation and PHY and waits for completion.
  **/
-s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
+int32_t ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 {
-	s32 status = IXGBE_NOT_IMPLEMENTED;
-	u32 time_out;
-	u32 max_time_out = 10;
-	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
+	int32_t status = IXGBE_NOT_IMPLEMENTED;
+	uint32_t time_out;
+	uint32_t max_time_out = 10;
+	uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG;
 
 	/*
 	 * Set advertisement settings in PHY based on autoneg_advertised
@@ -434,10 +434,10 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
  *  @speed: new link speed
  *  @autoneg: TRUE if autonegotiation enabled
  **/
-s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
+int32_t ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
                                        ixgbe_link_speed speed,
-                                       bool autoneg,
-                                       bool autoneg_wait_to_complete)
+                                       int autoneg,
+                                       int autoneg_wait_to_complete)
 {
 	UNREFERENCED_PARAMETER(autoneg);
 	UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
@@ -468,15 +468,15 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
  *  Reads the VS1 register to determine if link is up and the current speed for
  *  the PHY.
  **/
-s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
-                             bool *link_up)
+int32_t ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                             int *link_up)
 {
-	s32 status = IXGBE_SUCCESS;
-	u32 time_out;
-	u32 max_time_out = 10;
-	u16 phy_link = 0;
-	u16 phy_speed = 0;
-	u16 phy_data = 0;
+	int32_t status = IXGBE_SUCCESS;
+	uint32_t time_out;
+	uint32_t max_time_out = 10;
+	uint16_t phy_link = 0;
+	uint16_t phy_speed = 0;
+	uint16_t phy_data = 0;
 
 	/* Initialize speed and link to default case */
 	*link_up = FALSE;
@@ -514,10 +514,10 @@ s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
  *  @hw: pointer to hardware structure
  *  @firmware_version: pointer to the PHY Firmware Version
  **/
-s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
-                                       u16 *firmware_version)
+int32_t ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
+                                       uint16_t *firmware_version)
 {
-	s32 status = IXGBE_SUCCESS;
+	int32_t status = IXGBE_SUCCESS;
 
 	status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 	                              IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
@@ -530,14 +530,14 @@ s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
  *  ixgbe_reset_phy_nl - Performs a PHY reset
  *  @hw: pointer to hardware structure
  **/
-s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
+int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 {
-	u16 phy_offset, control, eword, edata, list_crc, block_crc, id, sfp_id;
-	bool end_data = FALSE;
-	u16 list_offset, data_offset;
-	u16 phy_data = 0;
-	s32 ret_val = IXGBE_SUCCESS;
-	u32 i;
+	uint16_t phy_offset, control, eword, edata, list_crc, block_crc, id, sfp_id;
+	int end_data = FALSE;
+	uint16_t list_offset, data_offset;
+	uint16_t phy_data = 0;
+	int32_t ret_val = IXGBE_SUCCESS;
+	uint32_t i;
 
 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 	                     IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
diff --git a/sys/dev/pci/ixgbe_type.h b/sys/dev/pci/ixgbe_type.h
index be689aad597..c4975a7c910 100644
--- a/sys/dev/pci/ixgbe_type.h
+++ b/sys/dev/pci/ixgbe_type.h
@@ -913,12 +913,12 @@
 
 /* Check whether address is multicast.  This is little-endian specific check.*/
 #define IXGBE_IS_MULTICAST(Address) \
-                (bool)(((u8 *)(Address))[0] & ((u8)0x01))
+                (int)(((uint8_t *)(Address))[0] & ((uint8_t)0x01))
 
 /* Check whether an address is broadcast. */
 #define IXGBE_IS_BROADCAST(Address)                      \
-                ((((u8 *)(Address))[0] == ((u8)0xff)) && \
-                (((u8 *)(Address))[1] == ((u8)0xff)))
+                ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && \
+                (((uint8_t *)(Address))[1] == ((uint8_t)0xff)))
 
 /* RAH */
 #define IXGBE_RAH_VIND_MASK     0x003C0000
@@ -1101,17 +1101,17 @@
 
 #ifndef __le16
 /* Little Endian defines */
-#define __le8   u8
-#define __le16  u16
-#define __le32  u32
-#define __le64  u64
+#define __le8   uint8_t
+#define __le16  uint16_t
+#define __le32  uint32_t
+#define __le64  uint64_t
 
 #endif
 
 
 /* Transmit Descriptor - Legacy */
 struct ixgbe_legacy_tx_desc {
-	u64 buffer_addr;       /* Address of the descriptor's data buffer */
+	uint64_t buffer_addr;       /* Address of the descriptor's data buffer */
 	union {
 		__le32 data;
 		struct {
@@ -1233,9 +1233,9 @@ struct ixgbe_adv_tx_context_desc {
 #define IXGBE_ADVTXD_MSS_SHIFT       16  /* Adv ctxt MSS shift */
 
 /* Autonegotiation advertised speeds */
-typedef u32 ixgbe_autoneg_advertised;
+typedef uint32_t ixgbe_autoneg_advertised;
 /* Link speed */
-typedef u32 ixgbe_link_speed;
+typedef uint32_t ixgbe_link_speed;
 #define IXGBE_LINK_SPEED_UNKNOWN   0
 #define IXGBE_LINK_SPEED_100_FULL  0x0008
 #define IXGBE_LINK_SPEED_1GB_FULL  0x0020
@@ -1316,12 +1316,12 @@ enum ixgbe_bus_width {
 };
 
 struct ixgbe_addr_filter_info {
-	u32 num_mc_addrs;
-	u32 rar_used_count;
-	u32 mc_addr_in_rar_count;
-	u32 mta_in_use;
-	u32 overflow_promisc;
-	bool user_set_promisc;
+	uint32_t num_mc_addrs;
+	uint32_t rar_used_count;
+	uint32_t mc_addr_in_rar_count;
+	uint32_t mta_in_use;
+	uint32_t overflow_promisc;
+	int user_set_promisc;
 };
 
 /* Bus parameters */
@@ -1333,184 +1333,184 @@ struct ixgbe_bus_info {
 
 /* Flow control parameters */
 struct ixgbe_fc_info {
-	u32 high_water; /* Flow Control High-water */
-	u32 low_water; /* Flow Control Low-water */
-	u16 pause_time; /* Flow Control Pause timer */
-	bool send_xon; /* Flow control send XON */
-	bool strict_ieee; /* Strict IEEE mode */
+	uint32_t high_water; /* Flow Control High-water */
+	uint32_t low_water; /* Flow Control Low-water */
+	uint16_t pause_time; /* Flow Control Pause timer */
+	int send_xon; /* Flow control send XON */
+	int strict_ieee; /* Strict IEEE mode */
 	enum ixgbe_fc_type type; /* Type of flow control */
 	enum ixgbe_fc_type original_type;
 };
 
 /* Statistics counters collected by the MAC */
 struct ixgbe_hw_stats {
-	u64 crcerrs;
-	u64 illerrc;
-	u64 errbc;
-	u64 mspdc;
-	u64 mpctotal;
-	u64 mpc[8];
-	u64 mlfc;
-	u64 mrfc;
-	u64 rlec;
-	u64 lxontxc;
-	u64 lxonrxc;
-	u64 lxofftxc;
-	u64 lxoffrxc;
-	u64 pxontxc[8];
-	u64 pxonrxc[8];
-	u64 pxofftxc[8];
-	u64 pxoffrxc[8];
-	u64 prc64;
-	u64 prc127;
-	u64 prc255;
-	u64 prc511;
-	u64 prc1023;
-	u64 prc1522;
-	u64 gprc;
-	u64 bprc;
-	u64 mprc;
-	u64 gptc;
-	u64 gorc;
-	u64 gotc;
-	u64 rnbc[8];
-	u64 ruc;
-	u64 rfc;
-	u64 roc;
-	u64 rjc;
-	u64 mngprc;
-	u64 mngpdc;
-	u64 mngptc;
-	u64 tor;
-	u64 tpr;
-	u64 tpt;
-	u64 ptc64;
-	u64 ptc127;
-	u64 ptc255;
-	u64 ptc511;
-	u64 ptc1023;
-	u64 ptc1522;
-	u64 mptc;
-	u64 bptc;
-	u64 xec;
-	u64 rqsmr[16];
-	u64 tqsmr[8];
-	u64 qprc[16];
-	u64 qptc[16];
-	u64 qbrc[16];
-	u64 qbtc[16];
+	uint64_t crcerrs;
+	uint64_t illerrc;
+	uint64_t errbc;
+	uint64_t mspdc;
+	uint64_t mpctotal;
+	uint64_t mpc[8];
+	uint64_t mlfc;
+	uint64_t mrfc;
+	uint64_t rlec;
+	uint64_t lxontxc;
+	uint64_t lxonrxc;
+	uint64_t lxofftxc;
+	uint64_t lxoffrxc;
+	uint64_t pxontxc[8];
+	uint64_t pxonrxc[8];
+	uint64_t pxofftxc[8];
+	uint64_t pxoffrxc[8];
+	uint64_t prc64;
+	uint64_t prc127;
+	uint64_t prc255;
+	uint64_t prc511;
+	uint64_t prc1023;
+	uint64_t prc1522;
+	uint64_t gprc;
+	uint64_t bprc;
+	uint64_t mprc;
+	uint64_t gptc;
+	uint64_t gorc;
+	uint64_t gotc;
+	uint64_t rnbc[8];
+	uint64_t ruc;
+	uint64_t rfc;
+	uint64_t roc;
+	uint64_t rjc;
+	uint64_t mngprc;
+	uint64_t mngpdc;
+	uint64_t mngptc;
+	uint64_t tor;
+	uint64_t tpr;
+	uint64_t tpt;
+	uint64_t ptc64;
+	uint64_t ptc127;
+	uint64_t ptc255;
+	uint64_t ptc511;
+	uint64_t ptc1023;
+	uint64_t ptc1522;
+	uint64_t mptc;
+	uint64_t bptc;
+	uint64_t xec;
+	uint64_t rqsmr[16];
+	uint64_t tqsmr[8];
+	uint64_t qprc[16];
+	uint64_t qptc[16];
+	uint64_t qbrc[16];
+	uint64_t qbtc[16];
 };
 
 /* forward declaration */
 struct ixgbe_hw;
 
 /* iterator type for walking multicast address lists */
-typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
-                                  u32 *vmdq);
+typedef uint8_t* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, uint8_t **mc_addr_ptr,
+                                  uint32_t *vmdq);
 
 /* Function pointer table */
 struct ixgbe_eeprom_operations {
-	s32 (*init_params)(struct ixgbe_hw *);
-	s32 (*read)(struct ixgbe_hw *, u16, u16 *);
-	s32 (*write)(struct ixgbe_hw *, u16, u16);
-	s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
-	s32 (*update_checksum)(struct ixgbe_hw *);
+	int32_t (*init_params)(struct ixgbe_hw *);
+	int32_t (*read)(struct ixgbe_hw *, uint16_t, uint16_t *);
+	int32_t (*write)(struct ixgbe_hw *, uint16_t, uint16_t);
+	int32_t (*validate_checksum)(struct ixgbe_hw *, uint16_t *);
+	int32_t (*update_checksum)(struct ixgbe_hw *);
 };
 
 struct ixgbe_mac_operations {
-	s32 (*init_hw)(struct ixgbe_hw *);
-	s32 (*reset_hw)(struct ixgbe_hw *);
-	s32 (*start_hw)(struct ixgbe_hw *);
-	s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
+	int32_t (*init_hw)(struct ixgbe_hw *);
+	int32_t (*reset_hw)(struct ixgbe_hw *);
+	int32_t (*start_hw)(struct ixgbe_hw *);
+	int32_t (*clear_hw_cntrs)(struct ixgbe_hw *);
 	enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
-	s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
-	s32 (*stop_adapter)(struct ixgbe_hw *);
-	s32 (*get_bus_info)(struct ixgbe_hw *);
-	s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
-	s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
+	int32_t (*get_mac_addr)(struct ixgbe_hw *, uint8_t *);
+	int32_t (*stop_adapter)(struct ixgbe_hw *);
+	int32_t (*get_bus_info)(struct ixgbe_hw *);
+	int32_t (*read_analog_reg8)(struct ixgbe_hw*, uint32_t, uint8_t*);
+	int32_t (*write_analog_reg8)(struct ixgbe_hw*, uint32_t, uint8_t);
 
 	/* Link */
-	s32 (*setup_link)(struct ixgbe_hw *);
-	s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
-	                        bool);
-	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
-	s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
-	                             bool *);
+	int32_t (*setup_link)(struct ixgbe_hw *);
+	int32_t (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, int,
+	                        int);
+	int32_t (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, int *, int);
+	int32_t (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
+	                             int *);
 
 	/* LED */
-	s32 (*led_on)(struct ixgbe_hw *, u32);
-	s32 (*led_off)(struct ixgbe_hw *, u32);
-	s32 (*blink_led_start)(struct ixgbe_hw *, u32);
-	s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
+	int32_t (*led_on)(struct ixgbe_hw *, uint32_t);
+	int32_t (*led_off)(struct ixgbe_hw *, uint32_t);
+	int32_t (*blink_led_start)(struct ixgbe_hw *, uint32_t);
+	int32_t (*blink_led_stop)(struct ixgbe_hw *, uint32_t);
 
 	/* RAR, Multicast, VLAN */
-	s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
-	s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
-	s32 (*init_rx_addrs)(struct ixgbe_hw *);
-	s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
+	int32_t (*set_rar)(struct ixgbe_hw *, uint32_t, uint8_t *, uint32_t, uint32_t);
+	int32_t (*set_vmdq)(struct ixgbe_hw *, uint32_t, uint32_t);
+	int32_t (*init_rx_addrs)(struct ixgbe_hw *);
+	int32_t (*update_uc_addr_list)(struct ixgbe_hw *, uint8_t *, uint32_t,
 	                           ixgbe_mc_addr_itr);
-	s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
+	int32_t (*update_mc_addr_list)(struct ixgbe_hw *, uint8_t *, uint32_t,
 	                           ixgbe_mc_addr_itr);
-	s32 (*enable_mc)(struct ixgbe_hw *);
-	s32 (*disable_mc)(struct ixgbe_hw *);
-	s32 (*clear_vfta)(struct ixgbe_hw *);
-	s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
+	int32_t (*enable_mc)(struct ixgbe_hw *);
+	int32_t (*disable_mc)(struct ixgbe_hw *);
+	int32_t (*clear_vfta)(struct ixgbe_hw *);
+	int32_t (*set_vfta)(struct ixgbe_hw *, uint32_t, uint32_t, int);
 
 	/* Flow Control */
-	s32 (*setup_fc)(struct ixgbe_hw *, s32);
+	int32_t (*setup_fc)(struct ixgbe_hw *, int32_t);
 };
 
 struct ixgbe_phy_operations {
-	s32 (*identify)(struct ixgbe_hw *);
-	s32 (*reset)(struct ixgbe_hw *);
-	s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
-	s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
-	s32 (*setup_link)(struct ixgbe_hw *);
-	s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
-	                        bool);
-	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
-	s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
+	int32_t (*identify)(struct ixgbe_hw *);
+	int32_t (*reset)(struct ixgbe_hw *);
+	int32_t (*read_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t *);
+	int32_t (*write_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t);
+	int32_t (*setup_link)(struct ixgbe_hw *);
+	int32_t (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, int,
+	                        int);
+	int32_t (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, int *);
+	int32_t (*get_firmware_version)(struct ixgbe_hw *, uint16_t *);
 };
 
 struct ixgbe_eeprom_info {
 	struct ixgbe_eeprom_operations  ops;
 	enum ixgbe_eeprom_type          type;
-	u16                             word_size;
-	u16                             address_bits;
+	uint16_t			word_size;
+	uint16_t			address_bits;
 };
 
 struct ixgbe_mac_info {
 	struct ixgbe_mac_operations     ops;
 	enum ixgbe_mac_type             type;
-	u8                              addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
-	u8                              perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
-	s32                             mc_filter_type;
-	u32                             mcft_size;
-	u32                             vft_size;
-	u32                             num_rar_entries;
-	u32                             max_tx_queues;
-	u32                             max_rx_queues;
-	u32                             link_attach_type;
-	u32                             link_mode_select;
-	bool                            link_settings_loaded;
-	bool                            autoneg;
-	bool                            autoneg_failed;
+	uint8_t                        addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
+	uint8_t                        perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
+	int32_t                         mc_filter_type;
+	uint32_t                       mcft_size;
+	uint32_t                       vft_size;
+	uint32_t                       num_rar_entries;
+	uint32_t                       max_tx_queues;
+	uint32_t                       max_rx_queues;
+	uint32_t                       link_attach_type;
+	uint32_t                       link_mode_select;
+	int                             link_settings_loaded;
+	int                             autoneg;
+	int                             autoneg_failed;
 };
 
 struct ixgbe_phy_info {
 	struct ixgbe_phy_operations     ops;
 	enum ixgbe_phy_type             type;
-	u32                             addr;
-	u32                             id;
-	u32                             revision;
+	uint32_t                       addr;
+	uint32_t                       id;
+	uint32_t                       revision;
 	enum ixgbe_media_type           media_type;
-	bool                            reset_disable;
+	int                             reset_disable;
 	ixgbe_autoneg_advertised        autoneg_advertised;
-	bool                            autoneg_wait_to_complete;
+	int                             autoneg_wait_to_complete;
 };
 
 struct ixgbe_hw {
-	u8                              *hw_addr;
+	uint8_t                        *hw_addr;
 	void                            *back;
 	struct ixgbe_mac_info           mac;
 	struct ixgbe_addr_filter_info   addr_ctrl;
@@ -1518,12 +1518,12 @@ struct ixgbe_hw {
 	struct ixgbe_phy_info           phy;
 	struct ixgbe_eeprom_info        eeprom;
 	struct ixgbe_bus_info           bus;
-	u16                             device_id;
-	u16                             vendor_id;
-	u16                             subsystem_device_id;
-	u16                             subsystem_vendor_id;
-	u8                              revision_id;
-	bool                            adapter_stopped;
+	uint16_t                       device_id;
+	uint16_t                       vendor_id;
+	uint16_t                       subsystem_device_id;
+	uint16_t                       subsystem_vendor_id;
+	uint8_t                        revision_id;
+	int                             adapter_stopped;
 };
 
 #define ixgbe_hw(hw, func, ...)						\