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authorJonathan Gray <jsg@cvs.openbsd.org>2019-07-04 03:09:50 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2019-07-04 03:09:50 +0000
commit4c5f102df12a7a3bdb85227f4ebbea7bd934b002 (patch)
treebde7fbbba23063a2d129a13e5e6cc065360da4cf
parent3ba83cf6969443259568ff5e70c2fb7b570d771a (diff)
drm/amd/display/dm: add picasso support
From Likun Gao b22ab73314c0dfa91ac1948812c7e8050240c563 in mainline linux
-rw-r--r--sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c1
-rw-r--r--sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c8
2 files changed, 7 insertions, 2 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
index 01e88958198..8dbbdf363e3 100644
--- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
+++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
@@ -2350,6 +2350,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
case CHIP_VEGA20:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
+ case CHIP_PICASSO:
#endif
return amdgpu_dc != 0;
#endif
diff --git a/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 05fd91cdf15..a7cd2606797 100644
--- a/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1252,7 +1252,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 ||
adev->asic_type == CHIP_VEGA20 ||
- adev->asic_type == CHIP_RAVEN)
+ adev->asic_type == CHIP_RAVEN ||
+ adev->asic_type == CHIP_PICASSO)
client_id = SOC15_IH_CLIENTID_DCE;
int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -1679,6 +1680,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
+ case CHIP_PICASSO:
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail;
@@ -1863,6 +1865,7 @@ static int dm_early_init(void *handle)
break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
+ case CHIP_PICASSO:
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4;
@@ -2105,7 +2108,8 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 ||
adev->asic_type == CHIP_VEGA20 ||
- adev->asic_type == CHIP_RAVEN) {
+ adev->asic_type == CHIP_RAVEN ||
+ adev->asic_type == CHIP_PICASSO) {
/* Fill GFX9 params */
plane_state->tiling_info.gfx9.num_pipes =
adev->gfx.config.gb_addr_config_fields.num_pipes;