Some implementations of HitSyncDCache() call pmap_extract() for va->pa

conversion. Because pmap_extract() acquires the PTE mutex, a "locking
against myself" panic is triggered if the cache routine gets called in
a context where the mutex is already held.

In the pmap, all calls to HitSyncDCache() are for a whole page. Add a
new cache routine, HitSyncDCachePage(), which gets both the va and the
pa of a page. This removes the need of the va->pa conversion. The new
routine has the same signature as SyncDCachePage(), allowing reuse of
the same routine for cache implementations that do not need differences
between "Hit" and non-"Hit" routines.

With the diff, POWER Indigo2 R8000 boots multiuser again. Tested on sgi
GENERIC-IP27.MP and octeon GENERIC.MP, too.

Diff from miod@, ok kettenis@

14 files changed, 122 insertions, 30 deletions

diff --git a/sys/arch/loongson/include/cpu.h b/sys/arch/loongson/include/cpu.h
index 51d004f955c..6120b24e787 100644
--- a/sys/arch/loongson/include/cpu.h
+++ b/sys/arch/loongson/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.5 2015/08/15 22:31:38 miod Exp $ */
+/* $OpenBSD: cpu.h,v 1.6 2016/01/05 05:27:54 visa Exp $ */
 /*-
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -54,6 +54,8 @@
 	Loongson2_SyncICache((ci))
 #define	Mips_SyncDCachePage(ci, va, pa)		\
 	Loongson2_SyncDCachePage((ci), (va), (pa))
+#define	Mips_HitSyncDCachePage(ci, va, pa)	\
+	Loongson2_SyncDCachePage((ci), (va), (pa))
 #define	Mips_HitSyncDCache(ci, va, l)	\
 	Loongson2_HitSyncDCache((ci), (va), (l))
 #define	Mips_IOSyncDCache(ci, va, l, h)	\
@@ -73,6 +75,8 @@
 	Loongson3_SyncICache((ci))
 #define	Mips_SyncDCachePage(ci, va, pa)		\
 	Loongson3_SyncDCachePage((ci), (va), (pa))
+#define	Mips_HitSyncDCachePage(ci, va, pa)	\
+	Loongson3_SyncDCachePage((ci), (va), (pa))
 #define	Mips_HitSyncDCache(ci, va, l)	\
 	Loongson3_HitSyncDCache((ci), (va), (l))
 #define	Mips_IOSyncDCache(ci, va, l, h)	\
diff --git a/sys/arch/mips64/include/cache.h b/sys/arch/mips64/include/cache.h
index 2b9ece4037c..9e6bbae84db 100644
--- a/sys/arch/mips64/include/cache.h
+++ b/sys/arch/mips64/include/cache.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache.h,v 1.7 2015/08/15 22:31:38 miod Exp $	*/
+/*	$OpenBSD: cache.h,v 1.8 2016/01/05 05:27:54 visa Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -42,6 +42,8 @@ void	chip##_InvalidateICachePage(struct cpu_info *, vaddr_t); \
 void	chip##_SyncICache(struct cpu_info *); \
 /* Writeback all D$ for the given page */ \
 void	chip##_SyncDCachePage(struct cpu_info *, vaddr_t, paddr_t); \
+/* Writeback all D$ for the (currently mapped) given page */ \
+void	chip##_HitSyncDCachePage(struct cpu_info *, vaddr_t, paddr_t); \
 /* Writeback all D$ for the given range */ \
 void	chip##_HitSyncDCache(struct cpu_info *, vaddr_t, size_t); \
 /* Invalidate all D$ for the given range */ \
diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index ef610e49a90..503a84c0571 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.107 2015/12/25 08:34:50 visa Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.108 2016/01/05 05:27:54 visa Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -175,6 +175,8 @@ struct cpu_info {
 	void		(*ci_SyncICache)(struct cpu_info *);
 	void		(*ci_SyncDCachePage)(struct cpu_info *, vaddr_t,
 			    paddr_t);
+	void		(*ci_HitSyncDCachePage)(struct cpu_info *, vaddr_t,
+			    paddr_t);
 	void		(*ci_HitSyncDCache)(struct cpu_info *, vaddr_t, size_t);
 	void		(*ci_HitInvalidateDCache)(struct cpu_info *, vaddr_t,
 			    size_t);
@@ -509,6 +511,10 @@ u_int	cp1_get_prid(void);
 #define	Mips_SyncDCachePage(ci, va, pa) \
 	((ci)->ci_SyncDCachePage)(ci, va, pa)
 #endif
+#ifndef	Mips_HitSyncDCachePage
+#define	Mips_HitSyncDCachePage(ci, va, pa) \
+	((ci)->ci_HitSyncDCachePage)(ci, va, pa)
+#endif
 #ifndef	Mips_HitSyncDCache
 #define	Mips_HitSyncDCache(ci, va, l) \
 	((ci)->ci_HitSyncDCache)(ci, va, l)
diff --git a/sys/arch/mips64/mips64/cache_loongson2.c b/sys/arch/mips64/mips64/cache_loongson2.c
index 7d1e1b0a29c..36e3200e29d 100644
--- a/sys/arch/mips64/mips64/cache_loongson2.c
+++ b/sys/arch/mips64/mips64/cache_loongson2.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_loongson2.c,v 1.6 2014/03/31 20:21:19 miod Exp $	*/
+/*	$OpenBSD: cache_loongson2.c,v 1.7 2016/01/05 05:27:54 visa Exp $	*/
 
 /*
  * Copyright (c) 2009, 2012 Miodrag Vallat.
@@ -101,6 +101,7 @@ Loongson2_ConfigCache(struct cpu_info *ci)
 	ci->ci_InvalidateICachePage = Loongson2_InvalidateICachePage;
 	ci->ci_SyncICache = Loongson2_SyncICache;
 	ci->ci_SyncDCachePage = Loongson2_SyncDCachePage;
+	ci->ci_HitSyncDCachePage = Loongson2_SyncDCachePage;
 	ci->ci_HitSyncDCache = Loongson2_HitSyncDCache;
 	ci->ci_HitInvalidateDCache = Loongson2_HitInvalidateDCache;
 	ci->ci_IOSyncDCache = Loongson2_IOSyncDCache;
diff --git a/sys/arch/mips64/mips64/cache_loongson3.c b/sys/arch/mips64/mips64/cache_loongson3.c
index 1914f1d00bc..c3f7ee78e81 100644
--- a/sys/arch/mips64/mips64/cache_loongson3.c
+++ b/sys/arch/mips64/mips64/cache_loongson3.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_loongson3.c,v 1.1 2015/08/15 22:31:38 miod Exp $	*/
+/*	$OpenBSD: cache_loongson3.c,v 1.2 2016/01/05 05:27:54 visa Exp $	*/
 
 /*
  * Copyright (c) 2014 Miodrag Vallat.
@@ -39,6 +39,7 @@ Loongson3_ConfigCache(struct cpu_info *ci)
 	ci->ci_InvalidateICachePage = Loongson3_InvalidateICachePage;
 	ci->ci_SyncICache = Loongson3_SyncICache;
 	ci->ci_SyncDCachePage = Loongson3_SyncDCachePage;
+	ci->ci_HitSyncDCachePage = Loongson3_SyncDCachePage;
 	ci->ci_HitSyncDCache = Loongson3_HitSyncDCache;
 	ci->ci_HitInvalidateDCache = Loongson3_HitInvalidateDCache;
 	ci->ci_IOSyncDCache = Loongson3_IOSyncDCache;
diff --git a/sys/arch/mips64/mips64/cache_mips64r2.c b/sys/arch/mips64/mips64/cache_mips64r2.c
index 950ee4e80d5..5f1cfe55e74 100644
--- a/sys/arch/mips64/mips64/cache_mips64r2.c
+++ b/sys/arch/mips64/mips64/cache_mips64r2.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_mips64r2.c,v 1.1 2015/08/15 22:31:38 miod Exp $	*/
+/*	$OpenBSD: cache_mips64r2.c,v 1.2 2016/01/05 05:27:54 visa Exp $	*/
 
 /*
  * Copyright (c) 2014 Miodrag Vallat.
@@ -127,6 +127,7 @@ mips64r2_ConfigCache(struct cpu_info *ci)
 	ci->ci_InvalidateICachePage = mips64r2_InvalidateICachePage;
 	ci->ci_SyncICache = mips64r2_SyncICache;
 	ci->ci_SyncDCachePage = mips64r2_SyncDCachePage;
+	ci->ci_HitSyncDCachePage = mips64r2_HitSyncDCachePage;
 	ci->ci_HitSyncDCache = mips64r2_HitSyncDCache;
 	ci->ci_HitInvalidateDCache = mips64r2_HitInvalidateDCache;
 	ci->ci_IOSyncDCache = mips64r2_IOSyncDCache;
@@ -316,6 +317,18 @@ mips64r2_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 }
 
 /*
+ * Writeback D$ for the given page, which is expected to be currently
+ * mapped, allowing the use of `Hit' operations. This is less aggressive
+ * than using `Index' operations.
+ */
+
+void
+mips64r2_HitSyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
+{
+	mips64r2_hitwbinv_primary(va, PAGE_SIZE, ci->ci_l1data.linesize);
+}
+
+/*
  * Writeback D$ for the given range. Range is expected to be currently
  * mapped, allowing the use of `Hit' operations. This is less aggressive
  * than using `Index' operations.
diff --git a/sys/arch/mips64/mips64/cache_octeon.c b/sys/arch/mips64/mips64/cache_octeon.c
index 7aac0a43ae3..22b865e0d09 100644
--- a/sys/arch/mips64/mips64/cache_octeon.c
+++ b/sys/arch/mips64/mips64/cache_octeon.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_octeon.c,v 1.9 2014/08/12 04:30:21 miod Exp $	*/
+/*	$OpenBSD: cache_octeon.c,v 1.10 2016/01/05 05:27:54 visa Exp $	*/
 /*
  * Copyright (c) 2010 Takuya ASADA.
  *
@@ -121,6 +121,7 @@ Octeon_ConfigCache(struct cpu_info *ci)
 	ci->ci_InvalidateICachePage = Octeon_InvalidateICachePage;
 	ci->ci_SyncICache = Octeon_SyncICache;
 	ci->ci_SyncDCachePage = Octeon_SyncDCachePage;
+	ci->ci_HitSyncDCachePage = Octeon_SyncDCachePage;
 	ci->ci_HitSyncDCache = Octeon_HitSyncDCache;
 	ci->ci_HitInvalidateDCache = Octeon_HitInvalidateDCache;
 	ci->ci_IOSyncDCache = Octeon_IOSyncDCache;
diff --git a/sys/arch/mips64/mips64/cache_r10k.c b/sys/arch/mips64/mips64/cache_r10k.c
index b18ee6a464c..75105e2af7d 100644
--- a/sys/arch/mips64/mips64/cache_r10k.c
+++ b/sys/arch/mips64/mips64/cache_r10k.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r10k.c,v 1.6 2014/03/31 20:21:19 miod Exp $	*/
+/*	$OpenBSD: cache_r10k.c,v 1.7 2016/01/05 05:27:54 visa Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -102,6 +102,7 @@ Mips10k_ConfigCache(struct cpu_info *ci)
 	ci->ci_InvalidateICachePage = Mips10k_InvalidateICachePage;
 	ci->ci_SyncICache = Mips10k_SyncICache;
 	ci->ci_SyncDCachePage = Mips10k_SyncDCachePage;
+	ci->ci_HitSyncDCachePage = Mips10k_HitSyncDCachePage;
 	ci->ci_HitSyncDCache = Mips10k_HitSyncDCache;
 	ci->ci_HitInvalidateDCache = Mips10k_HitInvalidateDCache;
 	ci->ci_IOSyncDCache = Mips10k_IOSyncDCache;
@@ -311,6 +312,18 @@ Mips10k_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 }
 
 /*
+ * Writeback D$ for the given page, which is expected to be currently
+ * mapped, allowing the use of `Hit' operations. This is less aggressive
+ * than using `Index' operations.
+ */
+
+void
+Mips10k_HitSyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
+{
+	mips10k_hitwbinv_primary(va, PAGE_SIZE);
+}
+
+/*
  * Writeback D$ for the given range. Range is expected to be currently
  * mapped, allowing the use of `Hit' operations. This is less aggressive
  * than using `Index' operations.
diff --git a/sys/arch/mips64/mips64/cache_r4k.c b/sys/arch/mips64/mips64/cache_r4k.c
index b4b347f3fcc..255cf99372d 100644
--- a/sys/arch/mips64/mips64/cache_r4k.c
+++ b/sys/arch/mips64/mips64/cache_r4k.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r4k.c,v 1.14 2014/03/31 20:21:19 miod Exp $	*/
+/*	$OpenBSD: cache_r4k.c,v 1.15 2016/01/05 05:27:54 visa Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -121,6 +121,7 @@ Mips4k_ConfigCache(struct cpu_info *ci)
 	ci->ci_InvalidateICachePage = Mips4k_InvalidateICachePage;
 	ci->ci_SyncICache = Mips4k_SyncICache;
 	ci->ci_SyncDCachePage = Mips4k_SyncDCachePage;
+	ci->ci_HitSyncDCachePage = Mips4k_HitSyncDCachePage;
 	ci->ci_HitSyncDCache = Mips4k_HitSyncDCache;
 	ci->ci_HitInvalidateDCache = Mips4k_HitInvalidateDCache;
 	ci->ci_IOSyncDCache = Mips4k_IOSyncDCache;
@@ -294,12 +295,6 @@ Mips4k_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 	mips_sync();
 }
 
-/*
- * Writeback D$ for the given range. Range is expected to be currently
- * mapped, allowing the use of `Hit' operations. This is less aggressive
- * than using `Index' operations.
- */
-
 static __inline__ void
 mips4k_hitwbinv_primary(vaddr_t va, vsize_t sz, vsize_t line)
 {
@@ -324,6 +319,28 @@ mips4k_hitwbinv_secondary(vaddr_t va, vsize_t sz, vsize_t line)
 	}
 }
 
+/*
+ * Writeback D$ for the given page, which is expected to be currently
+ * mapped, allowing the use of `Hit' operations. This is less aggressive
+ * than using `Index' operations.
+ */
+
+void
+Mips4k_HitSyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
+{
+	mips4k_hitwbinv_primary(va, PAGE_SIZE, ci->ci_l1data.linesize);
+	if (ci->ci_l2.size != 0)
+		mips4k_hitwbinv_secondary(va, PAGE_SIZE, ci->ci_l2.linesize);
+
+	mips_sync();
+}
+
+/*
+ * Writeback D$ for the given range. Range is expected to be currently
+ * mapped, allowing the use of `Hit' operations. This is less aggressive
+ * than using `Index' operations.
+ */
+
 void
 Mips4k_HitSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 {
diff --git a/sys/arch/mips64/mips64/cache_r5k.c b/sys/arch/mips64/mips64/cache_r5k.c
index f59e11a127e..64d8a0b52e5 100644
--- a/sys/arch/mips64/mips64/cache_r5k.c
+++ b/sys/arch/mips64/mips64/cache_r5k.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r5k.c,v 1.14 2014/06/17 18:58:35 miod Exp $	*/
+/*	$OpenBSD: cache_r5k.c,v 1.15 2016/01/05 05:27:54 visa Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -422,6 +422,7 @@ Mips5k_ConfigCache(struct cpu_info *ci)
 	ci->ci_InvalidateICachePage = Mips5k_InvalidateICachePage;
 	ci->ci_SyncICache = Mips5k_SyncICache;
 	ci->ci_SyncDCachePage = Mips5k_SyncDCachePage;
+	ci->ci_HitSyncDCachePage = Mips5k_HitSyncDCachePage;
 	ci->ci_HitSyncDCache = Mips5k_HitSyncDCache;
 	ci->ci_HitInvalidateDCache = Mips5k_HitInvalidateDCache;
 	ci->ci_IOSyncDCache = Mips5k_IOSyncDCache;
@@ -781,6 +782,34 @@ Mips5k_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 }
 
 /*
+ * Writeback D$ for the given page, which is expected to be currently
+ * mapped, allowing the use of `Hit' operations. This is less aggressive
+ * than using `Index' operations.
+ */
+
+void
+Mips5k_HitSyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
+{
+	if (ci->ci_cacheconfiguration & CTYPE_HAS_IL2)
+		mips5k_hitwbinv_secondary(va, PAGE_SIZE);
+	else {
+#ifdef CPU_R4600
+		/*
+		 * R4600 revision 2 needs to load from an uncached address
+		 * before any Hit or CreateDEX operation. Alternatively, 12
+		 * nop (cycles) will empty the cache load buffer.
+		 * We are only putting 10 here, and hope the overhead of the
+		 * code around will provide the rest.
+		 */
+		nop10();
+#endif
+		mips5k_hitwbinv_primary(va, PAGE_SIZE);
+	}
+
+	mips_sync();
+}
+
+/*
  * Writeback D$ for the given range. Range is expected to be currently
  * mapped, allowing the use of `Hit' operations. This is less aggressive
  * than using `Index' operations.
diff --git a/sys/arch/mips64/mips64/cache_tfp.c b/sys/arch/mips64/mips64/cache_tfp.c
index 896c33ce5f7..50e47d5fa62 100644
--- a/sys/arch/mips64/mips64/cache_tfp.c
+++ b/sys/arch/mips64/mips64/cache_tfp.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_tfp.c,v 1.5 2015/09/20 11:50:05 miod Exp $	*/
+/*	$OpenBSD: cache_tfp.c,v 1.6 2016/01/05 05:27:54 visa Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -94,6 +94,7 @@ tfp_ConfigCache(struct cpu_info *ci)
 	ci->ci_InvalidateICachePage = tfp_InvalidateICachePage;
 	ci->ci_SyncICache = tfp_SyncICache;
 	ci->ci_SyncDCachePage = tfp_SyncDCachePage;
+	ci->ci_HitSyncDCachePage = tfp_SyncDCachePage;
 	ci->ci_HitSyncDCache = tfp_HitSyncDCache;
 	ci->ci_HitInvalidateDCache = tfp_HitInvalidateDCache;
 	ci->ci_IOSyncDCache = tfp_IOSyncDCache;
diff --git a/sys/arch/mips64/mips64/pmap.c b/sys/arch/mips64/mips64/pmap.c
index c3d58b86b69..5b1478897fb 100644
--- a/sys/arch/mips64/mips64/pmap.c
+++ b/sys/arch/mips64/mips64/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.82 2015/12/31 04:25:51 visa Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.83 2016/01/05 05:27:54 visa Exp $	*/
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -669,7 +669,7 @@ pmap_do_remove(pmap_t pmap, vaddr_t sva, vaddr_t eva)
 #endif
 		mtx_enter(&pmap->pm_pte_mtx);
 		pte = kvtopte(sva);
-		for(; sva < eva; sva += PAGE_SIZE, pte++) {
+		for (; sva < eva; sva += PAGE_SIZE, pte++) {
 			entry = *pte;
 			if (!(entry & PG_V))
 				continue;
@@ -678,7 +678,7 @@ pmap_do_remove(pmap_t pmap, vaddr_t sva, vaddr_t eva)
 			pmap->pm_stats.resident_count--;
 			pa = pfn_to_pad(entry);
 			if ((entry & PG_CACHEMODE) == PG_CACHED)
-				Mips_HitSyncDCache(ci, sva, PAGE_SIZE);
+				Mips_HitSyncDCachePage(ci, sva, pa);
 			*pte = PG_NV | PG_G;
 			/*
 			 * Flush the TLB for the given address.
@@ -879,7 +879,8 @@ pmap_protect(pmap_t pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
 				continue;
 			if ((entry & PG_M) != 0 /* && p != PG_M */)
 				if ((entry & PG_CACHEMODE) == PG_CACHED)
-					Mips_HitSyncDCache(ci, sva, PAGE_SIZE);
+					Mips_HitSyncDCachePage(ci, sva,
+					    pfn_to_pad(entry));
 			entry = (entry & ~(PG_M | PG_RO)) | p;
 			*pte = entry;
 			/*
@@ -1245,7 +1246,7 @@ pmap_kremove(vaddr_t va, vsize_t len)
 		if (!(entry & PG_V))
 			continue;
 		if ((entry & PG_CACHEMODE) == PG_CACHED)
-			Mips_HitSyncDCache(ci, va, PAGE_SIZE);
+			Mips_HitSyncDCachePage(ci, va, pfn_to_pad(entry));
 		*pte = PG_NV | PG_G;
 		pmap_invalidate_kernel_page(va);
 		pmap_kernel()->pm_stats.wired_count--;
@@ -1399,7 +1400,7 @@ pmap_zero_page(struct vm_page *pg)
 
 	mem_zero_page(va);
 	if (df || cache_valias_mask != 0)
-		Mips_HitSyncDCache(ci, va, PAGE_SIZE);
+		Mips_HitSyncDCachePage(ci, va, phys);
 
 #ifdef CPU_R4000
 	atomic_clearbits_int(&pg->pg_flags, PGF_EOP_CHECKED | PGF_EOP_VULN);
@@ -1458,7 +1459,7 @@ pmap_copy_page(struct vm_page *srcpg, struct vm_page *dstpg)
 	if (sf)
 		Mips_HitInvalidateDCache(ci, s, PAGE_SIZE);
 	if (df || cache_valias_mask != 0)
-		Mips_HitSyncDCache(ci, d, PAGE_SIZE);
+		Mips_HitSyncDCachePage(ci, d, dst);
 
 #ifdef CPU_R4000
 	atomic_clearbits_int(&dstpg->pg_flags, PGF_EOP_CHECKED | PGF_EOP_VULN);
@@ -1505,8 +1506,8 @@ pmap_clear_modify(struct vm_page *pg)
 			entry = *pte;
 			if ((entry & PG_V) != 0 && (entry & PG_M) != 0) {
 				if (pg->pg_flags & PGF_CACHED)
-					Mips_HitSyncDCache(ci, pv->pv_va,
-					    PAGE_SIZE);
+					Mips_HitSyncDCachePage(ci, pv->pv_va,
+					    pfn_to_pad(entry));
 				rv = TRUE;
 				entry &= ~PG_M;
 				*pte = entry;
@@ -1929,7 +1930,7 @@ pmap_pg_free(struct pool *pp, void *item)
 	vm_page_t pg = PHYS_TO_VM_PAGE(pa);
 
 	if (cache_valias_mask)
-		Mips_HitSyncDCache(curcpu(), va, PAGE_SIZE);
+		Mips_HitSyncDCachePage(curcpu(), va, pa);
 	uvm_pagefree(pg);
 }
 
@@ -1995,7 +1996,7 @@ pmap_unmap_direct(vaddr_t va)
 
 	pg = PHYS_TO_VM_PAGE(pa);
 	if (cache_valias_mask)
-		Mips_HitSyncDCache(curcpu(), va, PAGE_SIZE);
+		Mips_HitSyncDCachePage(curcpu(), va, pa);
 
 	return pg;
 }
diff --git a/sys/arch/octeon/include/cpu.h b/sys/arch/octeon/include/cpu.h
index da18f81f9eb..6e6963ba442 100644
--- a/sys/arch/octeon/include/cpu.h
+++ b/sys/arch/octeon/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.6 2014/03/31 20:21:19 miod Exp $ */
+/* $OpenBSD: cpu.h,v 1.7 2016/01/05 05:27:54 visa Exp $ */
 /*-
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -71,6 +71,8 @@ void hw_ipi_intr_clear(u_long);
 	Octeon_SyncICache((ci))
 #define	Mips_SyncDCachePage(ci, va, pa)		\
 	Octeon_SyncDCachePage((ci), (va), (pa))
+#define	Mips_HitSyncDCachePage(ci, va, pa)	\
+	Octeon_SyncDCachePage((ci), (va), (pa))
 #define	Mips_HitSyncDCache(ci, va, l)		\
 	Octeon_HitSyncDCache((ci), (va), (l))
 #define	Mips_IOSyncDCache(ci, va, l, h)		\
diff --git a/sys/arch/sgi/localbus/tcc.c b/sys/arch/sgi/localbus/tcc.c
index 9ac1155a64d..133f30c687d 100644
--- a/sys/arch/sgi/localbus/tcc.c
+++ b/sys/arch/sgi/localbus/tcc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tcc.c,v 1.8 2015/12/23 11:45:24 visa Exp $	*/
+/*	$OpenBSD: tcc.c,v 1.9 2016/01/05 05:27:54 visa Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -163,6 +163,7 @@ tcc_ConfigCache(struct cpu_info *ci)
 
 		ci->ci_SyncCache = tcc_SyncCache;
 		ci->ci_SyncDCachePage = tcc_SyncDCachePage;
+		ci->ci_HitSyncDCachePage = tcc_SyncDCachePage;
 		ci->ci_HitSyncDCache = tcc_HitSyncDCache;
 		ci->ci_HitInvalidateDCache = tcc_HitInvalidateDCache;
 		ci->ci_IOSyncDCache = tcc_IOSyncDCache;