diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2015-01-25 11:38:50 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2015-01-25 11:38:50 +0000 |
| commit | 563dccf6afb3703028c9fbe1aa643cc38e86388f (patch) | |
| tree | 058af3640e0dfb581256ca90a70443a7337a7a7a | |
| parent | ef4ef88e3f3bda32d3a88e8a883ce819bf4e2a83 (diff) | |
Correct a bit test for DDR2 CAS Latency and recognise CL7 and CL6.
While the spec only mentions bits for CL5->CL2 with the other
bits being marked 'TBD' it seems likely they are used now.
From David Vasek.
| -rw-r--r-- | sys/dev/spdmem.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/sys/dev/spdmem.c b/sys/dev/spdmem.c index 0d80c33261a..2aed6032a41 100644 --- a/sys/dev/spdmem.c +++ b/sys/dev/spdmem.c @@ -1,4 +1,4 @@ -/* $OpenBSD: spdmem.c,v 1.4 2015/01/19 18:38:41 miod Exp $ */ +/* $OpenBSD: spdmem.c,v 1.5 2015/01/25 11:38:49 jsg Exp $ */ /* $NetBSD: spdmem.c,v 1.3 2007/09/20 23:09:59 xtraeme Exp $ */ /* @@ -533,8 +533,8 @@ spdmem_ddr2_decode(struct spdmem_softc *sc, struct spdmem *s) } /* Print CAS latency */ - for (i = 5; i >= 2; i--) { - if (s->sm_data[SPDMEM_DDR_CAS] & (i << i)) { + for (i = 7; i >= 2; i--) { + if (s->sm_data[SPDMEM_DDR_CAS] & (1 << i)) { printf("CL%d", i); break; } |