diff options
| author | Patrick Wildt <patrick@cvs.openbsd.org> | 2019-09-09 20:00:52 +0000 |
|---|---|---|
| committer | Patrick Wildt <patrick@cvs.openbsd.org> | 2019-09-09 20:00:52 +0000 |
| commit | 59e994ee8a1a1edcf89e9aa49e2dd4586bda90b7 (patch) | |
| tree | b5926beba1700c9ca396b191d052ab641247d473 | |
| parent | f65a680dec4022d3a3424fdaee2cde5b9316dab3 (diff) | |
Update the bindings for imxsrc(4), since they changed when they were
upstreamed.
ok kettenis@
| -rw-r--r-- | sys/dev/fdt/imxsrc.c | 21 |
1 files changed, 8 insertions, 13 deletions
diff --git a/sys/dev/fdt/imxsrc.c b/sys/dev/fdt/imxsrc.c index 869d8effcb5..8a829d86ecb 100644 --- a/sys/dev/fdt/imxsrc.c +++ b/sys/dev/fdt/imxsrc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: imxsrc.c,v 1.2 2019/09/09 20:00:27 patrick Exp $ */ +/* $OpenBSD: imxsrc.c,v 1.3 2019/09/09 20:00:51 patrick Exp $ */ /* * Copyright (c) 2019 Patrick Wildt <patrick@blueri.se> * @@ -27,15 +27,13 @@ #include <dev/ofw/ofw_clock.h> #include <dev/ofw/fdt.h> -#define IMX8M_RESET_PCIEPHY 20 -#define IMX8M_RESET_PCIEPHY_PERST 21 -#define IMX8M_RESET_PCIE_CTRL_APPS_EN 22 -#define IMX8M_RESET_PCIE_CTRL_APPS_TURNOFF 25 -#define IMX8M_RESET_PCIE_CTRL_APPS_CLK_REQ 26 -#define IMX8M_RESET_PCIE2PHY 33 -#define IMX8M_RESET_PCIE2PHY_PERST 34 -#define IMX8M_RESET_PCIE2_CTRL_APPS_EN 35 -#define IMX8M_RESET_PCIE2_CTRL_APPS_CLK_REQ 36 +#define IMX8M_RESET_PCIEPHY 26 +#define IMX8M_RESET_PCIEPHY_PERST 27 +#define IMX8M_RESET_PCIE_CTRL_APPS_EN 28 +#define IMX8M_RESET_PCIE_CTRL_APPS_TURNOFF 29 +#define IMX8M_RESET_PCIE2PHY 34 +#define IMX8M_RESET_PCIE2PHY_PERST 35 +#define IMX8M_RESET_PCIE2_CTRL_APPS_EN 36 #define IMX8M_RESET_PCIE2_CTRL_APPS_TURNOFF 37 #define SRC_PCIE1_RCR 0x2c @@ -43,7 +41,6 @@ #define SRC_PCIE_RCR_PCIEPHY_G_RST (1 << 1) #define SRC_PCIE_RCR_PCIEPHY_BTN (1 << 2) #define SRC_PCIE_RCR_PCIEPHY_PERST (1 << 3) -#define SRC_PCIE_RCR_PCIE_CTRL_APPS_CLK_REQ (1 << 4) #define SRC_PCIE_RCR_PCIE_CTRL_APPS_EN (1 << 6) #define SRC_PCIE_RCR_PCIE_CTRL_APPS_TURNOFF (1 << 11) @@ -57,11 +54,9 @@ struct imxsrc_reset imx8m_resets[] = { [IMX8M_RESET_PCIEPHY_PERST] = { SRC_PCIE1_RCR, SRC_PCIE_RCR_PCIEPHY_PERST }, [IMX8M_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIE1_RCR, SRC_PCIE_RCR_PCIE_CTRL_APPS_EN }, [IMX8M_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIE1_RCR, SRC_PCIE_RCR_PCIE_CTRL_APPS_TURNOFF }, - [IMX8M_RESET_PCIE_CTRL_APPS_CLK_REQ] = { SRC_PCIE1_RCR, SRC_PCIE_RCR_PCIE_CTRL_APPS_CLK_REQ }, [IMX8M_RESET_PCIE2PHY] = { SRC_PCIE2_RCR, SRC_PCIE_RCR_PCIEPHY_G_RST | SRC_PCIE_RCR_PCIEPHY_BTN }, [IMX8M_RESET_PCIE2PHY_PERST] = { SRC_PCIE2_RCR, SRC_PCIE_RCR_PCIEPHY_PERST }, [IMX8M_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, SRC_PCIE_RCR_PCIE_CTRL_APPS_EN }, - [IMX8M_RESET_PCIE2_CTRL_APPS_CLK_REQ] = { SRC_PCIE2_RCR, SRC_PCIE_RCR_PCIE_CTRL_APPS_CLK_REQ }, [IMX8M_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, SRC_PCIE_RCR_PCIE_CTRL_APPS_TURNOFF }, }; |