Stricter type usage (width and signedness); first step towards 64 bit ptes.

5 files changed, 57 insertions, 56 deletions

diff --git a/sys/arch/mips64/include/pmap.h b/sys/arch/mips64/include/pmap.h
index 42acde5fd7c..26c379b7ca0 100644
--- a/sys/arch/mips64/include/pmap.h
+++ b/sys/arch/mips64/include/pmap.h
@@ -1,4 +1,4 @@
-/*      $OpenBSD: pmap.h,v 1.14 2007/10/18 04:32:09 miod Exp $ */
+/*      $OpenBSD: pmap.h,v 1.15 2009/11/18 20:58:50 miod Exp $ */
 
 /*
  * Copyright (c) 1987 Carnegie-Mellon University
@@ -81,7 +81,7 @@ typedef struct pmap {
 	int			pm_count;	/* pmap reference count */
 	simple_lock_data_t	pm_lock;	/* lock on pmap */
 	struct pmap_statistics	pm_stats;	/* pmap statistics */
-	int			pm_tlbpid;	/* address space tag */
+	u_int			pm_tlbpid;	/* address space tag */
 	u_int			pm_tlbgen;	/* TLB PID generation number */
 	struct segtab		*pm_segtab;	/* pointers to pages of PTEs */
 } *pmap_t;
@@ -108,7 +108,7 @@ extern	struct pmap kernel_pmap_store;
 #define	pmap_update(x)			do { /* nothing */ } while (0)
 
 void	pmap_bootstrap(void);
-int	pmap_is_page_ro( pmap_t, vaddr_t, int);
+int	pmap_is_page_ro( pmap_t, vaddr_t, pt_entry_t);
 void	pmap_kenter_cache(vaddr_t va, paddr_t pa, vm_prot_t prot, int cache);
 void	pmap_prefer(vaddr_t, vaddr_t *);
 void	pmap_set_modify(vm_page_t);
diff --git a/sys/arch/mips64/include/pte.h b/sys/arch/mips64/include/pte.h
index 179aa4f6376..b2490befd85 100644
--- a/sys/arch/mips64/include/pte.h
+++ b/sys/arch/mips64/include/pte.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pte.h,v 1.7 2008/04/07 22:30:05 miod Exp $	*/
+/*	$OpenBSD: pte.h,v 1.8 2009/11/18 20:58:50 miod Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -58,23 +58,24 @@ typedef u_int32_t pt_entry_t;	/* Mips page table entry */
 
 #endif /* _LOCORE */
 
+/* entryhi values */
+#define	PG_SVPN		0xfffffffffffff000	/* Software page no mask */
+#define	PG_HVPN		0xffffffffffffe000	/* Hardware page no mask */
+#define	PG_ODDPG	0x0000000000001000	/* Odd even pte entry */
+#define	PG_ASID		0x00000000000000ff	/* Address space ID */
+/* entrylo values */
 #define PG_RO		0x40000000	/* SW */
-
-#define	PG_SVPN		0xfffff000	/* Software page no mask */
-#define	PG_HVPN		0xffffe000	/* Hardware page no mask */
-#define	PG_ODDPG	0x00001000	/* Odd even pte entry */
-#define	PG_ASID		0x000000ff	/* Address space ID */
 #define	PG_G		0x00000001	/* HW */
 #define	PG_V		0x00000002
 #define	PG_NV		0x00000000
 #define	PG_M		0x00000004
-#define	PG_ATTR		0x0000003f
 #define	PG_UNCACHED	(CCA_NC << 3)
 #define	PG_CACHED_NC	(CCA_NONCOHERENT << 3)
 #define	PG_CACHED_CE	(CCA_COHERENT_EXCL << 3)
 #define	PG_CACHED_CEW	(CCA_COHERENT_EXCLWRITE << 3)
-#define	PG_CACHEMODE	0x00000038
 #define	PG_CACHED	(CCA_CACHED << 3)
+#define	PG_CACHEMODE	0x00000038
+#define	PG_ATTR		0x0000003f
 #define	PG_ROPAGE	(PG_V | PG_RO | PG_CACHED) /* Write protected */
 #define	PG_RWPAGE	(PG_V | PG_M | PG_CACHED)  /* Not w-prot not clean */
 #define	PG_CWPAGE	(PG_V | PG_CACHED)	   /* Not w-prot but clean */
@@ -82,10 +83,8 @@ typedef u_int32_t pt_entry_t;	/* Mips page table entry */
 #define	PG_FRAME	0x3fffffc0
 #define PG_SHIFT	6
 
-#define	pfn_to_pad(x)	(((vaddr_t)(x) & PG_FRAME) << PG_SHIFT)
-#define vad_to_pfn(x)	(((vaddr_t)(x) >> PG_SHIFT) & PG_FRAME)
-/* User virtual to pte page entry */
-#define uvtopte(adr)	(((adr) >> PGSHIFT) & (NPTEPG -1))
+#define	pfn_to_pad(pa)	(((pa) & PG_FRAME) << PG_SHIFT)
+#define vad_to_pfn(va)	(((va) >> PG_SHIFT) & PG_FRAME)
 
 #define	PG_SIZE_4K	0x00000000
 #define	PG_SIZE_16K	0x00006000
@@ -97,11 +96,11 @@ typedef u_int32_t pt_entry_t;	/* Mips page table entry */
 
 #if defined(_KERNEL) && !defined(_LOCORE)
 
-/*
- * Kernel virtual address to page table entry and visa versa.
- */
+/* Kernel virtual address to page table entry */
 #define	kvtopte(va) \
 	(Sysmap + (((vaddr_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT))
+/* User virtual address to pte page entry */
+#define uvtopte(adr)	(((adr) >> PGSHIFT) & (NPTEPG -1))
 
 extern	pt_entry_t *Sysmap;		/* kernel pte table */
 extern	u_int Sysmapsize;		/* number of pte's in Sysmap */
diff --git a/sys/arch/mips64/mips64/pmap.c b/sys/arch/mips64/mips64/pmap.c
index b3aa1afb44a..98073cd1fee 100644
--- a/sys/arch/mips64/mips64/pmap.c
+++ b/sys/arch/mips64/mips64/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.37 2009/07/23 19:24:55 miod Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.38 2009/11/18 20:58:51 miod Exp $	*/
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -58,8 +58,8 @@ struct pool pmap_pv_pool;
 #endif
 int	pmap_pv_lowat = PMAP_PV_LOWAT;
 
-int	pmap_alloc_tlbpid(struct proc *);
-int	pmap_enter_pv(pmap_t, vaddr_t, vm_page_t, u_int *);
+uint	pmap_alloc_tlbpid(struct proc *);
+int	pmap_enter_pv(pmap_t, vaddr_t, vm_page_t, pt_entry_t *);
 int	pmap_page_alloc(vaddr_t *);
 void	pmap_page_free(vaddr_t);
 void	pmap_page_cache(vm_page_t, int);
@@ -127,7 +127,7 @@ vaddr_t	virtual_start;  /* VA of first avail page (after kernel bss)*/
 vaddr_t	virtual_end;	/* VA of last avail page (end of kernel AS) */
 
 u_int		tlbpid_gen = 1;		/* TLB PID generation count */
-int		tlbpid_cnt = 2;		/* next available TLB PID */
+u_int		tlbpid_cnt = 2;		/* next available TLB PID */
 
 pt_entry_t	*Sysmap;		/* kernel pte table */
 u_int		Sysmapsize;		/* number of pte's in Sysmap */
@@ -184,7 +184,7 @@ vaddr_t
 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp)
 {
 	int i, j;
-	int npg;
+	uint npg;
 	vaddr_t va;
 	paddr_t pa;
 
@@ -228,11 +228,10 @@ pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp)
 		 * If we are running with a 32 bit ARCBios (i.e. kernel
 		 * linked in KSEG0), return a KSEG0 address whenever possible.
 		 */
-		if ((vaddr_t)&pmap_steal_memory - KSEG0_BASE < KSEG_SIZE &&
-		    pa + size < KSEG_SIZE)
-			va = PHYS_TO_KSEG0(pa);
-		else
+		if (IS_XKPHYS((vaddr_t)&pmap_steal_memory))
 			va = PHYS_TO_XKPHYS(pa, CCA_CACHED);
+		else
+			va = PHYS_TO_KSEG0(pa);
 
 		bzero((void *)va, size);
 		return (va);
@@ -471,8 +470,8 @@ pmap_remove(pmap_t pmap, vaddr_t sva, vaddr_t eva)
 			 * Flush the TLB for the given address.
 			 */
 			if (pmap->pm_tlbgen == tlbpid_gen) {
-				tlb_flush_addr(sva | (pmap->pm_tlbpid <<
-					VMTLB_PID_SHIFT));
+				tlb_flush_addr(sva |
+				    (pmap->pm_tlbpid << VMTLB_PID_SHIFT));
 				stat_count(remove_stats.flushes);
 			}
 		}
@@ -615,8 +614,9 @@ pmap_protect(pmap_t pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
 			entry = (entry & ~(PG_M | PG_RO)) | p;
 			*pte = entry;
 			if (pmap->pm_tlbgen == tlbpid_gen)
-				tlb_update(sva | (pmap->pm_tlbpid <<
-					VMTLB_PID_SHIFT), entry);
+				tlb_update(sva |
+				    (pmap->pm_tlbpid << VMTLB_PID_SHIFT),
+				    entry);
 		}
 	}
 }
@@ -752,7 +752,7 @@ pmap_enter(pmap_t pmap, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags)
 	 */
 	npte |= vad_to_pfn(pa);
 	if (pmap->pm_tlbgen == tlbpid_gen) {
-		DPRINTF(PDB_ENTER, ("pmap_enter: new pte %x tlbpid %d\n",
+		DPRINTF(PDB_ENTER, ("pmap_enter: new pte 0x%08x tlbpid %u\n",
 			npte, pmap->pm_tlbpid));
 	} else {
 		DPRINTF(PDB_ENTER, ("pmap_enter: new pte 0x%08x\n", npte));
@@ -960,12 +960,12 @@ pmap_copy_page(struct vm_page *srcpg, struct vm_page *dstpg)
 
 	pv = pg_to_pvh(srcpg);
 	if ((srcpg->pg_flags & PV_CACHED) &&
-	    (sf = ((pv->pv_va ^ (long)s) & CpuCacheAliasMask) != 0)) {
+	    (sf = ((pv->pv_va ^ s) & CpuCacheAliasMask) != 0)) {
 		Mips_SyncDCachePage(pv->pv_va);
 	}
 	pv = pg_to_pvh(dstpg);
 	if ((dstpg->pg_flags & PV_CACHED) &&
-	    (df = ((pv->pv_va ^ (long)d) & CpuCacheAliasMask) != 0)) {
+	    (df = ((pv->pv_va ^ d) & CpuCacheAliasMask) != 0)) {
 		Mips_SyncDCachePage(pv->pv_va);
 	}
 
@@ -1020,8 +1020,9 @@ pmap_clear_modify(struct vm_page *pg)
 				entry &= ~PG_M;
 				*pte = entry;
 				if (pv->pv_pmap->pm_tlbgen == tlbpid_gen)
-					tlb_update(pv->pv_va | (pv->pv_pmap->pm_tlbpid <<
-						VMTLB_PID_SHIFT), entry);
+					tlb_update(pv->pv_va |
+					    (pv->pv_pmap->pm_tlbpid <<
+					      VMTLB_PID_SHIFT), entry);
 			}
 		}
 	}
@@ -1085,7 +1086,7 @@ pmap_is_modified(struct vm_page *pg)
  *	Return RO protection of page.
  */
 int
-pmap_is_page_ro(pmap_t pmap, vaddr_t va, int entry)
+pmap_is_page_ro(pmap_t pmap, vaddr_t va, pt_entry_t entry)
 {
 	return (entry & PG_RO);
 }
@@ -1100,7 +1101,7 @@ pmap_page_cache(vm_page_t pg, int mode)
 {
 	pv_entry_t pv;
 	pt_entry_t *pte, entry;
-	u_int newmode;
+	pt_entry_t newmode;
 	int s;
 
 	DPRINTF(PDB_FOLLOW|PDB_ENTER, ("pmap_page_uncache(%p)\n", pg));
@@ -1126,8 +1127,9 @@ pmap_page_cache(vm_page_t pg, int mode)
 					entry = (entry & ~PG_CACHEMODE) | newmode;
 					*pte = entry;
 					if (pv->pv_pmap->pm_tlbgen == tlbpid_gen)
-						tlb_update(pv->pv_va | (pv->pv_pmap->pm_tlbpid <<
-							VMTLB_PID_SHIFT), entry);
+						tlb_update(pv->pv_va |
+						    (pv->pv_pmap->pm_tlbpid <<
+						     VMTLB_PID_SHIFT), entry);
 				}
 			}
 		}
@@ -1174,11 +1176,11 @@ pmap_page_free(vaddr_t va)
  * and start over. PID zero is reserved for kernel use.
  * This is called only by switch().
  */
-int
+uint
 pmap_alloc_tlbpid(struct proc *p)
 {
 	pmap_t pmap;
-	int id;
+	uint id;
 
 	pmap = p->p_vmspace->vm_map.pmap;
 	if (pmap->pm_tlbgen != tlbpid_gen) {
@@ -1205,7 +1207,7 @@ pmap_alloc_tlbpid(struct proc *p)
 		DPRINTF(PDB_FOLLOW|PDB_TLBPID, 
 			("pmap_alloc_tlbpid: curproc <none> "));
 	}
-	DPRINTF(PDB_FOLLOW|PDB_TLBPID, ("segtab %p tlbpid %d pid %d '%s'\n",
+	DPRINTF(PDB_FOLLOW|PDB_TLBPID, ("segtab %p tlbpid %u pid %d '%s'\n",
 			pmap->pm_segtab, id, p->p_pid, p->p_comm));
 
 	return (id);
@@ -1215,7 +1217,7 @@ pmap_alloc_tlbpid(struct proc *p)
  * Enter the pmap and virtual address into the physical to virtual map table.
  */
 int
-pmap_enter_pv(pmap_t pmap, vaddr_t va, vm_page_t pg, u_int *npte)
+pmap_enter_pv(pmap_t pmap, vaddr_t va, vm_page_t pg, pt_entry_t *npte)
 {
 	pv_entry_t pv, npv;
 	int s;
diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S
index 022b73a55c1..89763be15fb 100644
--- a/sys/arch/mips64/mips64/tlbhandler.S
+++ b/sys/arch/mips64/mips64/tlbhandler.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tlbhandler.S,v 1.20 2009/09/30 06:22:00 syuu Exp $ */
+/*	$OpenBSD: tlbhandler.S,v 1.21 2009/11/18 20:58:52 miod Exp $ */
 
 /*
  * Copyright (c) 1995-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -499,7 +499,7 @@ LEAF(tlb_flush_addr, 0)
 	xori	v0, v0, SR_INT_ENAB
 	mtc0	v0, COP_0_STATUS_REG	# Disable interrupts
 	ITLBNOPFIX
-	li	v0, (PG_HVPN | PG_ASID)
+	dli	v0, (PG_HVPN | PG_ASID)
 	and	a0, a0, v0		# Make sure valid hi value.
 	dmfc0	ta0, COP_0_TLB_HI	# Get current PID
 	dmtc0	a0, COP_0_TLB_HI	# look for addr & PID
@@ -559,8 +559,8 @@ LEAF(tlb_update, 0)
 	xori	v0, v0, SR_INT_ENAB
 	mtc0	v0, COP_0_STATUS_REG	# Disable interrupts
 	ITLBNOPFIX
-	and	ta1, a0, 0x1000		# ta1 = Even/Odd flag
-	li	v0, (PG_HVPN | PG_ASID)
+	and	ta1, a0, PG_ODDPG	# ta1 = Even/Odd flag
+	dli	v0, (PG_HVPN | PG_ASID)
 	and	a0, a0, v0
 	dmfc0	ta0, COP_0_TLB_HI	# Save current PID
 	dmtc0	a0, COP_0_TLB_HI	# Init high reg
diff --git a/sys/arch/mips64/mips64/trap.c b/sys/arch/mips64/mips64/trap.c
index 46ce38d202e..95ee0ca4638 100644
--- a/sys/arch/mips64/mips64/trap.c
+++ b/sys/arch/mips64/mips64/trap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: trap.c,v 1.46 2009/10/22 20:10:44 miod Exp $	*/
+/*	$OpenBSD: trap.c,v 1.47 2009/11/18 20:58:52 miod Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -423,7 +423,7 @@ printf("SIG-BUSB @%p pc %p, ra %p\n", trapframe->badvaddr, trapframe->pc, trapfr
 
 		/* compute next PC after syscall instruction */
 		tpc = trapframe->pc; /* Remember if restart */
-		if ((int)trapframe->cause & CR_BR_DELAY) {
+		if (trapframe->cause & CR_BR_DELAY) {
 			locr0->pc = MipsEmulateBranch(locr0, trapframe->pc, 0, 0);
 		}
 		else {
@@ -613,7 +613,7 @@ printf("SIG-BUSB @%p pc %p, ra %p\n", trapframe->badvaddr, trapframe->pc, trapfr
 
 		/* compute address of break instruction */
 		va = (caddr_t)trapframe->pc;
-		if ((int)trapframe->cause & CR_BR_DELAY)
+		if (trapframe->cause & CR_BR_DELAY)
 			va += 4;
 
 		/* read break instruction */
@@ -630,7 +630,7 @@ printf("SIG-BUSB @%p pc %p, ra %p\n", trapframe->badvaddr, trapframe->pc, trapfr
 			i = SIGFPE;
 			typ = FPE_FLTSUB;
 			/* skip instruction */
-			if ((int)trapframe->cause & CR_BR_DELAY)
+			if (trapframe->cause & CR_BR_DELAY)
 				locr0->pc = MipsEmulateBranch(locr0,
 				    trapframe->pc, 0, 0);
 			else
@@ -640,7 +640,7 @@ printf("SIG-BUSB @%p pc %p, ra %p\n", trapframe->badvaddr, trapframe->pc, trapfr
 			i = SIGFPE;
 			typ = FPE_FLTDIV;	/* XXX FPE_INTDIV ? */
 			/* skip instruction */
-			if ((int)trapframe->cause & CR_BR_DELAY)
+			if (trapframe->cause & CR_BR_DELAY)
 				locr0->pc = MipsEmulateBranch(locr0,
 				    trapframe->pc, 0, 0);
 			else
@@ -697,7 +697,7 @@ printf("SIG-BUSB @%p pc %p, ra %p\n", trapframe->badvaddr, trapframe->pc, trapfr
 		caddr_t va;
 		/* compute address of trapped instruction */
 		va = (caddr_t)trapframe->pc;
-		if ((int)trapframe->cause & CR_BR_DELAY)
+		if (trapframe->cause & CR_BR_DELAY)
 			va += 4;
 		printf("watch exception @ %p\n", va);
 #ifdef RM7K_PERFCNTR
@@ -719,12 +719,12 @@ printf("SIG-BUSB @%p pc %p, ra %p\n", trapframe->badvaddr, trapframe->pc, trapfr
 
 		/* compute address of trap instruction */
 		va = (caddr_t)trapframe->pc;
-		if ((int)trapframe->cause & CR_BR_DELAY)
+		if (trapframe->cause & CR_BR_DELAY)
 			va += 4;
 		/* read break instruction */
 		copyin(va, &instr, sizeof(int32_t));
 
-		if ((int)trapframe->cause & CR_BR_DELAY) {
+		if (trapframe->cause & CR_BR_DELAY) {
 			locr0->pc = MipsEmulateBranch(locr0, trapframe->pc, 0, 0);
 		} else {
 			locr0->pc += 4;