initial support for 21264 systems.

from NetBSD.

12 files changed, 2017 insertions, 3 deletions

diff --git a/sys/arch/alpha/alpha/dec_6600.c b/sys/arch/alpha/alpha/dec_6600.c
new file mode 100644
index 00000000000..96b5b9ca2a6
--- /dev/null
+++ b/sys/arch/alpha/alpha/dec_6600.c
@@ -0,0 +1,318 @@
+/* $OpenBSD: dec_6600.c,v 1.1 2000/11/16 04:50:17 ericj Exp $ */
+/* $NetBSD: dec_6600.c,v 1.7 2000/06/20 03:48:54 matt Exp $ */
+
+/*
+ * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
+ * All rights reserved.
+ *
+ * Author: Chris G. Demetriou
+ * 
+ * Permission to use, copy, modify and distribute this software and
+ * its documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ * 
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ * 
+ * Carnegie Mellon requests users of this software to return to
+ *
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/termios.h>
+#include <dev/cons.h>
+
+#include <machine/rpb.h>
+#include <machine/autoconf.h>
+#include <machine/cpuconf.h>
+#include <machine/bus.h>
+
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+#include <dev/isa/isareg.h>
+#include <dev/isa/isavar.h>
+#include <dev/ic/i8042reg.h>
+#include <dev/ic/pckbcvar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <alpha/pci/tsreg.h>
+#include <alpha/pci/tsvar.h>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsiconf.h>
+#include <dev/ata/atavar.h>
+
+#if 0
+#include "pckbd.h"
+#endif
+
+#ifndef CONSPEED
+#define CONSPEED TTYDEF_SPEED
+#endif
+
+#define	DR_VERBOSE(f) while (0)
+
+static int comcnrate __attribute__((unused)) = CONSPEED;
+
+void dec_6600_init __P((void));
+static void dec_6600_cons_init __P((void));
+static void dec_6600_device_register __P((struct device *, void *));
+
+void
+dec_6600_init()
+{
+
+	platform.family = "6600";
+
+	if ((platform.model = alpha_dsr_sysname()) == NULL) {
+		/* XXX Don't know the system variations, yet. */
+		platform.model = alpha_unknown_sysname();
+	}
+
+	platform.iobus = "tsc";
+	platform.cons_init = dec_6600_cons_init;
+	platform.device_register = dec_6600_device_register;
+	STQP(TS_C_DIM0) = 0UL;
+	STQP(TS_C_DIM1) = 0UL;
+}
+
+static void
+dec_6600_cons_init()
+{
+	struct ctb *ctb;
+	u_int64_t ctbslot;
+	struct tsp_config *tsp;
+
+	ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
+	ctbslot = ctb->ctb_turboslot;
+
+	/* Console hose defaults to hose 0. */
+	tsp_console_hose = 0;
+
+	tsp = tsp_init(0, tsp_console_hose);
+
+	switch (ctb->ctb_term_type) {
+	case 2: 
+		/* serial console ... */
+		assert(CTB_TURBOSLOT_HOSE(ctbslot) == 0);
+		/* XXX */
+		{
+			/*
+			 * Delay to allow PROM putchars to complete.
+			 * FIFO depth * character time,
+			 * character time = (1000000 / (defaultrate / 10))
+			 */
+			DELAY(160000000 / comcnrate);
+
+			if(comcnattach(tsp->pc_iot, 0x3f8, comcnrate,
+			    COM_FREQ,
+			    (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8))
+				panic("can't init serial console");
+
+			break;
+		}
+
+	case 3:
+#if NPCKBD > 0
+		/* display console ... */
+		/* XXX */
+		(void) pckbc_cnattach(&tsp->pc_iot, IO_KBD, KBCMDP,
+		    PCKBC_KBD_SLOT);
+
+		if (CTB_TURBOSLOT_TYPE(ctbslot) ==
+		    CTB_TURBOSLOT_TYPE_ISA)
+			isa_display_console(&tsp->pc_iot, &tsp->pc_memt);
+		else {
+			/* The display PCI might be different */
+			tsp_console_hose = CTB_TURBOSLOT_HOSE(ctbslot);
+			tsp = tsp_init(0, tsp_console_hose);
+			pci_display_console(&tsp->pc_iot, &tsp->pc_memt,
+			    &tsp->pc_pc, CTB_TURBOSLOT_BUS(ctbslot),
+			    CTB_TURBOSLOT_SLOT(ctbslot), 0);
+		}
+#else
+		panic("not configured to use display && keyboard console");
+#endif
+		break;
+
+	default:
+		printf("ctb_term_type = 0x%lx ctb_turboslot = 0x%lx"
+		    " hose = %ld\n", ctb->ctb_term_type, ctbslot,
+		    CTB_TURBOSLOT_HOSE(ctbslot));
+
+		panic("consinit: unknown console type %ld\n",
+		    ctb->ctb_term_type);
+	}
+}
+
+static void
+dec_6600_device_register(dev, aux)
+	struct device *dev;
+	void *aux;
+{
+	static int found, initted, scsiboot, ideboot, netboot;
+	static struct device *primarydev, *pcidev, *scsidev;
+	struct bootdev_data *b = bootdev_data;
+	struct device *parent = dev->dv_parent;
+	struct cfdata *cf = dev->dv_cfdata;
+	struct cfdriver *cd = cf->cf_driver;
+
+	if (found)
+		return;
+
+	if (!initted) {
+		scsiboot = (strcmp(b->protocol, "SCSI") == 0);
+		netboot = (strcmp(b->protocol, "BOOTP") == 0) ||
+		    (strcmp(b->protocol, "MOP") == 0);
+		/*
+		 * Add an extra check to boot from ide drives:
+		 * Newer SRM firmware use the protocol identifier IDE,
+		 * older SRM firmware use the protocol identifier SCSI.
+		 */
+		ideboot = (strcmp(b->protocol, "IDE") == 0);
+		DR_VERBOSE(printf("scsiboot = %d, ideboot = %d, netboot = %d\n",
+		    scsiboot, ideboot, netboot));
+		initted = 1;
+	}
+	if (primarydev == NULL) {
+		if (strcmp(cd->cd_name, "tsp"))
+			return;
+		else {
+			struct tsp_attach_args *tsp = aux;
+
+			if (b->bus != tsp->tsp_slot)
+				return;
+			primarydev = dev;
+			DR_VERBOSE(printf("\nprimarydev = %s\n",
+			    primarydev->dv_xname));
+			return;
+		}
+	}
+	if (pcidev == NULL) {
+		if (parent != primarydev)
+			return;
+		if (strcmp(cd->cd_name, "pci"))
+			return;
+		else {
+			struct pcibus_attach_args *pba = aux;
+
+			if ((b->slot / 1000) != pba->pba_bus)
+				return;
+	
+			pcidev = dev;
+			DR_VERBOSE(printf("\npcidev = %s\n",
+			    pcidev->dv_xname));
+			return;
+		}
+	}
+	if ((ideboot || scsiboot) && (scsidev == NULL)) {
+		if (parent != pcidev)
+			return;
+		else {
+			struct pci_attach_args *pa = aux;
+
+			if (b->slot % 1000 / 100 != pa->pa_function)
+				return;
+			if (b->slot % 100 != pa->pa_device)
+				return;
+	
+			scsidev = dev;
+			DR_VERBOSE(printf("\nscsidev = %s\n",
+			    scsidev->dv_xname));
+			return;
+		}
+	}
+	if ((ideboot || scsiboot) &&
+	    (!strcmp(cd->cd_name, "sd") ||
+	     !strcmp(cd->cd_name, "st") ||
+	     !strcmp(cd->cd_name, "cd"))) {
+		struct scsibus_attach_args *sa = aux;
+
+		if (parent->dv_parent != scsidev)
+			return;
+
+		if (b->unit / 100 != sa->sa_sc_link->target)
+                        return;
+
+
+		/* XXX LUN! */
+
+		switch (b->boot_dev_type) {
+		case 0:
+			if (strcmp(cd->cd_name, "sd") &&
+			    strcmp(cd->cd_name, "cd"))
+				return;
+			break;
+		case 1:
+			if (strcmp(cd->cd_name, "st"))
+				return;
+			break;
+		default:
+			return;
+		}
+
+		/* we've found it! */
+		booted_device = dev;
+		DR_VERBOSE(printf("\nbooted_device = %s\n",
+		    booted_device->dv_xname));
+		found = 1;
+	}
+
+	/*
+	 * Support to boot from IDE drives.
+	 */
+	if ((ideboot || scsiboot) && !strcmp(cd->cd_name, "wd")) {
+		struct ata_atapi_attach *aa_link = aux;
+		if ((strncmp("pciide", parent->dv_xname, 6) != 0)) {
+			return;
+		} else {
+			if (parent != scsidev)
+				return;
+		}
+		DR_VERBOSE(printf("\nAtapi info: drive: %d, channel %d\n",
+		    aa_link->aa_drv_data->drive, aa_link->aa_channel));
+		DR_VERBOSE(printf("Bootdev info: unit: %d, channel: %d\n",
+		    b->unit, b->channel));
+		if (b->unit != aa_link->aa_drv_data->drive ||
+		    b->channel != aa_link->aa_channel)
+			return;
+
+		/* we've found it! */
+		booted_device = dev;
+		DR_VERBOSE(printf("booted_device = %s\n",
+		    booted_device->dv_xname));
+		found = 1;
+	}
+	if (netboot) {
+		if (parent != pcidev)
+			return;
+		else {
+			struct pci_attach_args *pa = aux;
+
+			if (b->slot % 1000 / 100 != pa->pa_function)
+				return;
+			if ((b->slot % 100) != pa->pa_device)
+				return;
+	
+			booted_device = dev;
+			DR_VERBOSE(printf("\nbooted_device = %s\n",
+			    booted_device->dv_xname));
+			found = 1;
+			return;
+		}
+	}
+}
diff --git a/sys/arch/alpha/conf/GENERIC b/sys/arch/alpha/conf/GENERIC
index 20a5027b667..8cdbbf35df5 100644
--- a/sys/arch/alpha/conf/GENERIC
+++ b/sys/arch/alpha/conf/GENERIC
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC,v 1.57 2000/11/16 04:30:01 ericj Exp $
+#	$OpenBSD: GENERIC,v 1.58 2000/11/16 04:50:18 ericj Exp $
 #	$NetBSD: GENERIC,v 1.31 1996/12/03 17:25:29 cgd Exp $
 #
 # Generic Alpha kernel.  Enough to get booted, etc., but not much more.
@@ -17,6 +17,7 @@ option		DEC_AXPPCI_33	# NoName:	AXPpci33, etc.
 option		DEC_EB164	# EB164:	AlphaPC 164
 option		DEC_2000_300	# "Jensen":	2000/300 (DECpc AXP 150)
 option		DEC_550		# Miata:	Digital Personal Workstation
+option		DEC_6600	# EV6:		264DP OEM Board
 
 option		PMAP_NEW
 option		UVM
@@ -40,6 +41,10 @@ config		bsd	swap generic
 mainbus0 at	root
 cpu*	at	mainbus0
 
+# EV6 Tsunami Core Logic
+tsc*	at	mainbus0
+
+
 # TurboChannel host bus adapter support
 tcasic*	at	mainbus0
 
@@ -64,12 +69,14 @@ fta*	at	tc? slot ? offset ?		# DEC DEFTA FDDI cards
 apecs*	at	mainbus?
 cia*	at	mainbus?
 lca*	at	mainbus?
+tsp*	at	tsc?
 
 # PCI bus support
 pci*	at	apecs?
 pci*	at	cia?
 pci*	at	lca?
 pci*	at	ppb?
+pci*	at	tsp?
 
 # PCI devices
 #ahc*	at	pci? dev ? function ?		# AHA-28xx SCSI
diff --git a/sys/arch/alpha/conf/files.alpha b/sys/arch/alpha/conf/files.alpha
index 0686e1e721b..9703c2f49e1 100644
--- a/sys/arch/alpha/conf/files.alpha
+++ b/sys/arch/alpha/conf/files.alpha
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.alpha,v 1.36 2000/11/16 04:30:01 ericj Exp $
+#	$OpenBSD: files.alpha,v 1.37 2000/11/16 04:50:18 ericj Exp $
 #	$NetBSD: files.alpha,v 1.32 1996/11/25 04:03:21 cgd Exp $
 #
 # alpha-specific configuration info
@@ -11,7 +11,7 @@ maxusers 2 8 64
 # this loses, but there's no way to define attributes which have attributes
 define	alpha_shared_intr
 file	arch/alpha/dev/shared_intr.c	alpha_shared_intr | dec_eb164 |
-					dec_kn20aa | dec_550
+					dec_kn20aa | dec_6600 | dec_550
 
 define	alpha_sgmap
 file	arch/alpha/common/sgmap_common.c alpha_sgmap | dec_3000_500
@@ -191,12 +191,24 @@ file	arch/alpha/pci/cia_bus_mem.c	cia
 file	arch/alpha/pci/cia_bwx_bus_io.c	cia
 file	arch/alpha/pci/cia_bwx_bus_mem.c	cia
 
+device  tsc { }
+attach  tsc at mainbus
+file    arch/alpha/pci/tsc.c            dec_6600
+
+device  tsp: pcibus, alpha_sgmap, alpha_pci_sgmap_pte64
+attach  tsp at tsc
+file    arch/alpha/pci/tsp_dma.c        tsp
+file    arch/alpha/pci/tsp_pci.c        tsp
+file    arch/alpha/pci/tsp_bus_io.c     tsp
+file    arch/alpha/pci/tsp_bus_mem.c    tsp
+
 file	arch/alpha/pci/pci_2100_a50.c	dec_2100_a50
 file	arch/alpha/pci/pci_axppci_33.c	dec_axppci_33
 file	arch/alpha/pci/pci_eb164.c	dec_eb164
 file	arch/alpha/pci/pci_eb164_intr.s	dec_eb164
 file	arch/alpha/pci/pci_kn20aa.c	dec_kn20aa
 file	arch/alpha/pci/pci_550.c	dec_550
+file	arch/alpha/pci/pci_6600.c	dec_6600
 
 #
 # PCI Bus devices
@@ -278,6 +290,7 @@ file	arch/alpha/alpha/dec_axppci_33.c	dec_axppci_33	needs-flag
 file	arch/alpha/alpha/dec_eb164.c		dec_eb164	needs-flag
 file	arch/alpha/alpha/dec_kn20aa.c		dec_kn20aa	needs-flag
 file	arch/alpha/alpha/dec_550.c		dec_550		needs-flag
+file    arch/alpha/alpha/dec_6600.c             dec_6600	needs-flag
 
 
 # OSF/1 Binary Compatibility (COMPAT_OSF1)
diff --git a/sys/arch/alpha/pci/pci_6600.c b/sys/arch/alpha/pci/pci_6600.c
new file mode 100644
index 00000000000..dd7f639c3bc
--- /dev/null
+++ b/sys/arch/alpha/pci/pci_6600.c
@@ -0,0 +1,372 @@
+/* $OpenBSD: pci_6600.c,v 1.1 2000/11/16 04:50:18 ericj Exp $ */
+/* $NetBSD: pci_6600.c,v 1.5 2000/06/06 00:50:15 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Ross Harvey.
+ * 4. The name of Ross Harvey may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <vm/vm.h>
+#include <uvm/uvm.h>
+
+#include <machine/autoconf.h>
+#define _ALPHA_BUS_DMA_PRIVATE
+#include <machine/bus.h>
+#include <machine/rpb.h>
+#include <machine/alpha.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pciidereg.h>
+#include <dev/pci/pciidevar.h>
+
+#include <alpha/pci/tsreg.h>
+#include <alpha/pci/tsvar.h>
+#include <alpha/pci/pci_6600.h>
+
+#define pci_6600() { Generate ctags(1) key. }
+
+#include "sio.h"
+#if NSIO
+#include <alpha/pci/siovar.h>
+#endif
+
+#define	PCI_NIRQ		64
+#define	PCI_STRAY_MAX		5
+
+/*
+ * Some Tsunami models have a PCI device (the USB controller) with interrupts
+ * tied to ISA IRQ lines.  The IRQ is encoded as:
+ *
+ *	line = 0xe0 | isa_irq;
+ */
+#define	DEC_6600_LINE_IS_ISA(line)	((line) >= 0xe0 && (line) <= 0xef)
+#define	DEC_6600_LINE_ISA_IRQ(line)	((line) & 0x0f)
+
+static char *irqtype = "6600 irq";
+static struct tsp_config *sioprimary;
+
+void dec_6600_intr_disestablish __P((void *, void *));
+void *dec_6600_intr_establish __P((
+    void *, pci_intr_handle_t, int, int (*func)(void *), void *, char *));
+const char *dec_6600_intr_string __P((void *, pci_intr_handle_t));
+const struct evcnt *dec_6600_intr_evcnt __P((void *, pci_intr_handle_t));
+int dec_6600_intr_map __P((void *, pcitag_t, int, int, pci_intr_handle_t *));
+void *dec_6600_pciide_compat_intr_establish __P((void *, struct device *,
+    struct pci_attach_args *, int, int (*)(void *), void *));
+
+struct alpha_shared_intr *dec_6600_pci_intr;
+
+void dec_6600_iointr __P((void *framep, unsigned long vec));
+extern void dec_6600_intr_enable __P((int irq));
+extern void dec_6600_intr_disable __P((int irq));
+
+void
+pci_6600_pickintr(pcp)
+	struct tsp_config *pcp;
+{
+	bus_space_tag_t iot = pcp->pc_iot;
+	pci_chipset_tag_t pc = &pcp->pc_pc;
+#if 0
+	char *cp;
+#endif
+	int i;
+
+        pc->pc_intr_v = pcp;
+        pc->pc_intr_map = dec_6600_intr_map;
+        pc->pc_intr_string = dec_6600_intr_string;
+#if 0
+	pc->pc_intr_evcnt = dec_6600_intr_evcnt;
+#endif
+        pc->pc_intr_establish = dec_6600_intr_establish;
+        pc->pc_intr_disestablish = dec_6600_intr_disestablish;
+	pc->pc_pciide_compat_intr_establish = NULL;
+
+	/*
+	 * System-wide and Pchip-0-only logic...
+	 */
+	if (dec_6600_pci_intr == NULL) {
+		sioprimary = pcp;
+		pc->pc_pciide_compat_intr_establish =
+		    dec_6600_pciide_compat_intr_establish;
+		dec_6600_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ);
+		for (i = 0; i < PCI_NIRQ; i++) {
+			alpha_shared_intr_set_maxstrays(dec_6600_pci_intr, i,
+			    PCI_STRAY_MAX);
+			alpha_shared_intr_set_private(dec_6600_pci_intr, i,
+			    sioprimary);
+
+#if 0
+			cp = alpha_shared_intr_string(dec_6600_pci_intr);
+			sprintf(cp, "irq %d", i);
+			evcnt_attach_dynamic(alpha_shared_intr_evcnt(
+			    dec_6600_pci_intr, 1), EVCNT_TYPE_INTR, NULL,
+			    "dec_6600", cp);
+#endif
+		}
+#if NSIO
+		sio_intr_setup(pc, iot);
+		dec_6600_intr_enable(55);	/* irq line for sio */
+#endif
+		set_iointr(dec_6600_iointr);
+	}
+}
+
+int     
+dec_6600_intr_map(acv, bustag, buspin, line, ihp)
+        void *acv;
+        pcitag_t bustag; 
+        int buspin, line;
+        pci_intr_handle_t *ihp;
+{
+	struct tsp_config *pcp = acv;
+	pci_chipset_tag_t pc = &pcp->pc_pc;
+	int bus, device, function;
+
+	if (buspin == 0) {
+		/* No IRQ used. */
+		return 1;
+	}
+	if (buspin > 4) {
+		printf("intr_map: bad interrupt pin %d\n", buspin);
+		return 1;
+	}
+
+	alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function);
+
+	/*
+	 * The console places the interrupt mapping in the "line" value.
+	 * A value of (char)-1 indicates there is no mapping.
+	 */
+	if (line == 0xff) {
+		printf("dec_6600_intr_map: no mapping for %d/%d/%d\n",
+		    bus, device, function);
+		return (1);
+	}
+
+#if NSIO == 0
+	if (DEC_6600_LINE_IS_ISA(line)) {
+		printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n",
+		    DEC_6600_LINE_ISA_IRQ(line), bus, device, function);
+		return (1);
+	}
+#endif
+
+	if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= PCI_NIRQ)
+		panic("dec_6600_intr_map: dec 6600 irq too large (%d)\n",
+		    line);
+
+	*ihp = line;
+	return (0);
+}
+
+const char *
+dec_6600_intr_string(acv, ih)
+	void *acv;
+	pci_intr_handle_t ih;
+{
+
+	static const char irqfmt[] = "dec 6600 irq %ld";
+	static char irqstr[sizeof irqfmt];
+
+#if NSIO
+	if (DEC_6600_LINE_IS_ISA(ih))
+		return (sio_intr_string(NULL /*XXX*/,
+		    DEC_6600_LINE_ISA_IRQ(ih)));
+#endif
+
+	snprintf(irqstr, sizeof irqstr, irqfmt, ih);
+	return (irqstr);
+}
+
+#if 0
+const struct evcnt *
+dec_6600_intr_evcnt(acv, ih)
+	void *acv;
+	pci_intr_handle_t ih;
+{
+
+#if NSIO
+	if (DEC_6600_LINE_IS_ISA(ih))
+		return (sio_intr_evcnt(NULL /*XXX*/,
+		    DEC_6600_LINE_ISA_IRQ(ih)));
+#endif
+
+	return (alpha_shared_intr_evcnt(dec_6600_pci_intr, ih));
+}
+#endif
+
+void *
+dec_6600_intr_establish(acv, ih, level, func, arg, name)
+        void *acv, *arg;
+        pci_intr_handle_t ih;
+        int level;
+        int (*func) __P((void *));
+	char *name;
+{
+	void *cookie;
+
+#if NSIO
+	if (DEC_6600_LINE_IS_ISA(ih))
+		return (sio_intr_establish(NULL /*XXX*/,
+		    DEC_6600_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg,
+	            name));
+#endif
+
+	if (ih >= PCI_NIRQ)
+		panic("dec_6600_intr_establish: bogus dec 6600 IRQ 0x%lx\n",
+		    ih);
+
+	cookie = alpha_shared_intr_establish(dec_6600_pci_intr, ih, IST_LEVEL,
+	    level, func, arg, name);
+
+	if (cookie != NULL && alpha_shared_intr_isactive(dec_6600_pci_intr, ih))
+		dec_6600_intr_enable(ih);
+	return (cookie);
+}
+
+void
+dec_6600_intr_disestablish(acv, cookie)
+        void *acv, *cookie;
+{
+	struct alpha_shared_intrhand *ih = cookie;
+	unsigned int irq = ih->ih_num;
+	int s;
+
+#if NSIO
+	/*
+	 * We have to determine if this is an ISA IRQ or not!  We do this
+	 * by checking to see if the intrhand points back to an intrhead
+	 * that points to the sioprimary TSP.  If not, it's an ISA IRQ.
+	 * Pretty disgusting, eh?
+	 */
+	if (ih->ih_intrhead->intr_private != sioprimary) {
+		sio_intr_disestablish(NULL /*XXX*/, cookie);
+		return;
+	}
+#endif
+ 
+	s = splhigh();
+
+	alpha_shared_intr_disestablish(dec_6600_pci_intr, cookie, irqtype);
+	if (alpha_shared_intr_isactive(dec_6600_pci_intr, irq) == 0) {
+		dec_6600_intr_disable(irq);
+		alpha_shared_intr_set_dfltsharetype(dec_6600_pci_intr, irq,
+		    IST_NONE);
+	}
+ 
+	splx(s);
+}
+
+void
+dec_6600_iointr(framep, vec)
+	void *framep;
+	unsigned long vec;
+{
+	int irq; 
+
+	if (vec >= 0x900) {
+		irq = (vec - 0x900) >> 4;
+
+		if (irq >= PCI_NIRQ)
+			panic("iointr: irq %d is too high", irq);
+
+		if (!alpha_shared_intr_dispatch(dec_6600_pci_intr, irq)) {
+			alpha_shared_intr_stray(dec_6600_pci_intr, irq,
+			    irqtype);
+			if (ALPHA_SHARED_INTR_DISABLE(dec_6600_pci_intr, irq))
+				dec_6600_intr_disable(irq);
+		}
+		return;
+	}
+#if NSIO
+	if (vec >= 0x800) {
+		sio_iointr(framep, vec);
+		return;
+	}
+#endif
+	panic("iointr: weird vec 0x%lx\n", vec);
+}
+
+void
+dec_6600_intr_enable(irq)
+	int irq;
+{
+	alpha_mb();
+	STQP(TS_C_DIM0) |= 1UL << irq;
+	alpha_mb();
+}
+
+void
+dec_6600_intr_disable(irq)
+	int irq;
+{
+	alpha_mb();
+	STQP(TS_C_DIM0) &= ~(1UL << irq);
+	alpha_mb();
+}
+
+void *
+dec_6600_pciide_compat_intr_establish(v, dev, pa, chan, func, arg)
+	void *v;
+	struct device *dev;
+	struct pci_attach_args *pa;
+	int chan;
+	int (*func) __P((void *));
+	void *arg;
+{
+	pci_chipset_tag_t pc = pa->pa_pc;
+	void *cookie = NULL;
+	int bus, irq;
+
+	alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
+
+	/*
+	 * If this isn't PCI bus #0 on the TSP that holds the PCI-ISA
+	 * bridge, all bets are off.
+	 */
+	if (bus != 0 || pc->pc_intr_v != sioprimary)
+		return (NULL);
+
+	irq = PCIIDE_COMPAT_IRQ(chan);
+#if NSIO
+	cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO,
+	    func, arg, "dec 6600 irq");
+
+	if (cookie == NULL)
+		return (NULL);
+#endif
+	return (cookie);
+}
diff --git a/sys/arch/alpha/pci/pci_6600.h b/sys/arch/alpha/pci/pci_6600.h
new file mode 100644
index 00000000000..756ba27accd
--- /dev/null
+++ b/sys/arch/alpha/pci/pci_6600.h
@@ -0,0 +1,6 @@
+/* $OpenBSD: pci_6600.h,v 1.1 2000/11/16 04:50:18 ericj Exp $ */
+/* $NetBSD$ */
+
+/* Public Domain */
+
+void pci_6600_pickintr __P((struct tsp_config *));
diff --git a/sys/arch/alpha/pci/tsc.c b/sys/arch/alpha/pci/tsc.c
new file mode 100644
index 00000000000..322eb2dc4ee
--- /dev/null
+++ b/sys/arch/alpha/pci/tsc.c
@@ -0,0 +1,268 @@
+/* $OpenBSD: tsc.c,v 1.1 2000/11/16 04:50:18 ericj Exp $ */
+/* $NetBSD: tsc.c,v 1.3 2000/06/25 19:17:40 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Ross Harvey.
+ * 4. The name of Ross Harvey may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <machine/autoconf.h>
+#include <machine/rpb.h>
+
+#include <dev/isa/isareg.h>
+#include <dev/isa/isavar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <alpha/pci/tsreg.h>
+#include <alpha/pci/tsvar.h>
+
+#ifdef DEC_6600
+#include <alpha/pci/pci_6600.h>
+#endif
+
+#define tsc() { Generate ctags(1) key. }
+
+int	tscmatch __P((struct device *, void *, void *));
+void	tscattach __P((struct device *, struct device *, void *));
+
+struct cfattach tsc_ca = {
+	sizeof(struct tsc_softc), tscmatch, tscattach,
+};
+
+struct cfdriver tsc_cd = {
+        NULL, "tsc", DV_DULL,
+};
+
+struct tsp_config tsp_configuration[2];
+
+static int tscprint __P((void *, const char *pnp));
+
+int	tspmatch __P((struct device *, void *, void *));
+void	tspattach __P((struct device *, struct device *, void *));
+
+struct cfattach tsp_ca = {
+	sizeof(struct tsp_softc), tspmatch, tspattach,
+};
+
+struct cfdriver tsp_cd = {
+        NULL, "tsp", DV_DULL,
+};
+
+
+static int tspprint __P((void *, const char *pnp));
+
+/* There can be only one */
+static int tscfound;
+
+/* Which hose is the display console connected to? */
+int tsp_console_hose;
+
+int
+tscmatch(parent, match, aux)
+	struct device *parent;
+	void *match;
+	void *aux;
+{
+	struct mainbus_attach_args *ma = aux;
+
+	return cputype == ST_DEC_6600
+	    && strcmp(ma->ma_name, tsc_cd.cd_name) == 0
+	    && !tscfound;
+}
+
+void tscattach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	int i;
+	int nbus;
+	u_int64_t csc, aar;
+	struct tsp_attach_args tsp;
+	struct mainbus_attach_args *ma = aux;
+
+	tscfound = 1;
+
+	csc = LDQP(TS_C_CSC);
+
+	nbus = 1 + (CSC_BC(csc) >= 2);
+	printf(": 21272 Core Logic Chipset, Cchip rev %d\n"
+		"%s%d: %c Dchips, %d memory bus%s of %d bytes\n",
+		(int)MISC_REV(LDQP(TS_C_MISC)),
+		ma->ma_name, ma->ma_slot, "2448"[CSC_BC(csc)],
+		nbus, nbus > 1 ? "es" : "", 16 + 16 * ((csc & CSC_AW) != 0));
+	printf("%s%d: arrays present: ", ma->ma_name, ma->ma_slot);
+	for(i = 0; i < 4; ++i) {
+		aar = LDQP(TS_C_AAR0 + i * TS_STEP);
+		printf("%s%dMB%s", i ? ", " : "", (8 << AAR_ASIZ(aar)) & ~0xf,
+		    aar & AAR_SPLIT ? " (split)" : "");
+	}
+	printf(", Dchip 0 rev %d\n", (int)LDQP(TS_D_DREV) & 0xf);
+
+	bzero(&tsp, sizeof tsp);
+	tsp.tsp_name = "tsp";
+	config_found(self, &tsp, NULL);
+
+	if(LDQP(TS_C_CSC) & CSC_P1P) {
+		++tsp.tsp_slot;
+		config_found(self, &tsp, tscprint);
+	}
+}
+
+static int
+tscprint(aux, p)
+	void *aux;
+	const char *p;
+{
+	register struct tsp_attach_args *tsp = aux;
+
+	if(p)
+		printf("%s%d at %s", tsp->tsp_name, tsp->tsp_slot, p);
+	return UNCONF;
+}
+
+#define tsp() { Generate ctags(1) key. }
+
+int
+tspmatch(parent, match, aux)
+	struct device *parent;
+	void *match;
+	void *aux;
+{
+	struct tsp_attach_args *t = aux;
+
+	return  cputype == ST_DEC_6600
+	    && strcmp(t->tsp_name, tsp_cd.cd_name) == 0;
+}
+
+void
+tspattach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct pcibus_attach_args pba;
+	struct tsp_attach_args *t = aux;
+	struct tsp_config *pcp;
+
+	printf("\n");
+	pcp = tsp_init(1, t->tsp_slot);
+	tsp_dma_init(pcp);
+	pci_6600_pickintr(pcp);
+	pba.pba_busname = "pci";
+	pba.pba_iot = pcp->pc_iot;
+	pba.pba_memt = pcp->pc_memt;
+	pba.pba_dmat =
+	    alphabus_dma_get_tag(&pcp->pc_dmat_direct, ALPHA_BUS_PCI);
+	pba.pba_pc = &pcp->pc_pc;
+	pba.pba_bus = 0;
+#if 0
+	pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
+	    PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
+#endif
+	config_found(self, &pba, tspprint);
+}
+
+struct tsp_config *
+tsp_init(mallocsafe, n)
+	int mallocsafe;
+	int n;	/* Pchip number */
+{
+	struct tsp_config *pcp;
+
+	KASSERT((n | 1) == 1);
+	pcp = &tsp_configuration[n];
+	pcp->pc_pslot = n;
+	pcp->pc_iobase = TS_Pn(n, 0);
+	pcp->pc_csr = S_PAGE(TS_Pn(n, P_CSRBASE));
+	if (!pcp->pc_initted) {
+		pcp->pc_iot = tsp_bus_io_init(pcp);
+		pcp->pc_memt = tsp_bus_mem_init(pcp);
+#if 0
+		alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1;
+		alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1;
+
+		alpha_bus_get_window = tsp_bus_get_window;
+#endif 
+	}
+	pcp->pc_mallocsafe = mallocsafe;
+	tsp_pci_init(&pcp->pc_pc, pcp);
+	pcp->pc_initted = 1;
+	return pcp;
+}
+
+static int
+tspprint(aux, p)
+	void *aux;
+	const char *p;
+{
+	register struct pcibus_attach_args *pci = aux;
+
+	if(p)
+		printf("%s at %s", pci->pba_busname, p);
+	printf(" bus %d", pci->pba_bus);
+	return UNCONF;
+}
+
+#if 0
+static int
+tsp_bus_get_window(type, window, abst)
+	int type, window;
+	struct alpha_bus_space_translation *abst;
+{
+	struct tsp_config *tsp = &tsp_configuration[tsp_console_hose];
+	bus_space_tag_t st;
+	int error;
+
+	switch (type) {
+	case ALPHA_BUS_TYPE_PCI_IO:
+		st = &tsp->pc_iot;
+		break;
+
+	case ALPHA_BUS_TYPE_PCI_MEM:
+		st = &tsp->pc_memt;
+		break;
+
+	default:
+		panic("tsp_bus_get_window");
+	}
+
+	error = alpha_bus_space_get_window(st, window, abst);
+	if (error)
+		return (error);
+
+	abst->abst_sys_start = TS_PHYSADDR(abst->abst_sys_start);
+	abst->abst_sys_end = TS_PHYSADDR(abst->abst_sys_end);
+
+	return (0);
+}
+#endif
diff --git a/sys/arch/alpha/pci/tsp_bus_io.c b/sys/arch/alpha/pci/tsp_bus_io.c
new file mode 100644
index 00000000000..56c4b9dd0eb
--- /dev/null
+++ b/sys/arch/alpha/pci/tsp_bus_io.c
@@ -0,0 +1,64 @@
+/* $OpenBSD: tsp_bus_io.c,v 1.1 2000/11/16 04:50:18 ericj Exp $ */
+/* $NetBSD: tsp_bus_io.c,v 1.4 2000/06/26 19:46:24 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Ross Harvey.
+ * 4. The name of Ross Harvey may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/syslog.h>
+#include <sys/device.h>
+
+#include <vm/vm.h>
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+#include <alpha/pci/tsreg.h>
+#include <alpha/pci/tsvar.h>
+
+#define	CHIP	tsp
+
+typedef struct tsp_config *TSPCON;
+
+#define	CHIP_EX_MALLOC_SAFE(v)  (((TSPCON)(v))->pc_mallocsafe)
+#define CHIP_IO_EXTENT(v)       (((TSPCON)(v))->pc_io_ex)
+
+#define CHIP_IO_SYS_START(v)    (((TSPCON)(v))->pc_iobase | P_PCI_IO)
+
+/*
+ * Tsunami core logic appears on EV6.  We require at least EV56
+ * support for the assembler to emit BWX opcodes.
+ */
+__asm(".arch ev6");
+
+#include <alpha/pci/pci_bwx_bus_io_chipdep.c>
diff --git a/sys/arch/alpha/pci/tsp_bus_mem.c b/sys/arch/alpha/pci/tsp_bus_mem.c
new file mode 100644
index 00000000000..20624843add
--- /dev/null
+++ b/sys/arch/alpha/pci/tsp_bus_mem.c
@@ -0,0 +1,66 @@
+/* $OpenBSD: tsp_bus_mem.c,v 1.1 2000/11/16 04:50:18 ericj Exp $ */
+/* $NetBSD: tsp_bus_mem.c,v 1.4 2000/06/26 19:46:25 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Ross Harvey.
+ * 4. The name of Ross Harvey may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/syslog.h>
+#include <sys/device.h>
+
+#include <vm/vm.h>
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/autoconf.h>
+#include <machine/rpb.h>
+
+#include <alpha/pci/tsreg.h>
+#include <alpha/pci/tsvar.h>
+
+#define tsp_bus_mem() { Generate ctags(1) key. }
+
+#define	CHIP	tsp
+
+#define	CHIP_EX_MALLOC_SAFE(v)  (((struct tsp_config *)(v))->pc_mallocsafe)
+#define CHIP_MEM_EXTENT(v)       (((struct tsp_config *)(v))->pc_mem_ex)
+
+#define CHIP_MEM_SYS_START(v)    (((struct tsp_config *)(v))->pc_iobase)
+
+/* 
+ * Tsunami core logic appears on EV6.  We require at least EV56          
+ * support for the assembler to emit BWX opcodes.
+ */                                                                      
+__asm(".arch ev6");                                                      
+
+#include <alpha/pci/pci_bwx_bus_mem_chipdep.c>
diff --git a/sys/arch/alpha/pci/tsp_dma.c b/sys/arch/alpha/pci/tsp_dma.c
new file mode 100644
index 00000000000..21cbbaf4d7f
--- /dev/null
+++ b/sys/arch/alpha/pci/tsp_dma.c
@@ -0,0 +1,442 @@
+/* $OpenBSD: tsp_dma.c,v 1.1 2000/11/16 04:50:18 ericj Exp $ */
+/* $NetBSD: tsp_dma.c,v 1.1 1999/06/29 06:46:47 ross Exp $ */
+
+/*-
+ * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Ross Harvey.
+ * 4. The name of Ross Harvey may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+/*-
+ * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define _ALPHA_BUS_DMA_PRIVATE
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <vm/vm.h>
+#include <uvm/uvm_extern.h>
+
+#include <machine/autoconf.h>
+
+#include <machine/bus.h>
+#include <machine/rpb.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <alpha/pci/tsreg.h>
+#include <alpha/pci/tsvar.h>
+
+#define tsp_dma() { Generate ctags(1) key. }
+
+#define	EDIFF(a, b) (((a) | WSBA_ENA | WSBA_SG)	!= ((b) | WSBA_ENA | WSBA_SG))
+
+bus_dma_tag_t tsp_dma_get_tag __P((bus_dma_tag_t, alpha_bus_t));
+
+int	tsp_bus_dmamap_create_sgmap __P((bus_dma_tag_t, bus_size_t, int,
+	    bus_size_t, bus_size_t, int, bus_dmamap_t *));
+
+void	tsp_bus_dmamap_destroy_sgmap __P((bus_dma_tag_t, bus_dmamap_t));
+
+int	tsp_bus_dmamap_load_sgmap __P((bus_dma_tag_t, bus_dmamap_t, void *,
+	    bus_size_t, struct proc *, int));
+
+int	tsp_bus_dmamap_load_mbuf_sgmap __P((bus_dma_tag_t, bus_dmamap_t,
+	    struct mbuf *, int));
+
+int	tsp_bus_dmamap_load_uio_sgmap __P((bus_dma_tag_t, bus_dmamap_t,
+	    struct uio *, int));
+
+int	tsp_bus_dmamap_load_raw_sgmap __P((bus_dma_tag_t, bus_dmamap_t,
+	    bus_dma_segment_t *, int, bus_size_t, int));
+
+void	tsp_bus_dmamap_unload_sgmap __P((bus_dma_tag_t, bus_dmamap_t));
+
+void	tsp_tlb_invalidate __P((struct tsp_config *));
+
+void
+tsp_dma_init(pcp)
+	struct tsp_config *pcp;
+{
+	int i;
+	bus_dma_tag_t t;
+	struct ts_pchip *pccsr = pcp->pc_csr;
+	bus_addr_t dwbase, dwlen, sgwbase, sgwlen, tbase;
+	static struct map_expected {
+		u_int32_t base, mask, enables;
+	} premap[4] = {
+		{ 0x800000, 		   0x700000, WSBA_ENA | WSBA_SG },
+		{ 0x80000000 | WSBA_ENA, 0x3ff00000, WSBA_ENA           },
+		{ 0, 0 },
+		{ 0, 0 }
+	};
+
+	alpha_mb();
+	for(i = 0; i < 4; ++i) {
+		if (EDIFF(pccsr->tsp_wsba[i].tsg_r, premap[i].base) ||
+		    EDIFF(pccsr->tsp_wsm[i].tsg_r, premap[i].mask))
+			printf("tsp%d: window %d: %lx/base %lx/mask %lx"
+			    " reinitialized\n",
+			    pcp->pc_pslot, i,
+			    pccsr->tsp_wsba[i].tsg_r,
+			    pccsr->tsp_wsm[i].tsg_r,
+			    pccsr->tsp_tba[i].tsg_r);
+		pccsr->tsp_wsba[i].tsg_r = premap[i].base | premap[i].enables;
+		pccsr->tsp_wsm[i].tsg_r = premap[i].mask;
+	}
+	alpha_mb();
+
+	/*
+	 * Initialize the DMA tag used for direct-mapped DMA.
+	 */
+	t = &pcp->pc_dmat_direct;
+	t->_cookie = pcp;
+	t->_wbase = dwbase = WSBA_ADDR(pccsr->tsp_wsba[1].tsg_r);
+	t->_wsize = dwlen = WSM_LEN(pccsr->tsp_wsm[1].tsg_r);
+	t->_next_window = &pcp->pc_dmat_sgmap;
+	t->_boundary = 0;
+	t->_sgmap = NULL;
+	t->_get_tag = tsp_dma_get_tag;
+	t->_dmamap_create = _bus_dmamap_create;
+	t->_dmamap_destroy = _bus_dmamap_destroy;
+	t->_dmamap_load = _bus_dmamap_load_direct;
+	t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct;
+	t->_dmamap_load_uio = _bus_dmamap_load_uio_direct;
+	t->_dmamap_load_raw = _bus_dmamap_load_raw_direct;
+	t->_dmamap_unload = _bus_dmamap_unload;
+	t->_dmamap_sync = _bus_dmamap_sync;
+
+	t->_dmamem_alloc = _bus_dmamem_alloc;
+	t->_dmamem_free = _bus_dmamem_free;
+	t->_dmamem_map = _bus_dmamem_map;
+	t->_dmamem_unmap = _bus_dmamem_unmap;
+	t->_dmamem_mmap = _bus_dmamem_mmap;
+
+	/*
+	 * Initialize the DMA tag used for sgmap-mapped DMA.
+	 */
+	t = &pcp->pc_dmat_sgmap;
+	t->_cookie = pcp;
+	t->_wbase = sgwbase = WSBA_ADDR(pccsr->tsp_wsba[0].tsg_r);
+	t->_wsize = sgwlen = WSM_LEN(pccsr->tsp_wsm[0].tsg_r);
+	t->_next_window = NULL;
+	t->_boundary = 0;
+	t->_sgmap = &pcp->pc_sgmap;
+	t->_get_tag = tsp_dma_get_tag;
+	t->_dmamap_create = tsp_bus_dmamap_create_sgmap;
+	t->_dmamap_destroy = tsp_bus_dmamap_destroy_sgmap;
+	t->_dmamap_load = tsp_bus_dmamap_load_sgmap;
+	t->_dmamap_load_mbuf = tsp_bus_dmamap_load_mbuf_sgmap;
+	t->_dmamap_load_uio = tsp_bus_dmamap_load_uio_sgmap;
+	t->_dmamap_load_raw = tsp_bus_dmamap_load_raw_sgmap;
+	t->_dmamap_unload = tsp_bus_dmamap_unload_sgmap;
+	t->_dmamap_sync = _bus_dmamap_sync;
+
+	t->_dmamem_alloc = _bus_dmamem_alloc;
+	t->_dmamem_free = _bus_dmamem_free;
+	t->_dmamem_map = _bus_dmamem_map;
+	t->_dmamem_unmap = _bus_dmamem_unmap;
+	t->_dmamem_mmap = _bus_dmamem_mmap;
+
+	/*
+	 * Initialize the SGMAP.  Align page table to 32k in case
+	 * window is somewhat larger than expected.
+	 */
+	alpha_sgmap_init(t, &pcp->pc_sgmap, "tsp_sgmap",
+	    sgwbase, 0, sgwlen, sizeof(u_int64_t), NULL, (32*1024));
+
+	/*
+	 * Enable window 0 and enable SG PTE mapping.
+	 */
+	alpha_mb();
+	pccsr->tsp_wsba[0].tsg_r |= WSBA_SG | WSBA_ENA;
+	alpha_mb();
+
+	/*
+	 * Check windows for sanity, especially if we later decide to
+	 * use the firmware's initialization in some cases.
+	 */
+	if ((sgwbase <= dwbase && dwbase < sgwbase + sgwlen) ||
+	    (dwbase <= sgwbase && sgwbase < dwbase + dwlen))
+		panic("tsp_dma_init: overlap");
+
+	tbase = pcp->pc_sgmap.aps_ptpa;
+	if (tbase & ~0x7fffffc00UL)
+		panic("tsp_dma_init: bad page table address");
+	alpha_mb();
+	pccsr->tsp_tba[0].tsg_r = tbase;
+	alpha_mb();
+
+	tsp_tlb_invalidate(pcp);
+	alpha_mb();
+
+	/* XXX XXX BEGIN XXX XXX */
+	{							/* XXX */
+		extern paddr_t alpha_XXX_dmamap_or;		/* XXX */
+		alpha_XXX_dmamap_or = dwbase;			/* XXX */
+	}							/* XXX */
+	/* XXX XXX END XXX XXX */
+}
+
+/*
+ * Return the bus dma tag to be used for the specified bus type.
+ * INTERNAL USE ONLY!
+ */
+bus_dma_tag_t
+tsp_dma_get_tag(t, bustype)
+	bus_dma_tag_t t;
+	alpha_bus_t bustype;
+{
+	struct tsp_config *pcp = t->_cookie;
+
+	switch (bustype) {
+	case ALPHA_BUS_PCI:
+	case ALPHA_BUS_EISA:
+		/*
+		 * The direct mapped window will work for most systems,
+		 * most of the time. When it doesn't, we chain to the sgmap
+		 * window automatically.
+		 */
+		return (&pcp->pc_dmat_direct);
+
+	case ALPHA_BUS_ISA:
+		/*
+		 * ISA doesn't have enough address bits to use
+		 * the direct-mapped DMA window, so we must use
+		 * SGMAPs.
+		 */
+		return (&pcp->pc_dmat_sgmap);
+
+	default:
+		panic("tsp_dma_get_tag: shouldn't be here, really...");
+	}
+}
+
+/*
+ * Create a TSP SGMAP-mapped DMA map.
+ */
+int
+tsp_bus_dmamap_create_sgmap(t, size, nsegments, maxsegsz, boundary,
+    flags, dmamp)
+	bus_dma_tag_t t;
+	bus_size_t size;  
+	int nsegments;
+	bus_size_t maxsegsz;
+	bus_size_t boundary;
+	int flags; 
+	bus_dmamap_t *dmamp;
+{
+	bus_dmamap_t map;
+	int error;
+
+	error = _bus_dmamap_create(t, size, nsegments, maxsegsz,
+	    boundary, flags, dmamp);
+	if (error)
+		return (error);
+
+	map = *dmamp;
+
+	if (flags & BUS_DMA_ALLOCNOW) {
+		error = alpha_sgmap_alloc(map, round_page(size),
+		    t->_sgmap, flags);
+		if (error)
+			tsp_bus_dmamap_destroy_sgmap(t, map);
+	}
+
+	return (error);
+}
+
+/*
+ * Destroy a TSP SGMAP-mapped DMA map.
+ */
+void
+tsp_bus_dmamap_destroy_sgmap(t, map)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+{
+
+	if (map->_dm_flags & DMAMAP_HAS_SGMAP)
+		alpha_sgmap_free(map, t->_sgmap);
+
+	_bus_dmamap_destroy(t, map);
+}
+
+/*
+ * Load a TSP SGMAP-mapped DMA map with a linear buffer.
+ */
+int
+tsp_bus_dmamap_load_sgmap(t, map, buf, buflen, p, flags)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+	void *buf;
+	bus_size_t buflen;
+	struct proc *p;
+	int flags;
+{
+	int error;
+
+	error = pci_sgmap_pte64_load(t, map, buf, buflen, p, flags,
+	    t->_sgmap);
+	if (error == 0)
+		tsp_tlb_invalidate(t->_cookie);
+
+	return (error);
+}
+
+/*
+ * Load a TSP SGMAP-mapped DMA map with an mbuf chain.
+ */
+int
+tsp_bus_dmamap_load_mbuf_sgmap(t, map, m, flags)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+	struct mbuf *m;
+	int flags;
+{
+	int error;
+
+	error = pci_sgmap_pte64_load_mbuf(t, map, m, flags, t->_sgmap);
+	if (error == 0)
+		tsp_tlb_invalidate(t->_cookie);
+
+	return (error);
+}
+
+/*
+ * Load a TSP SGMAP-mapped DMA map with a uio.
+ */
+int
+tsp_bus_dmamap_load_uio_sgmap(t, map, uio, flags)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+	struct uio *uio;
+	int flags;
+{
+	int error;
+
+	error = pci_sgmap_pte64_load_uio(t, map, uio, flags, t->_sgmap);
+	if (error == 0)
+		tsp_tlb_invalidate(t->_cookie);
+
+	return (error);
+}
+
+/*
+ * Load a TSP SGMAP-mapped DMA map with raw memory.
+ */
+int
+tsp_bus_dmamap_load_raw_sgmap(t, map, segs, nsegs, size, flags)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+	bus_dma_segment_t *segs;
+	int nsegs;
+	bus_size_t size;
+	int flags;
+{
+	int error;
+
+	error = pci_sgmap_pte64_load_raw(t, map, segs, nsegs, size, flags,
+	    t->_sgmap);
+	if (error == 0)
+		tsp_tlb_invalidate(t->_cookie);
+
+	return (error);
+}
+
+/*
+ * Unload a TSP DMA map.
+ */
+void
+tsp_bus_dmamap_unload_sgmap(t, map)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+{
+
+	/*
+	 * Invalidate any SGMAP page table entries used by this
+	 * mapping.
+	 */
+	pci_sgmap_pte64_unload(t, map, t->_sgmap);
+	tsp_tlb_invalidate(t->_cookie);
+
+	/*
+	 * Do the generic bits of the unload.
+	 */
+	_bus_dmamap_unload(t, map);
+}
+
+/*
+ * Flush the TSP scatter/gather TLB.
+ */
+void
+tsp_tlb_invalidate(pcp)
+	struct tsp_config *pcp;
+{
+
+	alpha_mb();
+	pcp->pc_csr->tsp_tlbia.tsg_r = 0;
+	alpha_mb();
+}
diff --git a/sys/arch/alpha/pci/tsp_pci.c b/sys/arch/alpha/pci/tsp_pci.c
new file mode 100644
index 00000000000..7daca3130fe
--- /dev/null
+++ b/sys/arch/alpha/pci/tsp_pci.c
@@ -0,0 +1,148 @@
+/* $OpenBSD: tsp_pci.c,v 1.1 2000/11/16 04:50:18 ericj Exp $ */
+/* $NetBSD: tsp_pci.c,v 1.1 1999/06/29 06:46:47 ross Exp $ */
+
+/*-
+ * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Ross Harvey.
+ * 4. The name of Ross Harvey may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+
+#include <vm/vm.h>
+#include <uvm/uvm_extern.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <machine/autoconf.h>
+#include <machine/rpb.h>
+
+#include <alpha/pci/tsreg.h>
+#include <alpha/pci/tsvar.h>
+
+#define tsp_pci() { Generate ctags(1) key. }
+
+void		tsp_attach_hook __P((struct device *, struct device *,
+		    struct pcibus_attach_args *));
+int		tsp_bus_maxdevs __P((void *, int));
+pcitag_t	tsp_make_tag __P((void *, int, int, int));
+void		tsp_decompose_tag __P((void *, pcitag_t, int *, int *,
+		    int *));
+pcireg_t	tsp_conf_read __P((void *, pcitag_t, int));
+void		tsp_conf_write __P((void *, pcitag_t, int, pcireg_t));
+
+void
+tsp_pci_init(pc, v)
+	pci_chipset_tag_t pc;
+	void *v;
+{
+	pc->pc_conf_v = v;
+	pc->pc_attach_hook = tsp_attach_hook;
+	pc->pc_bus_maxdevs = tsp_bus_maxdevs;
+	pc->pc_make_tag = tsp_make_tag;
+	pc->pc_decompose_tag = tsp_decompose_tag;
+	pc->pc_conf_read = tsp_conf_read;
+	pc->pc_conf_write = tsp_conf_write;
+}
+
+void
+tsp_attach_hook(parent, self, pba)
+	struct device *parent, *self;
+	struct pcibus_attach_args *pba;
+{
+}
+
+int
+tsp_bus_maxdevs(cpv, busno)
+	void *cpv;
+	int busno;
+{
+	return 32;
+}
+
+pcitag_t
+tsp_make_tag(cpv, b, d, f)
+	void *cpv;
+	int b, d, f;
+{
+	return b << 16 | d << 11 | f << 8;
+}
+
+void
+tsp_decompose_tag(cpv, tag, bp, dp, fp)
+	void *cpv;
+	pcitag_t tag;
+	int *bp, *dp, *fp;
+{
+	if (bp != NULL)
+		*bp = (tag >> 16) & 0xff;
+	if (dp != NULL)
+		*dp = (tag >> 11) & 0x1f;
+	if (fp != NULL)
+		*fp = (tag >> 8) & 0x7;
+}
+/*
+ * Tsunami makes this a lot easier than it used to be, automatically
+ * generating type 0 or type 1 cycles, and quietly returning -1 with
+ * no errors on unanswered probes.
+ */
+pcireg_t
+tsp_conf_read(cpv, tag, offset)
+	void *cpv;
+	pcitag_t tag;
+	int offset;
+{
+	pcireg_t *datap, data;
+	struct tsp_config *pcp = cpv;
+
+	datap = S_PAGE(pcp->pc_iobase | P_PCI_CONFIG | tag | (offset & ~3));
+	alpha_mb();
+	data = *datap;
+	alpha_mb();
+	return data;
+}
+
+void
+tsp_conf_write(cpv, tag, offset, data)
+	void *cpv;
+	pcitag_t tag;
+	int offset;
+	pcireg_t data;
+{
+	pcireg_t *datap;
+	struct tsp_config *pcp = cpv;
+
+	datap = S_PAGE(pcp->pc_iobase | P_PCI_CONFIG | tag | (offset & ~3));
+	alpha_mb();
+	*datap = data;
+	alpha_mb();
+}
diff --git a/sys/arch/alpha/pci/tsreg.h b/sys/arch/alpha/pci/tsreg.h
new file mode 100644
index 00000000000..fa1ed0dd525
--- /dev/null
+++ b/sys/arch/alpha/pci/tsreg.h
@@ -0,0 +1,227 @@
+/* $OpenBSD: tsreg.h,v 1.1 2000/11/16 04:50:18 ericj Exp $ */
+/* $NetBSD: tsreg.h,v 1.1 1999/06/29 06:46:47 ross Exp $ */
+
+/*-
+ * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Ross Harvey.
+ * 4. The name of Ross Harvey may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+/*
+ * 21272 Core Logic registers and constants.
+ */
+
+#define	tsreg() { Generate ctags(1) key. }
+
+/*
+ * Superpage pointer from physical address.
+ */
+#define	S_PAGE(phys) ((void *)ALPHA_PHYS_TO_K0SEG(phys))
+
+/*
+ * {LD,ST}QP: LoaD and STore Quad Physical
+ */
+#define	LDQP(a)	(*(volatile long *)ALPHA_PHYS_TO_K0SEG(a))
+#define	STQP(a) LDQP(a)
+
+/*
+ * Define extraction functions for bit fields via length and left,right bitno
+ */
+#define	TSFIELD(r,offs,len) (((r) >> (offs)) & (~0UL >> (64 - (len))))
+#define	TSFIELDBB(r,lb,rb) TSFIELD((r), (rb), (lb) - (rb) + 1)
+
+/*
+ * EV6 has a new superpage which can pass through 44 address bits.  (Umm, a
+ * superduperpage?) But, the firmware doesn't turn it on, so we use the old
+ * one and let the HW sign extend va/pa<40> to get us the pa<43> that makes
+ * the needed I/O space access. This is just as well; it means we don't have
+ * to worry about which GENERIC code might get called on other CPU models.
+ *
+ *	E.g., we want this:	      0x0801##a000##0000
+ *	We use this:		      0x0101##a000##0000
+ *	...mix in the old SP:	0xffff##fc00##0000##0000
+ *	...after PA sign ext:	0xffff##ff00##a000##0000
+ *	(PA<42:41> ignored)
+ */
+
+/*
+ * This hack allows us to map the I/O address space without using
+ * the KSEG sign extention hack.
+ */
+#define	TS_PHYSADDR(x)							\
+	(((x) & ~0x0100##0000##0000) | 0x0800##0000##0000)
+
+/*
+ * Cchip CSR Map
+ */
+
+#define TS_C_CSC	0x101##a000##0000UL	/* Cchip System Configuration */
+
+#	define	CSC_P1P		(1L << 14)
+#	define	CSC_BC(r)	TSFIELD((r), 0, 2)
+#	define	CSC_AW		(1L << 8)
+
+#define TS_C_MTR	0x101##a000##0040UL
+
+#define TS_C_MISC	0x101##a000##0080UL	/* Miscellaneous Register */
+
+#	define	MISC_REV(r)	TSFIELD((r), 39, 8)
+
+#define TS_C_MPD	0x101##a000##00c0UL
+
+#define TS_C_AAR0	0x101##a000##0100UL
+#define TS_C_AAR1	0x101##a000##0140UL
+#define TS_C_AAR2	0x101##a000##0180UL
+#define TS_C_AAR3	0x101##a000##01c0UL
+
+#	define	AAR_ASIZ(r)	TSFIELD((r), 12, 4)
+#	define	AAR_SPLIT	(1L << 8)
+
+#define TS_C_DIM0	0x101##a000##0200UL
+#define TS_C_DIM1	0x101##a000##0240UL
+#define TS_C_DIR0	0x101##a000##0280UL
+#define TS_C_DIR1	0x101##a000##02c0UL
+#define TS_C_DRIR	0x101##a000##0300UL
+#define TS_C_PRBEN	0x101##a000##0340UL
+#define TS_C_IIC0	0x101##a000##0380UL
+#define TS_C_IIC1	0x101##a000##03c0UL
+#define TS_C_MPR0	0x101##a000##0400UL
+#define TS_C_MPR1	0x101##a000##0440UL
+#define TS_C_MPR2	0x101##a000##0480UL
+#define TS_C_MPR3	0x101##a000##04c0UL
+#define TS_C_MCTL	0x101##a000##0500UL
+
+#define TS_C_TTR	0x101##a000##0580UL
+#define TS_C_TDR	0x101##a000##05c0UL
+
+/*
+ * Dchip CSR Map
+ */
+
+#define TS_D_DSC	0x101##b000##0800UL
+#define TS_D_STR	0x101##b000##0840UL
+#define TS_D_DREV	0x101##b000##0880UL
+#define TS_D_DSC2	0x101##b000##08c0UL
+
+/*
+ * Pchip CSR Offsets
+ */
+
+#define P_WSBA0		0x0000
+#define P_WSBA1		0x0040
+#define P_WSBA2		0x0080
+#define P_WSBA3		0x00c0
+
+#	define	WSBA_ADDR(r) (TSFIELDBB((r), 31, 20) << 20)
+#	define	WSBA_SG	     2
+#	define	WSBA_ENA     1
+
+#define P_WSM0		0x0100
+#define P_WSM1		0x0140
+#define P_WSM2		0x0180
+#define P_WSM3		0x01c0
+
+#	define	WSM_AM(r)    TSFIELDBB((r), 31, 20)
+#	define	WSM_LEN(r)   ((WSM_AM(r) + 1) << 20)
+
+#define P_TBA0		0x0200
+#define P_TBA1		0x0240
+#define P_TBA2		0x0280
+#define P_TBA3		0x02c0
+
+#define P_PCTL		0x0300
+#define P_PLAT		0x0340
+	/* reserved	0x0380 */
+#define P_PERROR	0x03c0
+
+#define P_PERRMASK	0x0400
+#define P_PERRSET	0x0440
+#define P_TLBIV		0x0480
+#define P_TLBIA		0x04c0
+
+#define P_PMONCTL	0x0500
+#define P_PMONCNT	0x0540
+
+#define P_SPRST		0x0800
+
+#define	TS_STEP		0x40
+
+/*
+ * Pchip I/O offsets
+ */
+
+#define	P_CSRBASE	 0x001##8000##0000UL
+#define	P_PCI_MEM	 0
+#define	P_PCI_IO	 0x001##fc00##0000UL
+#define	P_PCI_CONFIG	 0x001##fe00##0000UL
+
+/*
+ * Construct EV6 I/O Space Address for Pchip 0 and Pchip 1.
+ */
+
+#define	TS_P0(offs)	(0x100##0000##0000UL + (offs))
+#define	TS_P1(offs)	(0x102##0000##0000UL + (offs))
+#define	TS_Pn(n, offs)	(0x100##0000##0000UL + 0x2##0000##0000UL * (n) + (offs))
+
+/*
+ * Tsunami Generic Register Type
+ */
+typedef struct _ts_gr {
+	volatile u_int64_t tsg_r;
+	long	tsg_deadspace[7];
+} TS_GR;
+
+/*
+ * Tsunami Pchip
+ */
+struct	ts_pchip {
+	TS_GR	tsp_wsba[4];	/* Window Space Base Address */
+
+	TS_GR	tsp_wsm[4];	/* Window Space Mask */
+
+	TS_GR	tsp_tba[4];	/* Translated Base Address */
+
+	TS_GR	tsp_pctl;	/* Pchip Control */
+	TS_GR	tsp_plat;	/* Pchip Latency */
+	TS_GR	tsp_resA;
+	TS_GR	tsp_error;	/* Pchip Error */
+
+	TS_GR	tsp_perrmask;	/* Pchip Error Mask */
+	TS_GR	tsp_perrset;	/* Pchip Error Set */
+	TS_GR	tsp_tlbiv;	/* Translation Buffer Invalidate Virtual */
+	TS_GR	tsp_tlbia;	/* Translation Buffer Invalidate All */
+
+	TS_GR	tsp_pmonctl;	/* PChip Monitor Control */
+	TS_GR	tsp_pmoncnt;	/* PChip Monitor Counters */
+	TS_GR	tsp_resB;
+	TS_GR	tsp_resC;
+
+	TS_GR	tsp_resD_K[8];
+
+	TS_GR	tsp_sprts;	/* ??? */
+};
diff --git a/sys/arch/alpha/pci/tsvar.h b/sys/arch/alpha/pci/tsvar.h
new file mode 100644
index 00000000000..bde47c4cf7b
--- /dev/null
+++ b/sys/arch/alpha/pci/tsvar.h
@@ -0,0 +1,83 @@
+/* $OpenBSD: tsvar.h,v 1.1 2000/11/16 04:50:18 ericj Exp $ */
+/* $NetBSD: tsvar.h,v 1.1 1999/06/29 06:46:47 ross Exp $ */
+
+/*-
+ * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Ross Harvey.
+ * 4. The name of Ross Harvey may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <dev/isa/isavar.h>
+#include <dev/pci/pcivar.h>
+#include <alpha/pci/pci_sgmap_pte64.h>
+
+#define	tsvar() { Generate ctags(1) key. }
+
+struct tsc_softc {
+	struct	device tsc_dev;
+};
+
+struct tsp_config {
+	int	pc_pslot;		/* Pchip 0 or 1 */
+	int	pc_initted;		/* Initialized */
+	u_int64_t pc_iobase;		/* All Pchip space starts here */
+	struct	ts_pchip *pc_csr;	/* Pchip CSR space starts here */
+
+	bus_space_tag_t pc_iot, pc_memt;
+	struct	alpha_pci_chipset pc_pc;
+
+	struct	alpha_bus_dma_tag pc_dmat_direct;
+	struct	alpha_bus_dma_tag pc_dmat_sgmap;
+
+	struct alpha_sgmap pc_sgmap;
+
+	u_int32_t pc_hae_mem;
+	u_int32_t pc_hae_io;
+
+	struct	extent *pc_io_ex, *pc_mem_ex;
+	int	pc_mallocsafe;
+};
+
+struct tsp_softc {
+	struct	device sc_dev;
+	struct	tsp_config *sc_ccp;
+};
+
+struct tsp_attach_args {
+	char	*tsp_name;
+	int	tsp_slot;
+};
+
+extern int tsp_console_hose;
+
+struct	tsp_config *tsp_init __P((int, int));
+void	tsp_pci_init __P((pci_chipset_tag_t, void *));
+void	tsp_dma_init __P((struct tsp_config *));
+
+bus_space_tag_t	tsp_bus_io_init __P((void *));
+bus_space_tag_t	tsp_bus_mem_init __P((void *));