get rid of otus_phy_write().

unobfuscate things a bit.

2 files changed, 84 insertions, 63 deletions

diff --git a/sys/dev/usb/if_otus.c b/sys/dev/usb/if_otus.c
index 4b09c3ef98b..4c39dc5d4a6 100644
--- a/sys/dev/usb/if_otus.c
+++ b/sys/dev/usb/if_otus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_otus.c,v 1.5 2009/03/26 19:54:16 damien Exp $	*/
+/*	$OpenBSD: if_otus.c,v 1.6 2009/04/02 19:03:40 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -313,12 +313,13 @@ otus_attachhook(void *xsc)
 		return;
 	}
 
+	sc->txmask = sc->eeprom.baseEepHeader.txMask;
+	sc->rxmask = sc->eeprom.baseEepHeader.rxMask;
 	IEEE80211_ADDR_COPY(ic->ic_myaddr, sc->eeprom.baseEepHeader.macAddr);
+	sc->sc_led_newstate = otus_led_newstate_type3;	/* XXX */
 
-/* XXX */
-	sc->sc_led_newstate = otus_led_newstate_type3;
-
-	printf("%s: address %s\n", sc->sc_dev.dv_xname,
+	printf("%s: MIMO %dT%dR, address %s\n", sc->sc_dev.dv_xname,
+	    (sc->txmask == 1) ? 1 : 2, (sc->rxmask == 1) ? 1 : 2,
 	    ether_sprintf(ic->ic_myaddr));
 
 	ic->ic_phytype = IEEE80211_T_OFDM;	/* not only, but not used */
@@ -905,7 +906,7 @@ otus_read_eeprom(struct otus_softc *sc)
 
 	/* Read EEPROM by blocks of 32 bytes. */
 	eep = (uint8_t *)&sc->eeprom;
-	reg = 0x1600;
+	reg = AR_EEPROM_OFFSET;
 	for (i = 0; i < sizeof (sc->eeprom) / 32; i++) {
 		for (j = 0; j < 8; j++, reg += 4)
 			regs[j] = htole32(reg);
@@ -1311,12 +1312,12 @@ otus_tx(struct otus_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
 	if (ridx >= OTUS_RIDX_OFDM6) {
 		phyctl |= AR_TX_PHY_MT_OFDM;
 		if (ridx <= OTUS_RIDX_OFDM24)
-			phyctl |= AR_TX_PHY_ANTMSK(5);
+			phyctl |= AR_TX_PHY_ANTMSK(sc->txmask);
 		else
 			phyctl |= AR_TX_PHY_ANTMSK(1);
 	} else {	/* CCK */
 		phyctl |= AR_TX_PHY_MT_CCK;
-		phyctl |= AR_TX_PHY_ANTMSK(5);
+		phyctl |= AR_TX_PHY_ANTMSK(sc->txmask);
 	}
 
 	/* Update rate control stats for frames that are ACK'ed. */
@@ -1686,12 +1687,6 @@ otus_init_mac(struct otus_softc *sc)
 	return 0;
 }
 
-static __inline void
-otus_phy_write(struct otus_softc *sc, uint32_t reg, uint32_t val)
-{
-	otus_write(sc, 0x1bc000 + reg, val);
-}
-
 /*
  * Return default value for PHY register based on current operating mode.
  */
@@ -1725,49 +1720,49 @@ otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c)
 	offset = 2 * 0x1000;
 
 	tmp = letoh32(eep->antCtrlCommon);
-	otus_phy_write(sc, AR_PHY_SWITCH_COM, tmp);
+	otus_write(sc, AR_PHY_SWITCH_COM, tmp);
 
 	tmp = letoh32(eep->antCtrlChain[0]);
-	otus_phy_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp);
+	otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp);
 
 	tmp = letoh32(eep->antCtrlChain[1]);
-	otus_phy_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp);
+	otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp);
 
 	if (1 /* sc->sc_sco == AR_SCO_SCN */) {
 		tmp = otus_phy_get_def(sc, AR_PHY_SETTLING);
 		tmp &= ~(0x7f << 7);
 		tmp |= (eep->switchSettling & 0x7f) << 7;
-		otus_phy_write(sc, AR_PHY_SETTLING, tmp);
+		otus_write(sc, AR_PHY_SETTLING, tmp);
 	}
 
 	tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ);
 	tmp &= ~0xffff;
 	tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize;
-	otus_phy_write(sc, AR_PHY_DESIRED_SZ, tmp);
+	otus_write(sc, AR_PHY_DESIRED_SZ, tmp);
 
 	tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 |
 	      eep->txFrameToXpaOn << 8 | eep->txFrameToXpaOn;
-	otus_phy_write(sc, AR_PHY_RF_CTL4, tmp);
+	otus_write(sc, AR_PHY_RF_CTL4, tmp);
 
 	tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3);
 	tmp &= ~(0xff << 16);
 	tmp |= eep->txEndToRxOn << 16;
-	otus_phy_write(sc, AR_PHY_RF_CTL3, tmp);
+	otus_write(sc, AR_PHY_RF_CTL3, tmp);
 
 	tmp = otus_phy_get_def(sc, AR_PHY_CCA);
 	tmp &= ~(0x7f << 12);
 	tmp |= (eep->thresh62 & 0x7f) << 12;
-	otus_phy_write(sc, AR_PHY_CCA, tmp);
+	otus_write(sc, AR_PHY_CCA, tmp);
 
 	tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN);
 	tmp &= ~(0x3f << 12);
 	tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12;
-	otus_phy_write(sc, AR_PHY_RXGAIN, tmp);
+	otus_write(sc, AR_PHY_RXGAIN, tmp);
 
 	tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset);
 	tmp &= ~(0x3f << 12);
 	tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12;
-	otus_phy_write(sc, AR_PHY_RXGAIN + offset, tmp);
+	otus_write(sc, AR_PHY_RXGAIN + offset, tmp);
 
 	tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ);
 	tmp &= ~(0x3f << 18);
@@ -1776,27 +1771,27 @@ otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c)
 		tmp &= ~(0xf << 10);
 		tmp |= (eep->bswMargin[0] & 0xf) << 10;
 	}
-	otus_phy_write(sc, AR_PHY_GAIN_2GHZ, tmp);
+	otus_write(sc, AR_PHY_GAIN_2GHZ, tmp);
 
 	tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset);
 	tmp &= ~(0x3f << 18);
 	tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18;
-	otus_phy_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp);
+	otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp);
 
 	tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4);
 	tmp &= ~(0x3f << 5 | 0x1f);
 	tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f);
-	otus_phy_write(sc, AR_PHY_TIMING_CTRL4, tmp);
+	otus_write(sc, AR_PHY_TIMING_CTRL4, tmp);
 
 	tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset);
 	tmp &= ~(0x3f << 5 | 0x1f);
 	tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f);
-	otus_phy_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp);
+	otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp);
 
-	tmp = otus_phy_get_def(sc, 0xa258);
+	tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1);
 	tmp &= ~(0xf << 16);
 	tmp |= (eep->xpd & 0xf) << 16;
-	otus_phy_write(sc, 0xa258, tmp);
+	otus_write(sc, AR_PHY_TPCRG1, tmp);
 
 	return otus_write_barrier(sc);
 }
@@ -1813,7 +1808,7 @@ otus_program_phy(struct otus_softc *sc, struct ieee80211_channel *c)
 	else
 		vals = ar5416_phy_vals_5ghz_20mhz;
 	for (i = 0; i < nitems(ar5416_phy_regs); i++)
-		otus_phy_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]);
+		otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]);
 	sc->phy_vals = vals;
 
 	if (sc->eeprom.baseEepHeader.deviceType == 0x80)	/* FEM */
@@ -1821,16 +1816,16 @@ otus_program_phy(struct otus_softc *sc, struct ieee80211_channel *c)
 			return error;
 
 	/* Initial Tx power settings. */
-	otus_phy_write(sc, AR_PHY( 79), 0x7f);
-	otus_phy_write(sc, AR_PHY( 77), 0x3f3f3f3f);
-	otus_phy_write(sc, AR_PHY( 78), 0x3f3f3f3f);
-	otus_phy_write(sc, AR_PHY(653), 0x3f3f3f3f);
-	otus_phy_write(sc, AR_PHY(654), 0x3f3f3f3f);
-	otus_phy_write(sc, AR_PHY(739), 0x3f3f3f3f);
-	otus_phy_write(sc, AR_PHY(740), 0x3f3f3f3f);
-	otus_phy_write(sc, AR_PHY(755), 0x3f3f3f3f);
-	otus_phy_write(sc, AR_PHY(756), 0x3f3f3f3f);
-	otus_phy_write(sc, AR_PHY(757), 0x3f3f3f3f);
+	otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f);
+	otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f);
+	otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f);
+	otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f);
+	otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f);
+	otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f);
+	otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f);
+	otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f);
+	otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f);
+	otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f);
 
 	if (IEEE80211_IS_CHAN_2GHZ(c))
 		otus_write(sc, 0x1d4014, 0x5163);
@@ -1890,7 +1885,7 @@ otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c)
 	(void)otus_write_barrier(sc);
 
 	/* Disable BB Heavy Clip. */
-	otus_phy_write(sc, 0x99e0, 0x200);
+	otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200);
 	(void)otus_write_barrier(sc);
 
 	error = otus_cmd(sc, AR_CMD_FREQ_STRAT, NULL, 0, NULL);
@@ -1918,10 +1913,8 @@ otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c)
 			vals = ar5416_banks_vals_5ghz;
 		else
 			vals = ar5416_banks_vals_2ghz;
-		for (i = 0; i < nitems(ar5416_banks_regs); i++) {
-			otus_phy_write(sc, AR_PHY(ar5416_banks_regs[i]),
-			    vals[i]);
-		}
+		for (i = 0; i < nitems(ar5416_banks_regs); i++)
+			otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]);
 		if ((error = otus_write_barrier(sc)) != 0)
 			return error;
 
@@ -1951,16 +1944,17 @@ otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c)
 
 	/* Write bits 0-4 of d0 and d1. */
 	data = (d1 & 0x1f) << 5 | (d0 & 0x1f);
-	otus_phy_write(sc, AR_PHY(44), data);
+	otus_write(sc, AR_PHY(44), data);
 	/* Write bits 5-7 of d0 and d1. */
 	data = (d1 >> 5) << 5 | (d0 >> 5);
-	otus_phy_write(sc, AR_PHY(58), data);
+	otus_write(sc, AR_PHY(58), data);
 
 	if ((error = otus_write_barrier(sc)) != 0)
 		return error;
 	usbd_delay_ms(sc->sc_udev, 10);
 
-	otus_phy_write(sc, AR_PHY(1), 0x100 | 0x240);	/* XXX UB83 */
+	tmp = (sc->txmask == 0x5) ? 0x340 : 0x240;
+	otus_write(sc, AR_PHY_TURBO, tmp);
 	(void)otus_write_barrier(sc);
 
 	/* Send firmware command to set channel. */
diff --git a/sys/dev/usb/if_otusreg.h b/sys/dev/usb/if_otusreg.h
index 08de2249bcd..26f9074fee5 100644
--- a/sys/dev/usb/if_otusreg.h
+++ b/sys/dev/usb/if_otusreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_otusreg.h,v 1.4 2009/03/26 19:54:16 damien Exp $	*/
+/*	$OpenBSD: if_otusreg.h,v 1.5 2009/04/02 19:03:40 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -52,6 +52,8 @@
 #define AR_MAC_REG_SNIFFER		(AR_MAC_REG_BASE + 0x674)
 #define AR_MAC_REG_ACK_EXTENSION	(AR_MAC_REG_BASE + 0x690)
 #define AR_MAC_REG_EIFS_AND_SIFS	(AR_MAC_REG_BASE + 0x698)
+#define AR_MAC_REG_BUSY			(AR_MAC_REG_BASE + 0x6e8)
+#define AR_MAC_REG_BUSY_EXT		(AR_MAC_REG_BASE + 0x6ec)
 #define AR_MAC_REG_SLOT_TIME		(AR_MAC_REG_BASE + 0x6f0)
 #define AR_MAC_REG_AC0_CW		(AR_MAC_REG_BASE + 0xb00)
 #define AR_MAC_REG_AC1_CW		(AR_MAC_REG_BASE + 0xb04)
@@ -65,6 +67,8 @@
 					(AR_MAC_REG_BASE + 0xb30)
 #define AR_MAC_REG_AC1_AC0_TXOP		(AR_MAC_REG_BASE + 0xb44)
 #define AR_MAC_REG_AC3_AC2_TXOP		(AR_MAC_REG_BASE + 0xb48)
+#define AR_MAC_REG_OFDM_PHY_ERRORS	(AR_MAC_REG_BASE + 0xcb4)
+#define AR_MAC_REG_CCK_PHY_ERRORS	(AR_MAC_REG_BASE + 0xcb8)
 #define AR_MAC_REG_BCN_HT1		(AR_MAC_REG_BASE + 0xda0)
 
 /* Possible values for register AR_USB_MODE_CTRL. */
@@ -83,19 +87,40 @@
 /*
  * PHY registers.
  */
-#define AR_PHY(reg)		(0x9800 + (reg) * 4)
-#define AR_PHY_SWITCH_COM	0x9964
-#define AR_PHY_SWITCH_CHAIN_0	0x9960
-#define AR_PHY_SETTLING		0x9844
-#define AR_PHY_DESIRED_SZ	0x9850
-#define AR_PHY_RF_CTL4		0x9834
-#define AR_PHY_RF_CTL3		0x9828
-#define AR_PHY_RXGAIN		0x9848
-#define AR_PHY_TIMING_CTRL4	0x9920
-#define AR_PHY_GAIN_2GHZ	0xa20c
-#define AR_PHY_CCA		0xc864
+#define AR_PHY_BASE			0x1c5800
+#define AR_PHY(reg)			(AR_PHY_BASE + (reg) * 4)
+#define AR_PHY_TURBO			(AR_PHY_BASE + 0x0004)
+#define AR_PHY_RF_CTL3			(AR_PHY_BASE + 0x0028)
+#define AR_PHY_RF_CTL4			(AR_PHY_BASE + 0x0034)
+#define AR_PHY_SETTLING			(AR_PHY_BASE + 0x0044)
+#define AR_PHY_RXGAIN			(AR_PHY_BASE + 0x0048)
+#define AR_PHY_DESIRED_SZ		(AR_PHY_BASE + 0x0050)
+#define AR_PHY_FIND_SIG			(AR_PHY_BASE + 0x0058)
+#define AR_PHY_AGC_CTL1			(AR_PHY_BASE + 0x005c)
+#define AR_PHY_SFCORR			(AR_PHY_BASE + 0x0068)
+#define AR_PHY_SFCORR_LOW		(AR_PHY_BASE + 0x006c)
+#define AR_PHY_TIMING_CTRL4		(AR_PHY_BASE + 0x0120)
+#define AR_PHY_TIMING5			(AR_PHY_BASE + 0x0124)
+#define AR_PHY_POWER_TX_RATE1		(AR_PHY_BASE + 0x0134)
+#define AR_PHY_POWER_TX_RATE2		(AR_PHY_BASE + 0x0138)
+#define AR_PHY_POWER_TX_RATE_MAX	(AR_PHY_BASE + 0x013c)
+#define AR_PHY_SWITCH_CHAIN_0		(AR_PHY_BASE + 0x0160)
+#define AR_PHY_SWITCH_COM		(AR_PHY_BASE + 0x0164)
+#define AR_PHY_HEAVY_CLIP_ENABLE	(AR_PHY_BASE + 0x01e0)
+#define AR_PHY_CCK_DETECT		(AR_PHY_BASE + 0x0a08)
+#define AR_PHY_GAIN_2GHZ		(AR_PHY_BASE + 0x0a0c)
+#define AR_PHY_POWER_TX_RATE3		(AR_PHY_BASE + 0x0a34)
+#define AR_PHY_POWER_TX_RATE4		(AR_PHY_BASE + 0x0a38)
+#define AR_PHY_TPCRG1			(AR_PHY_BASE + 0x0a58)
+#define AR_PHY_POWER_TX_RATE5		(AR_PHY_BASE + 0x0b8c)
+#define AR_PHY_POWER_TX_RATE6		(AR_PHY_BASE + 0x0b90)
+#define AR_PHY_POWER_TX_RATE7		(AR_PHY_BASE + 0x0bcc)
+#define AR_PHY_POWER_TX_RATE8		(AR_PHY_BASE + 0x0bd0)
+#define AR_PHY_POWER_TX_RATE9		(AR_PHY_BASE + 0x0bd4)
+#define AR_PHY_CCA			(AR_PHY_BASE + 0x3064)
 
 #define AR_SEEPROM_HW_TYPE_OFFSET	0x1374
+#define AR_EEPROM_OFFSET		0x1600
 
 #define AR_BANK4_CHUP			(1 << 0)
 #define AR_BANK4_BMODE_LF_SYNTH_FREQ	(1 << 1)
@@ -267,7 +292,7 @@ static const uint8_t ar_chans[] = {
  * section overhead (5.1KB instead of 8.5KB).
  */
 
-/* NB: offset from 0x9800. */
+/* NB: apply AR_PHY(). */
 static const uint16_t ar5416_phy_regs[] = {
 	0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007, 0x008,
 	0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 0x010, 0x011,
@@ -588,7 +613,7 @@ static const uint32_t ar5416_phy_vals_2ghz_20mhz[] = {
 	0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0
 };
 
-/* NB: offset from 0x9800. */
+/* NB: apply AR_PHY(). */
 static const uint8_t ar5416_banks_regs[] = {
 	0x2c, 0x38, 0x2c, 0x3b, 0x2c, 0x38, 0x3c, 0x2c, 0x3a, 0x2c, 0x39,
 	0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c,
@@ -896,6 +921,8 @@ struct otus_softc {
 	usbd_interface_handle		sc_iface;
 
 	struct ar5416eeprom		eeprom;
+	uint8_t				rxmask;
+	uint8_t				txmask;
 
 	usbd_pipe_handle		data_tx_pipe;
 	usbd_pipe_handle		data_rx_pipe;