diff options
| author | Alexander Yurchenko <grange@cvs.openbsd.org> | 2003-04-01 05:03:53 +0000 |
|---|---|---|
| committer | Alexander Yurchenko <grange@cvs.openbsd.org> | 2003-04-01 05:03:53 +0000 |
| commit | aa6c0fd39eb83b213305fa6402a0457169e1ce17 (patch) | |
| tree | 4f0f0d540217bac0764469d9e0a727b54508ae7c | |
| parent | 0b5cd158e7086da81f1fbd33b05f8f05b831ae76 (diff) | |
Add a couple of new pci subclasses and caps from NetBSD
ok jason@
| -rw-r--r-- | sys/dev/pci/pcireg.h | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h index a12392c95f1..c0bbe598daa 100644 --- a/sys/dev/pci/pcireg.h +++ b/sys/dev/pci/pcireg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pcireg.h,v 1.20 2003/02/08 18:24:53 jason Exp $ */ +/* $OpenBSD: pcireg.h,v 1.21 2003/04/01 05:03:52 grange Exp $ */ /* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ /* @@ -157,6 +157,7 @@ typedef u_int8_t pci_revision_t; #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 +#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 /* 0x02 network subclasses */ @@ -205,6 +206,8 @@ typedef u_int8_t pci_revision_t; #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 +#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 +#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 /* 0x08 system subclasses */ @@ -252,6 +255,10 @@ typedef u_int8_t pci_revision_t; #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 #define PCI_SUBCLASS_WIRELESS_RF 0x10 +#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 +#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 +#define PCI_SUBCLASS_WIRELESS_802_11A 0x20 +#define PCI_SUBCLASS_WIRELESS_802_11B 0x21 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 /* 0x0e I2O (Intelligent I/O) subclasses */ @@ -272,6 +279,8 @@ typedef u_int8_t pci_revision_t; /* 0x11 data acquisition and signal processing subclasses */ #define PCI_SUBCLASS_DASP_DPIO 0x00 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 +#define PCI_SUBCLASS_DASP_SYNC 0x10 +#define PCI_SUBCLASS_DASP_MGMT 0x20 #define PCI_SUBCLASS_DASP_MISC 0x80 /* @@ -427,7 +436,8 @@ typedef u_int8_t pci_revision_t; /* * capabilities link list (PCI rev. 2.2) */ -#define PCI_CAPLISTPTR_REG 0x34 +#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ +#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) @@ -445,6 +455,10 @@ typedef u_int8_t pci_revision_t; #define PCI_CAP_DEBUGPORT 0x0a #define PCI_CAP_CPCI_RSRCCTL 0x0b #define PCI_CAP_HOTPLUG 0x0c +#define PCI_CAP_AGP8 0x0e +#define PCI_CAP_SECURE 0x0f +#define PCI_CAP_PCIEXPRESS 0x10 +#define PCI_CAP_MSIX 0x11 /* * Power Management Control Status Register; access via capability pointer. |