Remove _InvalidateICachePage cache op, it isn't used by anything.

4 files changed, 13 insertions, 103 deletions

diff --git a/sys/arch/mips64/mips64/cache_r10k.S b/sys/arch/mips64/mips64/cache_r10k.S
index 45f13932c75..e75c65965db 100644
--- a/sys/arch/mips64/mips64/cache_r10k.S
+++ b/sys/arch/mips64/mips64/cache_r10k.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r10k.S,v 1.8 2009/05/22 20:37:53 miod Exp $ */
+/*	$OpenBSD: cache_r10k.S,v 1.9 2009/08/06 21:06:30 miod Exp $ */
 
 /*
  * Copyright (c) 2004 Opsycon AB (www.opsycon.se)
@@ -30,7 +30,8 @@
  *  Processors supported:
  *  R10000
  *  R12000
- *  R14000	(needs to be tested)
+ *  R14000
+ *  R16000
  */
 
 #include <sys/errno.h>
@@ -179,8 +180,8 @@ ConfResult:
 	sw	ta1, CpuPrimaryDataSetSize
 
 #if 0
-	and	v0, 0xfffffff8
-	or	v0, 0x00000003			# set cachable writeback kseg0
+	and	v0, ~7
+	or	v0, CCA_CACHED			# set cachable writeback kseg0
 	mtc0	v0, COP_0_CONFIG		# establish any new config
 #endif
 	j	ra
@@ -264,39 +265,6 @@ END(Mips10k_SyncCache)
 
 /*----------------------------------------------------------------------------
  *
- * Mips10k_InvalidateICachePage --
- *
- *	void Mips10k_InvalidateICachePage(addr)
- *		vaddr_t addr;
- *
- *	Invalidate the L1 instruction cache page given by addr.
- *
- * Results:
- *	Void.
- *
- * Side effects:
- *	The contents of the L1 Instruction cache is flushed.
- *
- *----------------------------------------------------------------------------
- */
-LEAF(Mips10k_InvalidateICachePage, 0)
-	lw	v0, CpuNWayCache		# Cache properties
-	and	a0, ~PAGE_MASK			# Page align start address
-	PTR_ADDU a1, a0, PAGE_SIZE-128		# End address.
-	addiu	v0, -2				# <0 1way, 0 = two, >0 four
-1:
-	cache	HitInvalidate_I, 0(a0)
-	cache	HitInvalidate_I, 64(a0)
-
-	bne	a0, a1, 1b
-	PTR_ADDU a0, 128
-
-	j	ra
-	move	v0, zero
-END(Mips10k_InvalidateICachePage)
-
-/*----------------------------------------------------------------------------
- *
  * Mips10k_InvalidateICache --
  *
  *	void Mips10k_SyncICache(addr, len)
diff --git a/sys/arch/mips64/mips64/cache_r5k.S b/sys/arch/mips64/mips64/cache_r5k.S
index ab305a29caa..a400c97d3a9 100644
--- a/sys/arch/mips64/mips64/cache_r5k.S
+++ b/sys/arch/mips64/mips64/cache_r5k.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r5k.S,v 1.23 2009/05/22 20:37:53 miod Exp $ */
+/*	$OpenBSD: cache_r5k.S,v 1.24 2009/08/06 21:06:30 miod Exp $ */
 
 /*
  * Copyright (c) 1998-2004 Opsycon AB (www.opsycon.se)
@@ -34,7 +34,7 @@
  *  configurations will need another set of cache functions.
  *
  *  Processors supported:
- *  R4600/R4700
+ *  R4600/R4700 (if option CPUR4600)
  *  R5000
  *  RM52xx
  *  RM7xxx
@@ -318,7 +318,6 @@ Conf7K:					# RM7000, check for L2 and L3 cache
 	bne	t0, t1, 1b
 	nop
 
-
 Conf7KL2:
 	and	t1, v0, CF_7_SC			# check for L2 cache
 	bnez	t1, ConfResult
@@ -387,8 +386,8 @@ ConfResult:
 	srl	ta1, t2				# calculate set size.
 	sw	ta1, CpuPrimaryDataSetSize
 
-	and	v0, 0xfffffff8
-	or	v0, 0x00000003			# set cachable writeback kseg0
+	and	v0, ~7
+	or	v0, CCA_CACHED			# set cachable writeback kseg0
 	mtc0	v0, COP_0_CONFIG		# establish any new config
 	NOP10
 	j	ra
@@ -513,51 +512,6 @@ END(Mips5k_SyncCache)
 
 /*----------------------------------------------------------------------------
  *
- * Mips5k_InvalidateICachePage --
- *
- *	void Mips5k_InvalidateICachePage(addr)
- *		vaddr_t addr;
- *
- *	Invalidate the L1 instruction cache page given by addr.
- *
- * Results:
- *	Void.
- *
- * Side effects:
- *	The contents of the L1 Instruction cache is flushed.
- *
- *----------------------------------------------------------------------------
- */
-LEAF(Mips5k_InvalidateICachePage, 0)
-#ifdef CPUR4600
-	mfc0	v1, COP_0_STATUS_REG		# Save the status register.
-	li	v0, SR_DIAG_DE
-	mtc0	v0, COP_0_STATUS_REG		# Disable interrupts
-#endif
-	lw	v0, CpuNWayCache		# Cache properties
-	lw	t0, CpuPrimaryInstSetSize	# Set size
-	and	a0, ~PAGE_MASK			# Page align start address
-	PTR_ADDU a1, a0, PAGE_SIZE-128		# End address.
-	addiu	v0, -2				# <0 1way, 0 = two, >0 four
-1:
-	cache	HitInvalidate_I, 0(a0)
-	cache	HitInvalidate_I, 32(a0)
-	cache	HitInvalidate_I, 64(a0)
-	cache	HitInvalidate_I, 96(a0)
-
-	bne	a0, a1, 1b
-	PTR_ADDU a0, 128
-
-#ifdef CPUR4600
-	mtc0	v1, COP_0_STATUS_REG	# Restore the status register.
-	NOP10
-#endif
-	j	ra
-	move	v0, zero
-END(Mips5k_InvalidateICachePage)
-
-/*----------------------------------------------------------------------------
- *
  * Mips5k_InvalidateICache --
  *
  *	void Mips5k_SyncICache(addr, len)
@@ -595,7 +549,7 @@ LEAF(Mips5k_InvalidateICache, 0)
 	addiu	v0, -2				# <0 1way, 0 = two, >0 four
 1:
 	bltz	v0, 3f
-	addu	a1, -1
+	PTR_ADDU a1, -1
 
 2:
 	PTR_ADDU t1, t0, a0			# Nway cache, flush set B.
@@ -706,9 +660,6 @@ END(Mips5k_SyncDCachePage)
  *	as no TLB invalid traps occur. Only lines with matching
  *	addr are flushed.
  *
- *	Note: Use the CpuNWayCache flag to select 16 or 32 byte linesize.
- *	      All Nway cpu's now available have a fixed 32byte linesize.
- *
  * Results:
  *	None.
  *
@@ -954,7 +905,7 @@ NON_LEAF(Mips5k_IOSyncDCache, FRAMESZ(CF_SZ+2*REGSZ), ra)
 	and	t0, CTYPE_HAS_IL2		# Have internal L2?
 	bnez	t0, SyncSC			# Yes
 	nop
-	jal	 Mips5k_HitSyncDCache		# No flush L1.
+	jal	Mips5k_HitSyncDCache		# No flush L1.
 	nop
 	b	SyncDone
 	PTR_L	ra, CF_RA_OFFS+2*REGSZ(sp)
diff --git a/sys/arch/sgi/include/autoconf.h b/sys/arch/sgi/include/autoconf.h
index 0b16587d677..e6a83e4ce2d 100644
--- a/sys/arch/sgi/include/autoconf.h
+++ b/sys/arch/sgi/include/autoconf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: autoconf.h,v 1.18 2009/06/13 21:48:03 miod Exp $ */
+/*	$OpenBSD: autoconf.h,v 1.19 2009/08/06 21:06:32 miod Exp $ */
 
 /*
  * Copyright (c) 2001-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -59,7 +59,6 @@ struct sys_rec {
 	/* Published cache operations. */
 	void    (*_SyncCache)(void);
 	void    (*_InvalidateICache)(vaddr_t, int);
-	void    (*_InvalidateICachePage)(vaddr_t);
 	void    (*_SyncDCachePage)(vaddr_t);
 	void    (*_HitSyncDCache)(vaddr_t, int);
 	void    (*_IOSyncDCache)(vaddr_t, int, int);
diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c
index 3cb3c3c2679..3ff20a98bd3 100644
--- a/sys/arch/sgi/sgi/machdep.c
+++ b/sys/arch/sgi/sgi/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.77 2009/08/06 21:05:50 miod Exp $ */
+/*	$OpenBSD: machdep.c,v 1.78 2009/08/06 21:06:32 miod Exp $ */
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -27,25 +27,19 @@
  */
 #include <sys/param.h>
 #include <sys/systm.h>
-#include <sys/signalvar.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/buf.h>
 #include <sys/reboot.h>
 #include <sys/conf.h>
 #include <sys/file.h>
-#include <sys/malloc.h>
-#include <sys/mbuf.h>
 #include <sys/msgbuf.h>
-#include <sys/ioctl.h>
-#include <sys/tty.h>
 #include <sys/user.h>
 #include <sys/exec.h>
 #include <sys/sysctl.h>
 #include <sys/mount.h>
 #include <sys/syscallargs.h>
 #include <sys/exec_elf.h>
-#include <sys/extent.h>
 #ifdef SYSVSHM
 #include <sys/shm.h>
 #endif
@@ -458,7 +452,6 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 		Mips10k_ConfigCache();
 		sys_config._SyncCache = Mips10k_SyncCache;
 		sys_config._InvalidateICache = Mips10k_InvalidateICache;
-		sys_config._InvalidateICachePage = Mips10k_InvalidateICachePage;
 		sys_config._SyncDCachePage = Mips10k_SyncDCachePage;
 		sys_config._HitSyncDCache = Mips10k_HitSyncDCache;
 		sys_config._IOSyncDCache = Mips10k_IOSyncDCache;
@@ -469,7 +462,6 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 		Mips5k_ConfigCache();
 		sys_config._SyncCache = Mips5k_SyncCache;
 		sys_config._InvalidateICache = Mips5k_InvalidateICache;
-		sys_config._InvalidateICachePage = Mips5k_InvalidateICachePage;
 		sys_config._SyncDCachePage = Mips5k_SyncDCachePage;
 		sys_config._HitSyncDCache = Mips5k_HitSyncDCache;
 		sys_config._IOSyncDCache = Mips5k_IOSyncDCache;