Move the code that decodes the i.MX6 PLLs and PFDs into imxanatop(4)

instead of having imxccm(4) map more than it should and access the
memory space that imxanatop(4) should be responsible for.

ok kettenis@

7 files changed, 271 insertions, 216 deletions

diff --git a/sys/arch/arm64/conf/GENERIC b/sys/arch/arm64/conf/GENERIC
index 955099c9220..8c8728199ca 100644
--- a/sys/arch/arm64/conf/GENERIC
+++ b/sys/arch/arm64/conf/GENERIC
@@ -1,4 +1,4 @@
-# $OpenBSD: GENERIC,v 1.70 2018/05/16 13:21:50 patrick Exp $
+# $OpenBSD: GENERIC,v 1.71 2018/05/16 13:42:35 patrick Exp $
 #
 # GENERIC machine description file
 #
@@ -89,7 +89,7 @@ wsdisplay*	at simplefb?
 # iMX
 imxccm*		at fdt? early 1
 imxiomuxc*	at fdt? early 1
-imxanatop*	at fdt?
+imxanatop*	at fdt? early 1
 imxgpc*		at fdt?
 imxgpio*	at fdt?
 fec*		at fdt?
diff --git a/sys/arch/arm64/conf/RAMDISK b/sys/arch/arm64/conf/RAMDISK
index 6a5713e7a1e..f71c48183a0 100644
--- a/sys/arch/arm64/conf/RAMDISK
+++ b/sys/arch/arm64/conf/RAMDISK
@@ -1,4 +1,4 @@
-# $OpenBSD: RAMDISK,v 1.59 2018/05/16 13:21:50 patrick Exp $
+# $OpenBSD: RAMDISK,v 1.60 2018/05/16 13:42:35 patrick Exp $
 #
 # GENERIC machine description file
 #
@@ -95,7 +95,7 @@ wsdisplay*	at simplefb?
 # iMX
 imxccm*		at fdt? early 1
 imxiomuxc*	at fdt? early 1
-imxanatop*	at fdt?
+imxanatop*	at fdt? early 1
 imxgpc*		at fdt?
 imxgpio*	at fdt?
 fec*		at fdt?
diff --git a/sys/arch/armv7/conf/GENERIC b/sys/arch/armv7/conf/GENERIC
index 052f73bf71f..8d2ff0ae4dd 100644
--- a/sys/arch/armv7/conf/GENERIC
+++ b/sys/arch/armv7/conf/GENERIC
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC,v 1.106 2018/01/06 13:05:20 kettenis Exp $
+#	$OpenBSD: GENERIC,v 1.107 2018/05/16 13:42:35 patrick Exp $
 #
 # For further information on compiling OpenBSD kernels, see the config(8)
 # man page.
@@ -41,7 +41,7 @@ armliicc*	at cortex?
 # iMX
 imxccm*		at fdt? early 1		# clock control module
 imxiomuxc*	at fdt? early 1		# iomux controller
-imxanatop*	at fdt?			# anatop controller
+imxanatop*	at fdt? early 1		# anatop controller
 imxgpc*		at fdt?			# power controller
 imxdog*		at fdt?			# watchdog timer
 imxtemp*	at fdt?			# temperature monitor
diff --git a/sys/arch/armv7/conf/RAMDISK b/sys/arch/armv7/conf/RAMDISK
index c1bb9d21fc8..ad95d5eaa23 100644
--- a/sys/arch/armv7/conf/RAMDISK
+++ b/sys/arch/armv7/conf/RAMDISK
@@ -1,4 +1,4 @@
-#	$OpenBSD: RAMDISK,v 1.96 2018/04/01 19:28:32 patrick Exp $
+#	$OpenBSD: RAMDISK,v 1.97 2018/05/16 13:42:35 patrick Exp $
 
 machine		armv7 arm
 
@@ -42,7 +42,7 @@ armliicc*	at cortex?
 # iMX
 imxccm*		at fdt? early 1		# clock control module
 imxiomuxc*	at fdt? early 1		# iomux controller
-imxanatop*	at fdt?			# anatop controller
+imxanatop*	at fdt? early 1		# anatop controller
 imxgpc*		at fdt?			# power controller
 imxdog*		at fdt?			# watchdog timer
 imxgpio*	at fdt?			# user-visible GPIO pins?
diff --git a/sys/dev/fdt/imxanatop.c b/sys/dev/fdt/imxanatop.c
index 1835bbb222b..f29564782e1 100644
--- a/sys/dev/fdt/imxanatop.c
+++ b/sys/dev/fdt/imxanatop.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxanatop.c,v 1.1 2018/03/30 20:38:27 patrick Exp $ */
+/* $OpenBSD: imxanatop.c,v 1.2 2018/05/16 13:42:35 patrick Exp $ */
 /*
  * Copyright (c) 2016 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -28,10 +28,74 @@
 #include <dev/ofw/ofw_regulator.h>
 #include <dev/ofw/fdt.h>
 
+#include <dev/fdt/imxanatopvar.h>
+
+#define ANALOG_PLL_ARM				0x0000
+#define ANALOG_PLL_ARM_SET			0x0004
+#define ANALOG_PLL_ARM_CLR			0x0008
+#define  ANALOG_PLL_ARM_DIV_SELECT_MASK			0x7f
+#define  ANALOG_PLL_ARM_BYPASS				(1 << 16)
+#define ANALOG_PLL_USB1				0x0010
+#define ANALOG_PLL_USB1_SET			0x0014
+#define ANALOG_PLL_USB1_CLR			0x0018
+#define  ANALOG_PLL_USB1_DIV_SELECT_MASK		0x1
+#define  ANALOG_PLL_USB1_EN_USB_CLKS			(1 << 6)
+#define  ANALOG_PLL_USB1_POWER				(1 << 12)
+#define  ANALOG_PLL_USB1_ENABLE				(1 << 13)
+#define  ANALOG_PLL_USB1_BYPASS				(1 << 16)
+#define  ANALOG_PLL_USB1_LOCK				(1U << 31)
+#define ANALOG_PLL_USB2				0x0020
+#define ANALOG_PLL_USB2_SET			0x0024
+#define ANALOG_PLL_USB2_CLR			0x0028
+#define  ANALOG_PLL_USB2_DIV_SELECT_MASK		0x1
+#define  ANALOG_PLL_USB2_EN_USB_CLKS			(1 << 6)
+#define  ANALOG_PLL_USB2_POWER				(1 << 12)
+#define  ANALOG_PLL_USB2_ENABLE				(1 << 13)
+#define  ANALOG_PLL_USB2_BYPASS				(1 << 16)
+#define  ANALOG_PLL_USB2_LOCK				(1U << 31)
+#define ANALOG_PLL_SYS				0x0030
+#define  ANALOG_PLL_SYS_DIV_SELECT_MASK			0x1
+#define ANALOG_PLL_ENET				0x00e0
+#define ANALOG_PLL_ENET_SET			0x00e4
+#define ANALOG_PLL_ENET_CLR			0x00e8
+#define  ANALOG_PLL_ENET_DIV_125M			(1 << 11)
+#define  ANALOG_PLL_ENET_POWERDOWN			(1 << 12)
+#define  ANALOG_PLL_ENET_ENABLE				(1 << 13)
+#define  ANALOG_PLL_ENET_BYPASS				(1 << 16)
+#define  ANALOG_PLL_ENET_125M_PCIE			(1 << 19)
+#define  ANALOG_PLL_ENET_100M_SATA			(1 << 20)
+#define  ANALOG_PLL_ENET_LOCK				(1U << 31)
+#define ANALOG_PFD_480				0x00f0
+#define ANALOG_PFD_480_SET			0x00f4
+#define ANALOG_PFD_480_CLR			0x00f8
+#define  ANALOG_PFD_480_PFDx_FRAC(x, y)			(((x) >> ((y) << 3)) & 0x3f)
+#define ANALOG_PFD_528				0x0100
+#define ANALOG_PFD_528_SET			0x0104
+#define ANALOG_PFD_528_CLR			0x0108
+#define  ANALOG_PFD_528_PFDx_FRAC(x, y)			(((x) >> ((y) << 3)) & 0x3f)
+#define ANALOG_USB1_CHRG_DETECT			0x01b0
+#define ANALOG_USB1_CHRG_DETECT_SET		0x01b4
+#define ANALOG_USB1_CHRG_DETECT_CLR		0x01b8
+#define  ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B		(1 << 19)
+#define  ANALOG_USB1_CHRG_DETECT_EN_B			(1 << 20)
+#define ANALOG_USB2_CHRG_DETECT			0x0210
+#define ANALOG_USB2_CHRG_DETECT_SET		0x0214
+#define ANALOG_USB2_CHRG_DETECT_CLR		0x0218
+#define  ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B		(1 << 19)
+#define  ANALOG_USB2_CHRG_DETECT_EN_B			(1 << 20)
+#define ANALOG_DIGPROG				0x0260
+#define  ANALOG_DIGPROG_MINOR_MASK			0xff
+
+#define HCLK_FREQ				24000000
+
 #define HREAD4(sc, reg)							\
 	(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
 #define HWRITE4(sc, reg, val)						\
 	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
+#define HSET4(sc, reg, bits)						\
+	HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
+#define HCLR4(sc, reg, bits)						\
+	HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
 
 struct imxanatop_softc {
 	struct device		sc_dev;
@@ -39,6 +103,8 @@ struct imxanatop_softc {
 	bus_space_handle_t	sc_ioh;
 };
 
+struct imxanatop_softc *imxanatop_sc;
+
 struct imxanatop_regulator {
 	struct imxanatop_softc *ir_sc;
 
@@ -71,6 +137,15 @@ void	imxanatop_attach_regulator(struct imxanatop_softc *, int);
 uint32_t imxanatop_get_voltage(void *);
 int	imxanatop_set_voltage(void *, uint32_t);
 
+uint32_t imxanatop_decode_pll(enum imxanatop_clocks, uint32_t);
+uint32_t imxanatop_get_pll2_pfd(unsigned int);
+uint32_t imxanatop_get_pll3_pfd(unsigned int);
+void	imxanatop_enable_pll_usb1(void);
+void	imxanatop_enable_pll_usb2(void);
+void	imxanatop_enable_pll_enet(void);
+void	imxanatop_enable_enet(void);
+void	imxanatop_enable_sata(void);
+
 int
 imxanatop_match(struct device *parent, void *match, void *aux)
 {
@@ -110,6 +185,8 @@ imxanatop_attach(struct device *parent, struct device *self, void *aux)
 	for (node = OF_child(faa->fa_node); node; node = OF_peer(node))
 		if (OF_is_compatible(node, "fsl,anatop-regulator"))
 			imxanatop_attach_regulator(sc, node);
+
+	imxanatop_sc = sc;
 }
 
 void
@@ -185,3 +262,118 @@ imxanatop_set_voltage(void *cookie, uint32_t voltage)
 
 	return 0;
 }
+
+uint32_t
+imxanatop_decode_pll(enum imxanatop_clocks pll, uint32_t freq)
+{
+	struct imxanatop_softc *sc = imxanatop_sc;
+	uint32_t div;
+
+	KASSERT(sc != NULL);
+
+	switch (pll) {
+	case ARM_PLL1:
+		if (HREAD4(sc, ANALOG_PLL_ARM)
+		    & ANALOG_PLL_ARM_BYPASS)
+			return freq;
+		div = HREAD4(sc, ANALOG_PLL_ARM)
+		    & ANALOG_PLL_ARM_DIV_SELECT_MASK;
+		return (freq * div) / 2;
+	case SYS_PLL2:
+		div = HREAD4(sc, ANALOG_PLL_SYS)
+		    & ANALOG_PLL_SYS_DIV_SELECT_MASK;
+		return freq * (20 + (div << 1));
+	case USB1_PLL3:
+		div = HREAD4(sc, ANALOG_PLL_USB2)
+		    & ANALOG_PLL_USB2_DIV_SELECT_MASK;
+		return freq * (20 + (div << 1));
+	default:
+		return 0;
+	}
+}
+
+uint32_t
+imxanatop_get_pll2_pfd(unsigned int pfd)
+{
+	struct imxanatop_softc *sc = imxanatop_sc;
+	KASSERT(sc != NULL);
+
+	return imxanatop_decode_pll(SYS_PLL2, HCLK_FREQ) * 18ULL
+	    / ANALOG_PFD_528_PFDx_FRAC(HREAD4(sc, ANALOG_PFD_528), pfd);
+}
+
+uint32_t
+imxanatop_get_pll3_pfd(unsigned int pfd)
+{
+	struct imxanatop_softc *sc = imxanatop_sc;
+	KASSERT(sc != NULL);
+
+	return imxanatop_decode_pll(USB1_PLL3, HCLK_FREQ) * 18ULL
+	    / ANALOG_PFD_480_PFDx_FRAC(HREAD4(sc, ANALOG_PFD_480), pfd);
+}
+
+void
+imxanatop_enable_pll_enet(void)
+{
+	struct imxanatop_softc *sc = imxanatop_sc;
+	KASSERT(sc != NULL);
+
+	if (HREAD4(sc, ANALOG_PLL_ENET) & ANALOG_PLL_ENET_ENABLE)
+		return;
+
+	HCLR4(sc, ANALOG_PLL_ENET, ANALOG_PLL_ENET_POWERDOWN);
+
+	HSET4(sc, ANALOG_PLL_ENET, ANALOG_PLL_ENET_ENABLE);
+
+	while(!(HREAD4(sc, ANALOG_PLL_ENET) & ANALOG_PLL_ENET_LOCK));
+
+	HCLR4(sc, ANALOG_PLL_ENET, ANALOG_PLL_ENET_BYPASS);
+}
+
+void
+imxanatop_enable_enet(void)
+{
+	struct imxanatop_softc *sc = imxanatop_sc;
+	KASSERT(sc != NULL);
+
+	imxanatop_enable_pll_enet();
+	HWRITE4(sc, ANALOG_PLL_ENET_SET, ANALOG_PLL_ENET_DIV_125M);
+}
+
+void
+imxanatop_enable_sata(void)
+{
+	struct imxanatop_softc *sc = imxanatop_sc;
+	KASSERT(sc != NULL);
+
+	imxanatop_enable_pll_enet();
+	HWRITE4(sc, ANALOG_PLL_ENET_SET, ANALOG_PLL_ENET_100M_SATA);
+}
+
+void
+imxanatop_enable_pll_usb1(void)
+{
+	struct imxanatop_softc *sc = imxanatop_sc;
+	KASSERT(sc != NULL);
+
+	HWRITE4(sc, ANALOG_PLL_USB1_CLR, ANALOG_PLL_USB1_BYPASS);
+
+	HWRITE4(sc, ANALOG_PLL_USB1_SET,
+	      ANALOG_PLL_USB1_ENABLE
+	    | ANALOG_PLL_USB1_POWER
+	    | ANALOG_PLL_USB1_EN_USB_CLKS);
+}
+
+void
+imxanatop_enable_pll_usb2(void)
+{
+	struct imxanatop_softc *sc = imxanatop_sc;
+	KASSERT(sc != NULL);
+
+	HWRITE4(sc, ANALOG_PLL_USB2_CLR, ANALOG_PLL_USB2_BYPASS);
+
+	HWRITE4(sc, ANALOG_PLL_USB2_SET,
+	      ANALOG_PLL_USB2_ENABLE
+	    | ANALOG_PLL_USB2_POWER
+	    | ANALOG_PLL_USB2_EN_USB_CLKS);
+}
diff --git a/sys/dev/fdt/imxanatopvar.h b/sys/dev/fdt/imxanatopvar.h
new file mode 100644
index 00000000000..fbee17247c8
--- /dev/null
+++ b/sys/dev/fdt/imxanatopvar.h
@@ -0,0 +1,51 @@
+/* $OpenBSD: imxanatopvar.h,v 1.1 2018/05/16 13:42:35 patrick Exp $ */
+/*
+ * Copyright (c) 2018 Patrick Wildt <patrick@blueri.se>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+enum imxanatop_clocks {
+	/* OSC */
+	OSC,		/* 24 MHz OSC */
+
+	/* PLLs */
+	ARM_PLL1,	/* ARM core PLL */
+	SYS_PLL2,	/* System PLL: 528 MHz */
+	USB1_PLL3,	/* OTG USB PLL: 480 MHz */
+	USB2_PLL,	/* Host USB PLL: 480 MHz */
+	AUD_PLL4,	/* Audio PLL */
+	VID_PLL5,	/* Video PLL */
+	ENET_PLL6,	/* ENET PLL */
+	MLB_PLL,	/* MLB PLL */
+
+	/* SYS_PLL2 PFDs */
+	SYS_PLL2_PFD0,	/* 352 MHz */
+	SYS_PLL2_PFD1,	/* 594 MHz */
+	SYS_PLL2_PFD2,	/* 396 MHz */
+
+	/* USB1_PLL3 PFDs */
+	USB1_PLL3_PFD0,	/* 720 MHz */
+	USB1_PLL3_PFD1,	/* 540 MHz */
+	USB1_PLL3_PFD2,	/* 508.2 MHz */
+	USB1_PLL3_PFD3,	/* 454.7 MHz */
+};
+
+uint32_t imxanatop_decode_pll(enum imxanatop_clocks, uint32_t);
+uint32_t imxanatop_get_pll2_pfd(unsigned int);
+uint32_t imxanatop_get_pll3_pfd(unsigned int);
+void imxanatop_enable_pll_usb1(void);
+void imxanatop_enable_pll_usb2(void);
+void imxanatop_enable_pll_enet(void);
+void imxanatop_enable_enet(void);
+void imxanatop_enable_sata(void);
diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c
index 4153b754fde..186a6c911ab 100644
--- a/sys/dev/fdt/imxccm.c
+++ b/sys/dev/fdt/imxccm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxccm.c,v 1.1 2018/04/02 16:47:39 patrick Exp $ */
+/* $OpenBSD: imxccm.c,v 1.2 2018/05/16 13:42:35 patrick Exp $ */
 /*
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
  *
@@ -33,6 +33,8 @@
 #include <dev/ofw/ofw_clock.h>
 #include <dev/ofw/fdt.h>
 
+#include <dev/fdt/imxanatopvar.h>
+
 /* registers */
 #define CCM_CCR		0x00
 #define CCM_CCDR	0x04
@@ -69,35 +71,6 @@
 #define CCM_CCGR7	0x84
 #define CCM_CMEOR	0x88
 
-/* ANALOG */
-#define CCM_ANALOG_PLL_ARM			0x4000
-#define CCM_ANALOG_PLL_ARM_SET			0x4004
-#define CCM_ANALOG_PLL_ARM_CLR			0x4008
-#define CCM_ANALOG_PLL_USB1			0x4010
-#define CCM_ANALOG_PLL_USB1_SET			0x4014
-#define CCM_ANALOG_PLL_USB1_CLR			0x4018
-#define CCM_ANALOG_PLL_USB2			0x4020
-#define CCM_ANALOG_PLL_USB2_SET			0x4024
-#define CCM_ANALOG_PLL_USB2_CLR			0x4028
-#define CCM_ANALOG_PLL_SYS			0x4030
-#define CCM_ANALOG_USB1_CHRG_DETECT		0x41b0
-#define CCM_ANALOG_USB1_CHRG_DETECT_SET		0x41b4
-#define CCM_ANALOG_USB1_CHRG_DETECT_CLR		0x41b8
-#define CCM_ANALOG_USB2_CHRG_DETECT		0x4210
-#define CCM_ANALOG_USB2_CHRG_DETECT_SET		0x4214
-#define CCM_ANALOG_USB2_CHRG_DETECT_CLR		0x4218
-#define CCM_ANALOG_DIGPROG			0x4260
-#define CCM_ANALOG_PLL_ENET			0x40e0
-#define CCM_ANALOG_PLL_ENET_SET			0x40e4
-#define CCM_ANALOG_PLL_ENET_CLR			0x40e8
-#define CCM_ANALOG_PFD_480			0x40f0
-#define CCM_ANALOG_PFD_480_SET			0x40f4
-#define CCM_ANALOG_PFD_480_CLR			0x40f8
-#define CCM_ANALOG_PFD_528			0x4100
-#define CCM_ANALOG_PFD_528_SET			0x4104
-#define CCM_ANALOG_PFD_528_CLR			0x4108
-#define CCM_PMU_MISC1				0x4160
-
 /* bits and bytes */
 #define CCM_CCSR_PLL3_SW_CLK_SEL		(1 << 0)
 #define CCM_CCSR_PLL2_SW_CLK_SEL		(1 << 1)
@@ -122,39 +95,6 @@
 #define CCM_CCGR5_100M_SATA			(3 << 4)
 #define CCM_CSCMR1_PERCLK_CLK_PODF_MASK		0x1f
 #define CCM_CSCMR1_PERCLK_CLK_SEL_MASK		(1 << 6)
-#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK	0x7f
-#define CCM_ANALOG_PLL_ARM_BYPASS		(1 << 16)
-#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK	0x1
-#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS		(1 << 6)
-#define CCM_ANALOG_PLL_USB1_POWER		(1 << 12)
-#define CCM_ANALOG_PLL_USB1_ENABLE		(1 << 13)
-#define CCM_ANALOG_PLL_USB1_BYPASS		(1 << 16)
-#define CCM_ANALOG_PLL_USB1_LOCK		(1 << 31)
-#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK	0x1
-#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS		(1 << 6)
-#define CCM_ANALOG_PLL_USB2_POWER		(1 << 12)
-#define CCM_ANALOG_PLL_USB2_ENABLE		(1 << 13)
-#define CCM_ANALOG_PLL_USB2_BYPASS		(1 << 16)
-#define CCM_ANALOG_PLL_USB2_LOCK		(1U << 31)
-#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK	0x1
-#define CCM_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B	(1 << 19)
-#define CCM_ANALOG_USB1_CHRG_DETECT_EN_B	(1 << 20)
-#define CCM_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B	(1 << 19)
-#define CCM_ANALOG_USB2_CHRG_DETECT_EN_B	(1 << 20)
-#define CCM_ANALOG_DIGPROG_MINOR_MASK		0xff
-#define CCM_ANALOG_PLL_ENET_DIV_125M		(1 << 11)
-#define CCM_ANALOG_PLL_ENET_POWERDOWN		(1 << 12)
-#define CCM_ANALOG_PLL_ENET_ENABLE		(1 << 13)
-#define CCM_ANALOG_PLL_ENET_BYPASS		(1 << 16)
-#define CCM_ANALOG_PLL_ENET_125M_PCIE		(1 << 19)
-#define CCM_ANALOG_PLL_ENET_100M_SATA		(1 << 20)
-#define CCM_ANALOG_PLL_ENET_LOCK		(1U << 31)
-#define CCM_ANALOG_PFD_480_PFDx_FRAC(x, y)	(((x) >> ((y) << 3)) & 0x3f)
-#define CCM_ANALOG_PFD_528_PFDx_FRAC(x, y)	(((x) >> ((y) << 3)) & 0x3f)
-#define CCM_PMU_MISC1_LVDSCLK1_CLK_SEL_SATA	(0xB << 0)
-#define CCM_PMU_MISC1_LVDSCLK1_CLK_SEL_MASK	(0x1f << 0)
-#define CCM_PMU_MISC1_LVDSCLK1_OBEN		(1 << 10)
-#define CCM_PMU_MISC1_LVDSCLK1_IBEN		(1 << 12)
 
 #define HCLK_FREQ				24000000
 #define PLL3_80M				80000000
@@ -187,32 +127,6 @@ struct imxccm_softc {
 	struct clock_device	sc_cd;
 };
 
-enum clocks {
-	/* OSC */
-	OSC,		/* 24 MHz OSC */
-
-	/* PLLs */
-	ARM_PLL1,	/* ARM core PLL */
-	SYS_PLL2,	/* System PLL: 528 MHz */
-	USB1_PLL3,	/* OTG USB PLL: 480 MHz */
-	USB2_PLL,	/* Host USB PLL: 480 MHz */
-	AUD_PLL4,	/* Audio PLL */
-	VID_PLL5,	/* Video PLL */
-	ENET_PLL6,	/* ENET PLL */
-	MLB_PLL,	/* MLB PLL */
-
-	/* SYS_PLL2 PFDs */
-	SYS_PLL2_PFD0,	/* 352 MHz */
-	SYS_PLL2_PFD1,	/* 594 MHz */
-	SYS_PLL2_PFD2,	/* 396 MHz */
-
-	/* USB1_PLL3 PFDs */
-	USB1_PLL3_PFD0,	/* 720 MHz */
-	USB1_PLL3_PFD1,	/* 540 MHz */
-	USB1_PLL3_PFD2,	/* 508.2 MHz */
-	USB1_PLL3_PFD3,	/* 454.7 MHz */
-};
-
 int	imxccm_match(struct device *, void *, void *);
 void	imxccm_attach(struct device *parent, struct device *self, void *args);
 
@@ -224,11 +138,8 @@ struct cfdriver imxccm_cd = {
 	NULL, "imxccm", DV_DULL
 };
 
-uint32_t imxccm_decode_pll(struct imxccm_softc *, enum clocks, uint32_t);
-uint32_t imxccm_get_pll2_pfd(struct imxccm_softc *, unsigned int);
-uint32_t imxccm_get_pll3_pfd(struct imxccm_softc *, unsigned int);
 uint32_t imxccm_get_armclk(struct imxccm_softc *);
-void imxccm_armclk_set_parent(struct imxccm_softc *, enum clocks);
+void imxccm_armclk_set_parent(struct imxccm_softc *, enum imxanatop_clocks);
 uint32_t imxccm_get_usdhx(struct imxccm_softc *, int x);
 uint32_t imxccm_get_periphclk(struct imxccm_softc *);
 uint32_t imxccm_get_ahbclk(struct imxccm_softc *);
@@ -237,11 +148,6 @@ uint32_t imxccm_get_ipg_perclk(struct imxccm_softc *);
 uint32_t imxccm_get_uartclk(struct imxccm_softc *);
 void imxccm_enable(void *, uint32_t *, int);
 uint32_t imxccm_get_frequency(void *, uint32_t *);
-void imxccm_enable_pll_usb1(struct imxccm_softc *);
-void imxccm_enable_pll_usb2(struct imxccm_softc *);
-void imxccm_enable_pll_enet(struct imxccm_softc *);
-void imxccm_enable_enet(struct imxccm_softc *);
-void imxccm_enable_sata(struct imxccm_softc *);
 
 int
 imxccm_match(struct device *parent, void *match, void *aux)
@@ -265,7 +171,7 @@ imxccm_attach(struct device *parent, struct device *self, void *aux)
 	sc->sc_node = faa->fa_node;
 	sc->sc_iot = faa->fa_iot;
 	if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
-	    faa->fa_reg[0].size + 0x1000, 0, &sc->sc_ioh))
+	    faa->fa_reg[0].size, 0, &sc->sc_ioh))
 		panic("%s: bus_space_map failed!", __func__);
 
 	if (OF_is_compatible(sc->sc_node, "fsl,imx6ul-ccm")) {
@@ -276,10 +182,6 @@ imxccm_attach(struct device *parent, struct device *self, void *aux)
 		sc->sc_ngates = nitems(imx6_gates);
 	}
 
-	printf(": imx6 rev 1.%d CPU freq: %d MHz",
-	    HREAD4(sc, CCM_ANALOG_DIGPROG) & CCM_ANALOG_DIGPROG_MINOR_MASK,
-	    imxccm_get_armclk(sc) / 1000000);
-
 	printf("\n");
 
 	sc->sc_cd.cd_node = faa->fa_node;
@@ -290,60 +192,20 @@ imxccm_attach(struct device *parent, struct device *self, void *aux)
 }
 
 uint32_t
-imxccm_decode_pll(struct imxccm_softc *sc, enum clocks pll, uint32_t freq)
-{
-	uint32_t div;
-
-	switch (pll) {
-	case ARM_PLL1:
-		if (HREAD4(sc, CCM_ANALOG_PLL_ARM)
-		    & CCM_ANALOG_PLL_ARM_BYPASS)
-			return freq;
-		div = HREAD4(sc, CCM_ANALOG_PLL_ARM)
-		    & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK;
-		return (freq * div) / 2;
-	case SYS_PLL2:
-		div = HREAD4(sc, CCM_ANALOG_PLL_SYS)
-		    & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK;
-		return freq * (20 + (div << 1));
-	case USB1_PLL3:
-		div = HREAD4(sc, CCM_ANALOG_PLL_USB2)
-		    & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK;
-		return freq * (20 + (div << 1));
-	default:
-		return 0;
-	}
-}
-
-uint32_t
-imxccm_get_pll2_pfd(struct imxccm_softc *sc, unsigned int pfd)
-{
-	return imxccm_decode_pll(sc, SYS_PLL2, HCLK_FREQ) * 18ULL
-	    / CCM_ANALOG_PFD_528_PFDx_FRAC(HREAD4(sc, CCM_ANALOG_PFD_528), pfd);
-}
-
-uint32_t
-imxccm_get_pll3_pfd(struct imxccm_softc *sc, unsigned int pfd)
-{
-	return imxccm_decode_pll(sc, USB1_PLL3, HCLK_FREQ) * 18ULL
-	    / CCM_ANALOG_PFD_480_PFDx_FRAC(HREAD4(sc, CCM_ANALOG_PFD_480), pfd);
-}
-
-uint32_t
 imxccm_get_armclk(struct imxccm_softc *sc)
 {
 	uint32_t ccsr = HREAD4(sc, CCM_CCSR);
 
 	if (!(ccsr & CCM_CCSR_PLL1_SW_CLK_SEL))
-		return imxccm_decode_pll(sc, ARM_PLL1, HCLK_FREQ);
+		return imxanatop_decode_pll(ARM_PLL1, HCLK_FREQ);
 	else if (ccsr & CCM_CCSR_STEP_SEL)
-		return imxccm_get_pll2_pfd(sc, 2);
+		return imxanatop_get_pll2_pfd(2);
 	else
 		return HCLK_FREQ;
 }
 
 void
-imxccm_armclk_set_parent(struct imxccm_softc *sc, enum clocks clock)
+imxccm_armclk_set_parent(struct imxccm_softc *sc, enum imxanatop_clocks clock)
 {
 	switch (clock)
 	{
@@ -384,9 +246,9 @@ imxccm_get_usdhx(struct imxccm_softc *sc, int x)
 		podf = ((cscdr1 >> (10 + 3*x)) & CCM_CSCDR1_USDHCx_PODF_MASK);
 
 	if (cscmr1 & (1 << CCM_CSCDR1_USDHCx_CLK_SEL_SHIFT(x)))
-		clkroot = imxccm_get_pll2_pfd(sc, 0); // 352 MHz
+		clkroot = imxanatop_get_pll2_pfd(0); // 352 MHz
 	else
-		clkroot = imxccm_get_pll2_pfd(sc, 2); // 396 MHz
+		clkroot = imxanatop_get_pll2_pfd(2); // 396 MHz
 
 	return clkroot / (podf + 1);
 }
@@ -408,7 +270,7 @@ imxccm_get_periphclk(struct imxccm_softc *sc)
 		switch((HREAD4(sc, CCM_CBCMR)
 		    >> CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) {
 		case 0:
-			return imxccm_decode_pll(sc, USB1_PLL3, HCLK_FREQ);
+			return imxanatop_decode_pll(USB1_PLL3, HCLK_FREQ);
 		case 1:
 		case 2:
 			return HCLK_FREQ;
@@ -421,13 +283,13 @@ imxccm_get_periphclk(struct imxccm_softc *sc)
 		    >> CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) {
 		default:
 		case 0:
-			return imxccm_decode_pll(sc, SYS_PLL2, HCLK_FREQ);
+			return imxanatop_decode_pll(SYS_PLL2, HCLK_FREQ);
 		case 1:
-			return imxccm_get_pll2_pfd(sc, 2); // 396 MHz
+			return imxanatop_get_pll2_pfd(2); // 396 MHz
 		case 2:
-			return imxccm_get_pll2_pfd(sc, 0); // 352 MHz
+			return imxanatop_get_pll2_pfd(0); // 352 MHz
 		case 3:
-			return imxccm_get_pll2_pfd(sc, 2) / 2; // 198 MHz
+			return imxanatop_get_pll2_pfd(2) / 2; // 198 MHz
 		}
 	}
 }
@@ -483,16 +345,16 @@ imxccm_enable(void *cookie, uint32_t *cells, int on)
 	if (sc->sc_gates == imx6_gates) {
 		switch (idx) {
 		case IMX6_CLK_USBPHY1:
-			imxccm_enable_pll_usb1(sc);
+			imxanatop_enable_pll_usb1();
 			return;
 		case IMX6_CLK_USBPHY2:
-			imxccm_enable_pll_usb2(sc);
+			imxanatop_enable_pll_usb2();
 			return;
 		case IMX6_CLK_SATA_REF_100:
-			imxccm_enable_sata(sc);
+			imxanatop_enable_sata();
 			return;
 		case IMX6_CLK_ENET_REF:
-			imxccm_enable_enet(sc);
+			imxanatop_enable_enet();
 			return;
 		default:
 			break;
@@ -567,53 +429,3 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
 	return 0;
 }
 
-void
-imxccm_enable_pll_enet(struct imxccm_softc *sc)
-{
-	if (HREAD4(sc, CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_ENABLE)
-		return;
-
-	HCLR4(sc, CCM_ANALOG_PLL_ENET, CCM_ANALOG_PLL_ENET_POWERDOWN);
-
-	HSET4(sc, CCM_ANALOG_PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE);
-
-	while(!(HREAD4(sc, CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK));
-
-	HCLR4(sc, CCM_ANALOG_PLL_ENET, CCM_ANALOG_PLL_ENET_BYPASS);
-}
-
-void
-imxccm_enable_enet(struct imxccm_softc *sc)
-{
-	imxccm_enable_pll_enet(sc);
-	HWRITE4(sc, CCM_ANALOG_PLL_ENET_SET, CCM_ANALOG_PLL_ENET_DIV_125M);
-}
-
-void
-imxccm_enable_sata(struct imxccm_softc *sc)
-{
-	imxccm_enable_pll_enet(sc);
-	HWRITE4(sc, CCM_ANALOG_PLL_ENET_SET, CCM_ANALOG_PLL_ENET_100M_SATA);
-}
-
-void
-imxccm_enable_pll_usb1(struct imxccm_softc *sc)
-{
-	HWRITE4(sc, CCM_ANALOG_PLL_USB1_CLR, CCM_ANALOG_PLL_USB1_BYPASS);
-
-	HWRITE4(sc, CCM_ANALOG_PLL_USB1_SET,
-	      CCM_ANALOG_PLL_USB1_ENABLE
-	    | CCM_ANALOG_PLL_USB1_POWER
-	    | CCM_ANALOG_PLL_USB1_EN_USB_CLKS);
-}
-
-void
-imxccm_enable_pll_usb2(struct imxccm_softc *sc)
-{
-	HWRITE4(sc, CCM_ANALOG_PLL_USB2_CLR, CCM_ANALOG_PLL_USB2_BYPASS);
-
-	HWRITE4(sc, CCM_ANALOG_PLL_USB2_SET,
-	      CCM_ANALOG_PLL_USB2_ENABLE
-	    | CCM_ANALOG_PLL_USB2_POWER
-	    | CCM_ANALOG_PLL_USB2_EN_USB_CLKS);
-}