myson mtd803 ether and enable mtdphy no; form netbsd via form@

7 files changed, 1590 insertions, 4 deletions

diff --git a/sys/arch/i386/conf/GENERIC b/sys/arch/i386/conf/GENERIC
index a5ff1695caa..b91db9db2f5 100644
--- a/sys/arch/i386/conf/GENERIC
+++ b/sys/arch/i386/conf/GENERIC
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC,v 1.346 2003/08/12 23:23:56 jason Exp $
+#	$OpenBSD: GENERIC,v 1.347 2003/08/19 03:36:20 mickey Exp $
 #	$NetBSD: GENERIC,v 1.48 1996/05/20 18:17:23 mrg Exp $
 #
 #	GENERIC -- everything that's currently supported
@@ -367,6 +367,7 @@ xl*	at pci? dev ? function ?		# 3C9xx ethernet
 xl*	at cardbus? dev ? function ?		# 3C575/3C656 ethernet
 rl*	at pci? dev ? function ?		# RealTek 81[23]9 ethernet
 rl*	at cardbus? dev ? function ?		# RealTek 81[23]9 ethernet
+mtd*	at pci? dev ? function ?		# Myson MTD803
 tx*	at pci? dev ? function ?		# SMC 83C170 EPIC ethernet
 tl*	at pci? dev ? function ?		# Compaq Thunderlan ethernet
 vr*	at pci? dev ? function ?		# VIA Rhine ethernet
@@ -408,7 +409,7 @@ nsphyter*	at mii? phy ?			# NS and compatible PHYs
 qsphy*	at mii? phy ?				# Quality Semi QS6612 PHYs
 sqphy*	at mii? phy ?				# Seeq 8x220 PHYs
 rlphy* at mii? phy ?				# RealTek 8139 internal PHYs
-#mtdphy*	at mii? phy ?			# Myson MTD972 PHYs
+mtdphy* at mii? phy ?				# Myson MTD972 PHYs
 dcphy*	at mii? phy ?				# Digital Clone PHYs
 acphy*	at mii? phy ?				# Altima AC101 PHYs
 amphy*	at mii? phy ?				# AMD 79C873 PHYs
diff --git a/sys/conf/files b/sys/conf/files
index 73fcb67bb1b..f065928d4f2 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -1,4 +1,4 @@
-#	$OpenBSD: files,v 1.277 2003/08/15 23:01:01 fgsch Exp $
+#	$OpenBSD: files,v 1.278 2003/08/19 03:36:20 mickey Exp $
 #	$NetBSD: files,v 1.87 1996/05/19 17:17:50 jonathan Exp $
 
 #	@(#)files.newconf	7.5 (Berkeley) 5/10/93
@@ -211,6 +211,10 @@ file	dev/ic/xl.c		xl
 device	fxp: ether, ifnet, ifmedia, mii
 file	dev/ic/fxp.c		fxp
 
+# Myson MTD803
+device	mtd: ether, ifnet, ifmedia, mii
+file	dev/ic/mtd803.c		mtd
+
 # RealTek 8129/8139
 device	rl: ether, ifnet, ifmedia, mii
 file	dev/ic/rtl81x9.c	rl
diff --git a/sys/dev/ic/mtd803.c b/sys/dev/ic/mtd803.c
new file mode 100644
index 00000000000..606e9f44c99
--- /dev/null
+++ b/sys/dev/ic/mtd803.c
@@ -0,0 +1,1029 @@
+/* $NetBSD: mtd803.c,v 1.3 2003/07/14 15:47:12 lukem Exp $ */
+
+/*-
+ *
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Peter Bex <Peter.Bex@student.kun.nl>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * TODO:
+ * - Most importantly, get some bus_dmamap_syncs in the correct places.
+ *    I don't have access to a computer with PCI other than i386, and i386
+ *    is just such a machine where dmamap_syncs don't do anything.
+ * - Powerhook for when resuming after standby.
+ * - Watchdog stuff doesn't work yet, the system crashes.(lockmgr: no context)
+ * - There seems to be a CardBus version of the card. (see datasheet)
+ *    Perhaps a detach function is necessary then? (free buffs, stop rx/tx etc)
+ * - When you enable the TXBUN (Tx buffer unavailable) interrupt, it gets
+ *    raised every time a packet is sent. Strange, since everything works anyway
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/mbuf.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+#include <sys/ioctl.h>
+#include <sys/syslog.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#endif
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <machine/bus.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/ic/mtd803reg.h>
+#include <dev/ic/mtd803var.h>
+
+/*
+ * Device driver for the MTD803 3-in-1 Fast Ethernet Controller
+ * Written by Peter Bex (peter.bex@student.kun.nl)
+ *
+ * Datasheet at:   http://www.myson.com.tw   or   http://www.century-semi.com
+ */
+
+#define MTD_READ_1(sc, reg) \
+	bus_space_read_1((sc)->bus_tag, (sc)->bus_handle, (reg))
+#define MTD_WRITE_1(sc, reg, data) \
+	bus_space_write_1((sc)->bus_tag, (sc)->bus_handle, (reg), (data))
+
+#define MTD_READ_2(sc, reg) \
+	bus_space_read_2((sc)->bus_tag, (sc)->bus_handle, (reg))
+#define MTD_WRITE_2(sc, reg, data) \
+	bus_space_write_2((sc)->bus_tag, (sc)->bus_handle, (reg), (data))
+
+#define MTD_READ_4(sc, reg) \
+	bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, (reg))
+#define MTD_WRITE_4(sc, reg, data) \
+	bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, (reg), (data))
+
+#define MTD_SETBIT(sc, reg, x) \
+	MTD_WRITE_4((sc), (reg), MTD_READ_4((sc), (reg)) | (x))
+#define MTD_CLRBIT(sc, reg, x) \
+	MTD_WRITE_4((sc), (reg), MTD_READ_4((sc), (reg)) & ~(x))
+
+#define ETHER_CRC32(buf, len)	(ether_crc32_be((buf), (len)))
+
+int mtd_mii_readreg __P((struct device *, int, int));
+void mtd_mii_writereg __P((struct device *, int, int, int));
+void mtd_mii_statchg __P((struct device *));
+
+void mtd_start __P((struct ifnet *));
+void mtd_stop __P((struct ifnet *, int));
+int mtd_ioctl __P((struct ifnet *, u_long, caddr_t));
+void mtd_setmulti __P((struct mtd_softc *));
+void mtd_watchdog __P((struct ifnet *));
+int mtd_mediachange __P((struct ifnet *));
+void mtd_mediastatus __P((struct ifnet *, struct ifmediareq *));
+
+int mtd_init __P((struct ifnet *));
+void mtd_reset __P((struct mtd_softc *));
+void mtd_shutdown __P((void *));
+int mtd_init_desc __P((struct mtd_softc *));
+int mtd_put __P((struct mtd_softc *, int, struct mbuf *));
+struct mbuf *mtd_get __P((struct mtd_softc *, int, int));
+
+int mtd_rxirq __P((struct mtd_softc *));
+int mtd_txirq __P((struct mtd_softc *));
+int mtd_bufirq __P((struct mtd_softc *));
+
+
+int
+mtd_config(sc)
+	struct mtd_softc *sc;
+{
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	int i;
+
+	/* Read station address */
+	for (i = 0; i < ETHER_ADDR_LEN; ++i)
+		sc->arpcom.ac_enaddr[i] = MTD_READ_1(sc, MTD_PAR0 + i);
+	printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr));
+
+	if (mtd_init_desc(sc))
+		return (1);
+
+	/* Initialize ifnet structure */
+	ifp->if_softc = sc;
+	ifp->if_mtu = ETHERMTU;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = mtd_ioctl;
+	ifp->if_output = ether_output;
+	ifp->if_start = mtd_start;
+	ifp->if_watchdog = mtd_watchdog;
+	ifp->if_baudrate = 10000000;
+	IFQ_SET_READY(&ifp->if_snd);
+	bcopy(sc->dev.dv_xname, ifp->if_xname, IFNAMSIZ);
+
+	/* Setup MII interface */
+	sc->mii.mii_ifp = ifp;
+	sc->mii.mii_readreg = mtd_mii_readreg;
+	sc->mii.mii_writereg = mtd_mii_writereg;
+	sc->mii.mii_statchg = mtd_mii_statchg;
+	ifmedia_init(&sc->mii.mii_media, 0, mtd_mediachange,
+	    mtd_mediastatus);
+	mii_attach(&sc->dev, &sc->mii, 0xffffffff, MII_PHY_ANY,
+	    MII_OFFSET_ANY, 0);
+	if (LIST_FIRST(&sc->mii.mii_phys) == NULL) {
+		ifmedia_add(&sc->mii.mii_media, IFM_ETHER | IFM_NONE, 0,
+		    NULL);
+		ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_NONE);
+	} else
+		ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO);
+
+	/* Attach interface */
+	if_attach(ifp);
+	ether_ifattach(ifp);
+
+	/* Add shutdown hook to reset card when we reboot */
+	sc->sd_hook = shutdownhook_establish(mtd_shutdown, sc);
+
+	return (0);
+}
+
+
+/*
+ * mtd_init
+ * Must be called at splnet()
+ */
+int
+mtd_init(ifp)
+	struct ifnet *ifp;
+{
+	struct mtd_softc *sc = ifp->if_softc;
+
+	mtd_reset(sc);
+
+	/*
+	 * Set cache alignment and burst length. Don't really know what these
+	 * mean, so their values are probably suboptimal.
+	 */
+	MTD_WRITE_4(sc, MTD_BCR, MTD_BCR_BLEN16);
+
+	MTD_WRITE_4(sc, MTD_RXTXR, MTD_TX_STFWD | MTD_RX_BLEN | MTD_RX_512
+			| MTD_TX_FDPLX);
+
+	/* Promiscuous mode? */
+	if (ifp->if_flags & IFF_PROMISC)
+		MTD_SETBIT(sc, MTD_RXTXR, MTD_RX_PROM);
+	else
+		MTD_CLRBIT(sc, MTD_RXTXR, MTD_RX_PROM);
+
+	/* Broadcast mode? */
+	if (ifp->if_flags & IFF_BROADCAST)
+		MTD_SETBIT(sc, MTD_RXTXR, MTD_RX_ABROAD);
+	else
+		MTD_CLRBIT(sc, MTD_RXTXR, MTD_RX_ABROAD);
+
+	mtd_setmulti(sc);
+
+	/* Enable interrupts */
+	MTD_WRITE_4(sc, MTD_IMR, MTD_IMR_MASK);
+	MTD_WRITE_4(sc, MTD_ISR, MTD_ISR_ENABLE);
+
+	/* Set descriptor base addresses */
+	MTD_WRITE_4(sc, MTD_TXLBA, htole32(sc->desc_dma_map->dm_segs[0].ds_addr
+				+ sizeof(struct mtd_desc) * MTD_NUM_RXD));
+	MTD_WRITE_4(sc, MTD_RXLBA,
+		htole32(sc->desc_dma_map->dm_segs[0].ds_addr));
+
+	/* Enable receiver and transmitter */
+	MTD_SETBIT(sc, MTD_RXTXR, MTD_RX_ENABLE);
+	MTD_SETBIT(sc, MTD_RXTXR, MTD_TX_ENABLE);
+
+	/* Interface is running */
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	return 0;
+}
+
+
+int
+mtd_init_desc(sc)
+	struct mtd_softc *sc;
+{
+	int rseg, err, i;
+	bus_dma_segment_t seg;
+	bus_size_t size;
+
+	/* Allocate memory for descriptors */
+	size = (MTD_NUM_RXD + MTD_NUM_TXD) * sizeof(struct mtd_desc);
+
+	/* Allocate DMA-safe memory */
+	if ((err = bus_dmamem_alloc(sc->dma_tag, size, MTD_DMA_ALIGN,
+			 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to allocate DMA buffer, error = %d\n",
+			sc->dev.dv_xname, err);
+		return 1;
+	}
+
+	/* Map memory to kernel addressable space */
+	if ((err = bus_dmamem_map(sc->dma_tag, &seg, 1, size,
+		(caddr_t *)&sc->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
+		printf("%s: unable to map DMA buffer, error = %d\n",
+			sc->dev.dv_xname, err);
+		bus_dmamem_free(sc->dma_tag, &seg, rseg);
+		return 1;
+	}
+
+	/* Create a DMA map */
+	if ((err = bus_dmamap_create(sc->dma_tag, size, 1,
+		size, 0, BUS_DMA_NOWAIT, &sc->desc_dma_map)) != 0) {
+		printf("%s: unable to create DMA map, error = %d\n",
+			sc->dev.dv_xname, err);
+		bus_dmamem_unmap(sc->dma_tag, (caddr_t)sc->desc, size);
+		bus_dmamem_free(sc->dma_tag, &seg, rseg);
+		return 1;
+	}
+
+	/* Load the DMA map */
+	if ((err = bus_dmamap_load(sc->dma_tag, sc->desc_dma_map, sc->desc,
+		size, NULL, BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to load DMA map, error = %d\n",
+			sc->dev.dv_xname, err);
+		bus_dmamap_destroy(sc->dma_tag, sc->desc_dma_map);
+		bus_dmamem_unmap(sc->dma_tag, (caddr_t)sc->desc, size);
+		bus_dmamem_free(sc->dma_tag, &seg, rseg);
+		return 1;
+	}
+
+	/* Allocate memory for the buffers */
+	size = MTD_NUM_RXD * MTD_RXBUF_SIZE + MTD_NUM_TXD * MTD_TXBUF_SIZE;
+
+	/* Allocate DMA-safe memory */
+	if ((err = bus_dmamem_alloc(sc->dma_tag, size, MTD_DMA_ALIGN,
+			 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to allocate DMA buffer, error = %d\n",
+			sc->dev.dv_xname, err);
+
+		/* Undo DMA map for descriptors */
+		bus_dmamap_unload(sc->dma_tag, sc->desc_dma_map);
+		bus_dmamap_destroy(sc->dma_tag, sc->desc_dma_map);
+		bus_dmamem_unmap(sc->dma_tag, (caddr_t)sc->desc, size);
+		bus_dmamem_free(sc->dma_tag, &seg, rseg);
+		return 1;
+	}
+
+	/* Map memory to kernel addressable space */
+	if ((err = bus_dmamem_map(sc->dma_tag, &seg, 1, size,
+		&sc->buf, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
+		printf("%s: unable to map DMA buffer, error = %d\n",
+			sc->dev.dv_xname, err);
+		bus_dmamem_free(sc->dma_tag, &seg, rseg);
+
+		/* Undo DMA map for descriptors */
+		bus_dmamap_unload(sc->dma_tag, sc->desc_dma_map);
+		bus_dmamap_destroy(sc->dma_tag, sc->desc_dma_map);
+		bus_dmamem_unmap(sc->dma_tag, (caddr_t)sc->desc, size);
+		bus_dmamem_free(sc->dma_tag, &seg, rseg);
+		return 1;
+	}
+
+	/* Create a DMA map */
+	if ((err = bus_dmamap_create(sc->dma_tag, size, 1,
+		size, 0, BUS_DMA_NOWAIT, &sc->buf_dma_map)) != 0) {
+		printf("%s: unable to create DMA map, error = %d\n",
+			sc->dev.dv_xname, err);
+		bus_dmamem_unmap(sc->dma_tag, sc->buf, size);
+		bus_dmamem_free(sc->dma_tag, &seg, rseg);
+
+		/* Undo DMA map for descriptors */
+		bus_dmamap_unload(sc->dma_tag, sc->desc_dma_map);
+		bus_dmamap_destroy(sc->dma_tag, sc->desc_dma_map);
+		bus_dmamem_unmap(sc->dma_tag, (caddr_t)sc->desc, size);
+		bus_dmamem_free(sc->dma_tag, &seg, rseg);
+		return 1;
+	}
+
+	/* Load the DMA map */
+	if ((err = bus_dmamap_load(sc->dma_tag, sc->buf_dma_map, sc->buf,
+		size, NULL, BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to load DMA map, error = %d\n",
+			sc->dev.dv_xname, err);
+		bus_dmamap_destroy(sc->dma_tag, sc->buf_dma_map);
+		bus_dmamem_unmap(sc->dma_tag, sc->buf, size);
+		bus_dmamem_free(sc->dma_tag, &seg, rseg);
+
+		/* Undo DMA map for descriptors */
+		bus_dmamap_unload(sc->dma_tag, sc->desc_dma_map);
+		bus_dmamap_destroy(sc->dma_tag, sc->desc_dma_map);
+		bus_dmamem_unmap(sc->dma_tag, (caddr_t)sc->desc, size);
+		bus_dmamem_free(sc->dma_tag, &seg, rseg);
+		return 1;
+	}
+
+	/* Descriptors are stored as a circular linked list */
+	/* Fill in rx descriptors */
+	for (i = 0; i < MTD_NUM_RXD; ++i) {
+		sc->desc[i].stat = MTD_RXD_OWNER;
+		if (i == MTD_NUM_RXD - 1) {	/* Last descriptor */
+			/* Link back to first rx descriptor */
+			sc->desc[i].next =
+				htole32(sc->desc_dma_map->dm_segs[0].ds_addr);
+		} else {
+			/* Link forward to next rx descriptor */
+			sc->desc[i].next =
+			htole32(sc->desc_dma_map->dm_segs[0].ds_addr
+					+ (i + 1) * sizeof(struct mtd_desc));
+		}
+		sc->desc[i].conf = MTD_RXBUF_SIZE & MTD_RXD_CONF_BUFS;
+		/* Set buffer's address */
+		sc->desc[i].data = htole32(sc->buf_dma_map->dm_segs[0].ds_addr
+					+ i * MTD_RXBUF_SIZE);
+	}
+
+	/* Fill in tx descriptors */
+	for (/* i = MTD_NUM_RXD */; i < (MTD_NUM_TXD + MTD_NUM_RXD); ++i) {
+		sc->desc[i].stat = 0;	/* At least, NOT MTD_TXD_OWNER! */
+		if (i == (MTD_NUM_RXD + MTD_NUM_TXD - 1)) {	/* Last descr */
+			/* Link back to first tx descriptor */
+			sc->desc[i].next =
+				htole32(sc->desc_dma_map->dm_segs[0].ds_addr
+					+MTD_NUM_RXD * sizeof(struct mtd_desc));
+		} else {
+			/* Link forward to next tx descriptor */
+			sc->desc[i].next =
+				htole32(sc->desc_dma_map->dm_segs[0].ds_addr
+					+ (i + 1) * sizeof(struct mtd_desc));
+		}
+		/* sc->desc[i].conf = MTD_TXBUF_SIZE & MTD_TXD_CONF_BUFS; */
+		/* Set buffer's address */
+		sc->desc[i].data = htole32(sc->buf_dma_map->dm_segs[0].ds_addr
+					+ MTD_NUM_RXD * MTD_RXBUF_SIZE
+					+ (i - MTD_NUM_RXD) * MTD_TXBUF_SIZE);
+	}
+
+	return 0;
+}
+
+
+void
+mtd_mii_statchg(self)
+	struct device *self;
+{
+	/*struct mtd_softc *sc = (void *)self;*/
+
+	/* Should we do something here? :) */
+}
+
+
+int
+mtd_mii_readreg(self, phy, reg)
+	struct device *self;
+	int phy, reg;
+{
+	struct mtd_softc *sc = (void *)self;
+
+	/* XXX */
+	if (phy != 0)
+		return (0);
+
+	return (MTD_READ_2(sc, MTD_PHYBASE + reg * 2));
+}
+
+
+void
+mtd_mii_writereg(self, phy, reg, val)
+	struct device *self;
+	int phy, reg, val;
+{
+	struct mtd_softc *sc = (void *)self;
+
+	MTD_WRITE_2(sc, MTD_PHYBASE + reg * 2, val);
+}
+
+
+int
+mtd_put(sc, index, m)
+	struct mtd_softc *sc;
+	int index;
+	struct mbuf *m;
+{
+	int len, tlen;
+	caddr_t buf = sc->buf + MTD_NUM_RXD * MTD_RXBUF_SIZE
+			+ index * MTD_TXBUF_SIZE;
+	struct mbuf *n;
+
+	for (tlen = 0; m != NULL; m = n) {
+		len = m->m_len;
+		if (len == 0) {
+			MFREE(m, n);
+			continue;
+		} else if (tlen > MTD_TXBUF_SIZE) {
+			/* XXX FIXME: No idea what to do here. */
+			printf("%s: packet too large!\n",
+				sc->dev.dv_xname);
+			MFREE(m, n);
+			continue;
+		}
+		memcpy(buf, mtod(m, caddr_t), len);
+		buf += len;
+		tlen += len;
+		MFREE(m, n);
+	}
+	sc->desc[MTD_NUM_RXD + index].conf = MTD_TXD_CONF_PAD | MTD_TXD_CONF_CRC
+		| MTD_TXD_CONF_IRQC
+		| ((tlen << MTD_TXD_PKTS_SHIFT) & MTD_TXD_CONF_PKTS)
+		| (tlen & MTD_TXD_CONF_BUFS);
+
+	return tlen;
+}
+
+
+void
+mtd_start(ifp)
+	struct ifnet *ifp;
+{
+	struct mtd_softc *sc = ifp->if_softc;
+	struct mbuf *m;
+	int len;
+	int first_tx = sc->cur_tx;
+
+	for (;;) {
+		IFQ_DEQUEUE(&ifp->if_snd, m);
+
+		if (m == NULL)
+			break;
+
+#if NBPFILTER > 0
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m);
+#endif
+
+		/* Copy mbuf chain into tx buffer */
+		len = mtd_put(sc, sc->cur_tx, m);
+
+		if (sc->cur_tx != first_tx)
+			sc->desc[MTD_NUM_RXD + sc->cur_tx].stat = MTD_TXD_OWNER;
+
+		if (++sc->cur_tx >= MTD_NUM_TXD)
+			sc->cur_tx = 0;
+	}
+	/* Mark first & last descriptor */
+	sc->desc[MTD_NUM_RXD + first_tx].conf |= MTD_TXD_CONF_FSD;
+
+	if (sc->cur_tx == 0) {
+		sc->desc[MTD_NUM_RXD + MTD_NUM_TXD - 1].conf |=MTD_TXD_CONF_LSD;
+	} else {
+		sc->desc[MTD_NUM_RXD + sc->cur_tx - 1].conf |= MTD_TXD_CONF_LSD;
+	}
+
+	/* Give first descriptor to chip to complete transaction */
+	sc->desc[MTD_NUM_RXD + first_tx].stat = MTD_TXD_OWNER;
+
+	/* Transmit polling demand */
+	MTD_WRITE_4(sc, MTD_TXPDR, MTD_TXPDR_DEMAND);
+
+	/* XXX FIXME: Set up a watchdog timer */
+	/* ifp->if_timer = 5; */
+}
+
+
+void
+mtd_stop (ifp, disable)
+	struct ifnet *ifp;
+	int disable;
+{
+	struct mtd_softc *sc = ifp->if_softc;
+
+	/* Disable transmitter and receiver */
+	MTD_CLRBIT(sc, MTD_RXTXR, MTD_TX_ENABLE);
+	MTD_CLRBIT(sc, MTD_RXTXR, MTD_RX_ENABLE);
+
+	/* Disable interrupts */
+	MTD_WRITE_4(sc, MTD_IMR, 0x00000000);
+
+	/* Must do more at disable??... */
+	if (disable) {
+		/* Delete tx and rx descriptor base adresses */
+		MTD_WRITE_4(sc, MTD_RXLBA, 0x00000000);
+		MTD_WRITE_4(sc, MTD_TXLBA, 0x00000000);
+	}
+
+	ifp->if_timer = 0;
+	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+}
+
+
+void
+mtd_watchdog(ifp)
+	struct ifnet *ifp;
+{
+	struct mtd_softc *sc = ifp->if_softc;
+	int s;
+
+	log(LOG_ERR, "%s: device timeout\n", sc->dev.dv_xname);
+	++sc->arpcom.ac_if.if_oerrors;
+
+	mtd_stop(ifp, 0);
+
+	s = splnet();
+	mtd_init(ifp);
+	splx(s);
+
+	return;
+}
+
+
+int
+mtd_ioctl(ifp, cmd, data)
+	struct ifnet * ifp;
+	u_long cmd;
+	caddr_t data;
+{
+	struct mtd_softc *sc = ifp->if_softc;
+	struct ifreq *ifr = (struct ifreq *)data;
+	struct ifaddr *ifa = (struct ifaddr *)data;
+	int s, error = 0;
+
+	s = splimp();
+	if ((error = ether_ioctl(ifp, &sc->arpcom, cmd, data)) > 0) {
+		splx(s);
+		return (error);
+	}
+
+	/* Don't do anything special */
+	switch(cmd) {
+	case SIOCSIFADDR:
+		ifp->if_flags |= IFF_UP;
+		switch (ifa->ifa_addr->sa_family) {
+#ifdef INET
+		case AF_INET:
+			mtd_init(ifp);
+			arp_ifinit(&sc->arpcom, ifa);
+			break;
+#endif	/* INET */
+		default:
+			mtd_init(ifp);
+			break;
+		}
+		break;
+	case SIOCSIFMTU:
+		if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) {
+			error = EINVAL;
+		} else if (ifp->if_mtu != ifr->ifr_mtu) {
+			ifp->if_mtu = ifr->ifr_mtu;
+		}
+		break;
+	case SIOCSIFFLAGS:
+		if (ifp->if_flags & IFF_UP)
+			mtd_init(ifp);
+		else
+			if (ifp->if_flags & IFF_RUNNING)
+				/* mtd_stop(ifp) */;
+		error = 0;
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		error = (cmd == SIOCADDMULTI) ?
+		    ether_addmulti(ifr, &sc->arpcom) :
+		    ether_delmulti(ifr, &sc->arpcom);
+
+		if (error == ENETRESET) {
+			/*
+			 * Multicast list has changed; set the hardware
+			 * filter accordingly.
+			 */
+			mtd_setmulti(sc);
+			 error = 0;
+		}
+		break;
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, cmd);
+		break;
+	default:
+		error = EINVAL;
+		break;
+	}
+
+	splx(s);
+	return error;
+}
+
+
+struct mbuf *
+mtd_get(sc, index, totlen)
+	struct mtd_softc *sc;
+	int index;
+	int totlen;
+{
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	struct mbuf *m, *m0, *newm;
+	int len;
+	caddr_t buf = sc->buf + index * MTD_RXBUF_SIZE;
+
+	MGETHDR(m0, M_DONTWAIT, MT_DATA);
+	if (m0 == NULL)
+		return NULL;
+
+	m0->m_pkthdr.rcvif = ifp;
+	m0->m_pkthdr.len = totlen;
+	m = m0;
+	len = MHLEN;
+
+	while (totlen > 0) {
+		if (totlen >= MINCLSIZE) {
+			MCLGET(m, M_DONTWAIT);
+			if (!(m->m_flags & M_EXT)) {
+				m_freem(m0);
+				return NULL;
+			}
+			len = MCLBYTES;
+		}
+
+		if (m == m0) {
+			caddr_t newdata = (caddr_t)
+				ALIGN(m->m_data + sizeof(struct ether_header)) -
+				sizeof(struct ether_header);
+			len -= newdata - m->m_data;
+			m->m_data = newdata;
+		}
+
+		m->m_len = len = min(totlen, len);
+		memcpy(mtod(m, caddr_t), buf, len);
+		buf += len;
+
+		totlen -= len;
+		if (totlen > 0) {
+			MGET(newm, M_DONTWAIT, MT_DATA);
+			if (newm == NULL) {
+				m_freem(m0);
+				return NULL;
+			}
+			len = MLEN;
+			m = m->m_next = newm;
+		}
+	}
+
+	return m0;
+}
+
+
+int
+mtd_rxirq(sc)
+	struct mtd_softc *sc;
+{
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	int len;
+	struct mbuf *m;
+
+	for (; !(sc->desc[sc->cur_rx].stat & MTD_RXD_OWNER);) {
+		/* Error summary set? */
+		if (sc->desc[sc->cur_rx].stat & MTD_RXD_ERRSUM) {
+			printf("%s: received packet with errors\n",
+				sc->dev.dv_xname); 
+			/* Give up packet, since an error occurred */
+			sc->desc[sc->cur_rx].stat = MTD_RXD_OWNER;
+			sc->desc[sc->cur_rx].conf = MTD_RXBUF_SIZE &
+							MTD_RXD_CONF_BUFS;
+			++ifp->if_ierrors;
+			if (++sc->cur_rx >= MTD_NUM_RXD)
+				sc->cur_rx = 0;
+			continue;
+		}
+		/* Get buffer length */
+		len = (sc->desc[sc->cur_rx].stat & MTD_RXD_FLEN)
+			>> MTD_RXD_FLEN_SHIFT;
+		len -= ETHER_CRC_LEN;
+
+		/* Check packet size */
+		if (len <= sizeof(struct ether_header)) { 
+			printf("%s: invalid packet size %d; dropping\n",
+				sc->dev.dv_xname, len);
+			sc->desc[sc->cur_rx].stat = MTD_RXD_OWNER;
+			sc->desc[sc->cur_rx].conf = MTD_RXBUF_SIZE &
+							MTD_RXD_CONF_BUFS;
+			++ifp->if_ierrors;
+			if (++sc->cur_rx >= MTD_NUM_RXD)
+				sc->cur_rx = 0;
+			continue;
+		}
+
+		m = mtd_get(sc, (sc->cur_rx), len);
+
+		/* Give descriptor back to card */
+		sc->desc[sc->cur_rx].conf = MTD_RXBUF_SIZE & MTD_RXD_CONF_BUFS;
+		sc->desc[sc->cur_rx].stat = MTD_RXD_OWNER;
+
+		if (++sc->cur_rx >= MTD_NUM_RXD)
+			sc->cur_rx = 0;
+
+		if (m == NULL) {
+			printf("%s: error pulling packet off interface\n",
+				sc->dev.dv_xname);
+			++ifp->if_ierrors;
+			continue;
+		}
+
+		++ifp->if_ipackets;
+
+#if NBPFILTER > 0
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m);
+#endif
+		/* Pass the packet up */
+		ether_input_mbuf(ifp, m);
+	}
+
+	return 1;
+}
+
+
+int
+mtd_txirq(sc)
+	struct mtd_softc *sc;
+{
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+
+	/* Clear timeout */
+	ifp->if_timer = 0;
+
+	ifp->if_flags &= ~IFF_OACTIVE;
+	++ifp->if_opackets;
+
+	/* XXX FIXME If there is some queued, do an mtd_start? */
+
+	return 1;
+}
+
+
+int
+mtd_bufirq(sc)
+	struct mtd_softc *sc;
+{
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	
+	/* Clear timeout */
+	ifp->if_timer = 0;
+
+	/* XXX FIXME: Do something here to make sure we get some buffers! */
+
+	return 1;
+}
+
+
+int
+mtd_irq_h(args)
+	void *args;
+{
+	struct mtd_softc *sc = args;
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	u_int32_t status;
+	int r = 0;
+
+	if (!(ifp->if_flags & IFF_RUNNING) ||
+		!(sc->dev.dv_flags & DVF_ACTIVE))
+		return 0;
+
+	/* Disable interrupts */
+	MTD_WRITE_4(sc, MTD_IMR, 0x00000000);
+
+	for(;;) {
+		status = MTD_READ_4(sc, MTD_ISR);
+		if (!status)		/* We didn't ask for this */
+			break;
+
+		MTD_WRITE_4(sc, MTD_ISR, status);
+
+		/* NOTE: Perhaps we should reset with some of these errors? */
+
+		if (status & MTD_ISR_RXBUN) {
+#ifdef MTD_DEBUG
+			printf("%s: receive buffer unavailable\n",
+			    sc->dev.dv_xname);
+#endif
+			++ifp->if_ierrors;
+		}
+
+		if (status & MTD_ISR_RXERR) {
+#ifdef MTD_DEBUG
+			printf("%s: receive error\n", sc->dev.dv_xname);
+#endif
+			++ifp->if_ierrors;
+		}
+
+		if (status & MTD_ISR_TXBUN) {
+#ifdef MTD_DEBUG
+			printf("%s: transmit buffer unavailable\n",
+			    sc->dev.dv_xname);
+#endif
+			++ifp->if_ierrors;
+		}
+
+		if ((status & MTD_ISR_PDF)) {
+#ifdef MTD_DEBUG
+			printf("%s: parallel detection fault\n",
+			    sc->dev.dv_xname);
+#endif
+			++ifp->if_ierrors;
+		}
+
+		if (status & MTD_ISR_FBUSERR) {
+#ifdef MTD_DEBUG
+			printf("%s: fatal bus error\n", sc->dev.dv_xname);
+#endif
+			++ifp->if_ierrors;
+		}
+
+		if (status & MTD_ISR_TARERR) {
+#ifdef MTD_DEBUG
+			printf("%s: target error\n", sc->dev.dv_xname);
+#endif
+			++ifp->if_ierrors;
+		}
+
+		if (status & MTD_ISR_MASTERR) {
+#ifdef MTD_DEBUG
+			printf("%s: master error\n", sc->dev.dv_xname);
+#endif
+			++ifp->if_ierrors;
+		}
+
+		if (status & MTD_ISR_PARERR) {
+#ifdef MTD_DEBUG
+			printf("%s: parity error\n", sc->dev.dv_xname);
+#endif
+			++ifp->if_ierrors;
+		}
+
+		if (status & MTD_ISR_RXIRQ)	/* Receive interrupt */
+			r |= mtd_rxirq(sc);
+
+		if (status & MTD_ISR_TXIRQ)	/* Transmit interrupt */
+			r |= mtd_txirq(sc);
+
+		if (status & MTD_ISR_TXEARLY)	/* Transmit early */
+			r |= mtd_txirq(sc);
+
+		if (status & MTD_ISR_TXBUN)	/* Transmit buffer n/a */
+			r |= mtd_bufirq(sc);
+
+	}
+
+	/* Enable interrupts */
+	MTD_WRITE_4(sc, MTD_IMR, MTD_IMR_MASK);
+
+	return r;
+}
+
+
+void
+mtd_setmulti(sc)
+	struct mtd_softc *sc;
+{
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	u_int32_t rxtx_stat;
+	u_int32_t hash[2] = {0, 0};
+	u_int32_t crc;
+	struct ether_multi *enm;
+	struct ether_multistep step;
+	int mcnt = 0;
+
+	/* Get old status */
+	rxtx_stat = MTD_READ_4(sc, MTD_RXTXR);
+
+	if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
+		rxtx_stat |= MTD_RX_AMULTI;
+		MTD_WRITE_4(sc, MTD_RXTXR, rxtx_stat);
+		MTD_WRITE_4(sc, MTD_MAR0, MTD_ALL_ADDR);
+		MTD_WRITE_4(sc, MTD_MAR1, MTD_ALL_ADDR);
+		return;
+	}
+
+	ETHER_FIRST_MULTI(step, &sc->arpcom, enm);
+	while (enm != NULL) {
+		/* We need the 6 most significant bits of the CRC */
+		crc = ETHER_CRC32(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26;
+
+		hash[crc >> 5] |= 1 << (crc & 0xf);
+
+		++mcnt;
+		ETHER_NEXT_MULTI(step, enm);
+	}
+
+	/* Accept multicast bit needs to be on? */
+	if (mcnt)
+		rxtx_stat |= MTD_RX_AMULTI;
+	else
+		rxtx_stat &= ~MTD_RX_AMULTI;
+
+	/* Write out the hash */
+	MTD_WRITE_4(sc, MTD_MAR0, hash[0]);
+	MTD_WRITE_4(sc, MTD_MAR1, hash[1]);
+	MTD_WRITE_4(sc, MTD_RXTXR, rxtx_stat);
+}
+
+
+void
+mtd_reset(sc)
+	struct mtd_softc *sc;
+{
+	int i;
+
+	MTD_SETBIT(sc, MTD_BCR, MTD_BCR_RESET);
+
+	/* Reset descriptor status */
+	sc->cur_tx = 0;
+	sc->cur_rx = 0;
+
+	/* Wait until done with reset */
+	for (i = 0; i < MTD_TIMEOUT; ++i) {
+		DELAY(10);
+		if (!(MTD_READ_4(sc, MTD_BCR) & MTD_BCR_RESET))
+			break;
+	}
+
+	if (i == MTD_TIMEOUT) {
+		printf("%s: reset timed out\n", sc->dev.dv_xname);
+	}
+
+	/* Wait a little so chip can stabilize */
+	DELAY(1000);
+}
+
+
+int
+mtd_mediachange(ifp)
+	struct ifnet *ifp;
+{
+	struct mtd_softc *sc = ifp->if_softc;
+
+	return (mii_mediachg(&sc->mii));
+}
+
+
+void
+mtd_mediastatus(ifp, ifmr)
+	struct ifnet *ifp;
+	struct ifmediareq *ifmr;
+{
+	struct mtd_softc *sc = ifp->if_softc;
+
+	mii_pollstat(&sc->mii);
+	ifmr->ifm_active = sc->mii.mii_media_active;
+	ifmr->ifm_status = sc->mii.mii_media_status;
+}
+
+
+void
+mtd_shutdown (arg)
+	void *arg;
+{
+	struct mtd_softc *sc = arg;
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+
+	mtd_stop(ifp, 1);
+}
+
+struct cfdriver mtd_cd = {
+	0, "mtd", DV_IFNET
+};
diff --git a/sys/dev/ic/mtd803reg.h b/sys/dev/ic/mtd803reg.h
new file mode 100644
index 00000000000..0ec684af036
--- /dev/null
+++ b/sys/dev/ic/mtd803reg.h
@@ -0,0 +1,281 @@
+/* $NetBSD: mtd803reg.h,v 1.1 2002/11/07 21:56:59 martin Exp $ */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Peter Bex <Peter.Bex@student.kun.nl>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __DEV_IC_MTD803REG_H__
+#define __DEV_IC_MTD803REG_H__
+
+#define MTD_PCI_LOIO		0x10
+#define MTD_PCI_LOMEM		0x14
+
+/* Command and Status Register */
+#define MTD_PAR0		0x00		/* Physical address 0-3 */
+#define MTD_PAR1		0x04		/* Physical address 4-5 */
+#define MTD_MAR0		0x08		/* Multicast address 0-3 */
+#define MTD_MAR1		0x0c		/* Multicast address 4-7 */
+#define MTD_FAR0		0x10		/* Flowctrl address 0-3 */
+#define MTD_FAR1		0x14		/* Flowctrl address 4-5 */
+#define MTD_RXTXR		0x18		/* Receive-transmit config */
+#define MTD_BCR			0x1c		/* Bus command */
+#define MTD_TXPDR		0x20		/* Transmit polling demand */
+#define MTD_RXPDR		0x24		/* Receive polling demand */
+#define MTD_RCWP		0x28		/* Receive word pointer */
+#define MTD_TXLBA		0x2c		/* Transmit list base addr */
+#define MTD_RXLBA		0x30		/* Receive list base addr */
+#define MTD_ISR			0x34		/* Interrupt Status Register */
+#define MTD_IMR			0x38		/* Interrupt Mask Register */
+#define MTD_FHLT		0x3c		/* Flow ctrl high/low thresh */
+#define MTD_MIIMGT		0x40		/* ROM and MII management */
+#define MTD_TALLY		0x44		/* Tally ctr for CRC & MPA */
+#define MTD_TSR			0x48		/* Tally ctr for TSR */
+#define MTD_PHYBASE		0x4c		/* PHY status & control */
+#define MTD_OUI			0x50		/* OUI register */
+#define MTD_LPAR		0x54		/* Link Partner, Advertisment */
+#define MTD_WUECSR		0x5c		/* Wake-up Events CSR */
+
+#define MTD_ALL_ADDR		0xffffffff	/* Mask all addresses */
+#define MTD_TXPDR_DEMAND	0xffffffff	/* Demand transmit polling */
+#define MTD_RXPDR_DEMAND	0xffffffff	/* Demand receive polling */
+
+/* PHY registers */
+/* Basic mode control register */
+#define MTD_PHY_BMCR		0x00
+
+/* Bus Command Register */
+#define MTD_BCR_RSRVD1		0xfffffc00	/* Bits [31:10] are reserved */
+#define MTD_BCR_PROG		0x00000200	/* Programming */
+#define MTD_BCR_RLE		0x00000100	/* Read Line command Enable */
+#define MTD_BCR_RME		0x00000080	/* Read Multiple cmd Enable */
+#define MTD_BCR_WIE		0x00000040	/* Write and Inval. cmd Enab. */
+#define MTD_BCR_BLEN1		0x00000000	/* 1 dword burst length */
+#define MTD_BCR_BLEN4		0x00000008	/* 4 dwords burst length */
+#define MTD_BCR_BLEN8		0x00000010	/* 8 dwords burst length */
+#define MTD_BCR_BLEN16		0x00000018	/* 16 dwords burst length */
+#define MTD_BCR_BLEN32		0x00000020	/* 32 dwords burst length */
+#define MTD_BCR_BLEN64		0x00000028	/* 64 dwords burst length */
+#define MTD_BCR_BLEN128		0x00000030	/* 128 dwords burst length */
+#define MTD_BCR_BLEN512		0x00000038	/* 512 dwords burst length */
+#define MTD_BCR_RSVRD0		0x00000006	/* Bits [2:1] are reserved */
+#define MTD_BCR_RESET		0x00000001	/* Software reset */
+
+#define MTD_TIMEOUT		1000		/* Timeout when resetting */
+
+/* Transmit configuration register */
+#define MTD_TX_RUN		0x80000000	/* Transmit running status */
+#define MTD_TX_RSRVD1		0x60000000	/* Bits [14:13] are reserved */
+#define MTD_TX_BACKOPT		0x10000000	/* Optional backoff */
+#define MTD_TX_FASTBACK		0x08000000	/* Fast back-off */
+#define MTD_TX_RSRVD0		0x04000000	/* Bit 10 is reserved */
+#define MTD_TX_ENH		0x02000000	/* Enhanced mode */
+#define MTD_TX_FCTL		0x01000000	/* Transmit fctl packet enable*/
+#define MTD_TX_64		0x00000000	/* 64 bytes */
+#define MTD_TX_32		0x00200000	/* 32 bytes */
+#define MTD_TX_128		0x00400000	/* 128 bytes */
+#define MTD_TX_256		0x00600000	/* 256 bytes */
+#define MTD_TX_512		0x00800000	/* 512 bytes */
+#define MTD_TX_768		0x00a00000	/* 768 bytes */
+#define MTD_TX_1024		0x00c00000	/* 1024 bytes */
+#define MTD_TX_STFWD		0x00e00000	/* Store and forward */
+#define MTD_TX_FDPLX		0x00100000	/* Full duplex mode */
+#define MTD_TX_SPD10		0x00080000	/* Port speed is 10M */
+#define MTD_TX_ENABLE		0x00040000	/* Transmit enable */
+#define MTD_TX_LPBACK		0x00020000	/* Loopback mode bit 1 */
+#define MTD_TX_LPBACKZERO	0x00010000	/* Loopback mode bit 0 */
+
+/* Receive configuration register */
+#define MTD_RX_RUN		0x00008000	/* Receive running status */
+#define MTD_RX_EARLY		0x00004000	/* Early interrupt enable */
+#define MTD_RX_FCTL		0x00002000	/* Receive fctl packet enable */
+#define MTD_RX_FANA		0x00001000	/* Fctl address undefined(n/a)*/
+#define MTD_RX_BLEN		0x00000800	/* Receive burst len enable */
+#define MTD_RX_512		0x00000700	/* 512 words */
+#define MTD_RX_128		0x00000600	/* 128 words */
+#define MTD_RX_64		0x00000500	/* 64 words */
+#define MTD_RX_32		0x00000400	/* 32 words */
+#define MTD_RX_16		0x00000300	/* 16 words */
+#define MTD_RX_8		0x00000200	/* 8 words */
+#define MTD_RX_4		0x00000100	/* 4 words */
+#define MTD_RX_1		0x00000000	/* 1 word */
+#define MTD_RX_PROM		0x00000080	/* Promiscuous mode */
+#define MTD_RX_ABROAD		0x00000040	/* Accept broadcast */
+#define MTD_RX_AMULTI		0x00000020	/* Accept multicast */
+#define MTD_RX_ARP		0x00000008	/* Receive runt packet */
+#define MTD_RX_ALP		0x00000004	/* Receive long packet */
+#define MTD_RX_ERRP		0x00000002	/* Receive error packet */
+#define MTD_RX_ENABLE		0x00000001	/* Receive enable */
+
+/* Interrupt Status Register */
+#define MTD_ISR_RSRVD1		0xfff80000	/* Bits [31:19] are reserved */
+#define MTD_ISR_PDF		0x00040000	/* Parallel Detection Fault */
+#define MTD_ISR_RFCON		0x00020000	/* Receive FCtl xON packet */
+#define MRD_ISR_RFCOFF		0x00010000	/* Receive FCtl xOFF packet */
+#define MTD_ISR_LSC		0x00008000	/* Link Status Change */
+#define MTD_ISR_ANC		0x00004000	/* Autonegotiation complete */
+#define MTD_ISR_FBUSERR		0x00002000	/* Fatal bus error */
+#define MTD_ISR_PARERR		0x00000000	/* Parity error */
+#define MTD_ISR_MASTERR		0x00000800	/* Master error */
+#define MTD_ISR_TARERR		0x00001000	/* Target error */
+#define MTD_ISR_TXUNDER		0x00000400	/* Transmit underflow */
+#define MTD_ISR_RXOVER		0x00000200	/* Receive overflow */
+#define MTD_ISR_TXEARLY		0x00000100	/* Transmit early int */
+#define MTD_ISR_RXEARLY		0x00000080	/* Receive early int */
+#define MTD_ISR_CTROVER		0x00000040	/* Counter overflow */
+#define MTD_ISR_RXBUN		0x00000020	/* Receive buffer n/a */
+#define MTD_ISR_TXBUN		0x00000010	/* Transmit buffer n/a */
+#define MTD_ISR_TXIRQ		0x00000008	/* Transmit interrupt */
+#define MTD_ISR_RXIRQ		0x00000004	/* Receive interrupt */
+#define MTD_ISR_RXERR		0x00000002	/* Receive error */
+#define MTD_ISR_RSRVD0		0x00000001	/* Bit 1 is reserved */
+
+#define MTD_ISR_MASK		MTD_ISR_TXIRQ | MTD_ISR_RXIRQ | MTD_ISR_RXBUN \
+				| MTD_ISR_RXERR | MTD_ISR_PDF \
+				| MTD_ISR_FBUSERR | MTD_ISR_TXUNDER \
+				| MTD_ISR_RXOVER | MTD_ISR_PARERR \
+				| MTD_ISR_MASTERR | MTD_ISR_TARERR
+
+#define MTD_ISR_ENABLE		0xffffffff	/* Enable interrupts */
+
+/* Interrupt Mask Register. Essentially the same as ISR */
+#define MTD_IMR_RSRVD2		0xfff80000	/* Bits [31:19] are reserved */
+#define MTD_IMR_PDF		0x00040000	/* Parallel Detection Fault */
+#define MTD_IMR_RFCON		0x00020000	/* Receive FCtl xON packet */
+#define MRD_IMR_RFCOFF		0x00010000	/* Receive FCtl xOFF packet */
+#define MTD_IMR_LSC		0x00008000	/* Link Status Change */
+#define MTD_IMR_ANC		0x00004000	/* Autonegotiation complete */
+#define MTD_IMR_FBUSERR		0x00002000	/* Fatal bus error */
+#define MTD_IMR_RSRVD1		0x00001800	/* Bits [12:11] are reserved */
+#define MTD_IMR_TXUNDER		0x00000400	/* Transmit underflow */
+#define MTD_IMR_RXOVER		0x00000200	/* Receive overflow */
+#define MTD_IMR_TXEARLY		0x00000100	/* Transmit early int */
+#define MTD_IMR_RXEARLY		0x00000080	/* Receive early int */
+#define MTD_IMR_CTROVER		0x00000040	/* Counter overflow */
+#define MTD_IMR_RXBUN		0x00000020	/* Receive buffer n/a */
+#define MTD_IMR_TXBUN		0x00000010	/* Transmit buffer n/a */
+#define MTD_IMR_TXIRQ		0x00000008	/* Transmit interrupt */
+#define MTD_IMR_RXIRQ		0x00000004	/* Receive interrupt */
+#define MTD_IMR_RXERR		0x00000002	/* Receive error */
+#define MTD_IMR_RSRVD0		0x00000001	/* Bit 1 is reserved */
+
+#define MTD_IMR_MASK		MTD_IMR_TXIRQ | MTD_IMR_RXIRQ | MTD_IMR_RXBUN \
+				| MTD_IMR_RXERR | MTD_IMR_PDF \
+				| MTD_IMR_FBUSERR | MTD_IMR_TXUNDER \
+				| MTD_IMR_RXOVER \
+
+/* Tally counters for CRC and MPA */
+#define MTD_TALLY_CRCOVER	0x80000000	/* CRC tally ctr overflow */
+#define MTD_TALLY_NCRCERR	0x7fff0000	/* Number of CRC errors */
+#define MTD_TALLY_MPAOVER	0x00008000	/* MPA tally ctr overflow */
+#define MTD_TALLY_NMPAERR	0x00007fff	/* Number of MPA errors */
+
+/* Tally counters for Transmit Status Report */
+#define MTD_TSR_NABORT		0xff000000	/* Number of aborted packets */
+#define MTD_TSR_NLCOL		0x00ff0000	/* Number of late collisions */
+#define MTD_TSR_NRETRY		0x0000ffff	/* Number of transm. retries */
+
+/* Wake-Up Events Control and Status Register */
+#define MTD_WUECSR_RSRVD1	0xfffff000	/* Bits [31:12] are reserved */
+#define MTD_WUECSR_FRCWKUP	0x00000800	/* Force Wake Up LAN mode */
+#define MTD_WUECSR_STATCHG	0x00000400	/* Status Change enable */
+#define MTD_WUECSR_AGU		0x00000200	/* Accept Global Unicast */
+#define MTD_WUECSR_WUPOP	0x00000100	/* Wake Up Pin Output Pattern */
+#define MTD_WUECSR_WUPPROP	0x00000080	/* Wake Up Pin Property */
+#define MTD_WUECSR_LCD		0x00000040	/* Link Change Detected */
+#define MTD_WUECSR_MPR		0x00000020	/* Magic Packet Received */
+#define MTD_WUECSR_WUFR		0x00000010	/* Wake Up Frame Received */
+#define MTD_WUECSR_RSRVD0	0x00000008	/* Unspecified! */
+#define MTD_WUECSR_LCE		0x00000004	/* Link Change Enable */
+#define MTD_WUECSR_MPE		0x00000002	/* Magic Packet Enable */
+#define MTD_WUECSR_WUFE		0x00000001	/* Wake Up Frame Enable */
+
+
+/*
+ * Note: We should probably move the following info to a new PHY driver.
+ * Or maybe remove them anyway, but we might need them someday so leave them
+ *  here for now.
+ */
+/* PHY Control and Status Register */
+#define MTD_PHY_T4		0x80000000	/* T4 operation capability */
+#define MTD_PHY_TXFD		0x40000000	/* 100-TX Full Duplex cap. */
+#define MTD_PHY_TXHD		0x20000000	/* 100-TX Half Duplex cap. */
+#define MTD_PHY_TPFD		0x10000000	/* 10-TP Full Duplex cap. */
+#define MTD_PHY_TPHD		0x08000000	/* 10-TP Half Duplex cap. */
+#define MTD_PHY_RSRVD2		0x07c00000	/* Bits [16:22] are reserved */
+#define MTD_PHY_ANC		0x00200000	/* Autonegotiation complete */
+#define MTD_PHY_RMTFAULT	0x00100000	/* Remote fault */
+#define MTD_PHY_AUTONEG		0x00080000	/* Autonegotiation */
+#define MTD_PHY_LINK		0x00040000	/* Link status */
+#define MTD_PHY_JABBER		0x00020000	/* Jabber detected */
+#define MTD_PHY_EXTREG		0x00010000	/* Extended register exists */
+#define MTD_PHY_RESET		0x00008000	/* Reset PHY registers */
+#define MTD_PHY_LPBACK		0x00004000	/* Loopback select */
+#define MTD_PHY_SPEED		0x00002000	/* Speed select */
+#define MTD_PHY_ANEN		0x00001000	/* Autoneg enable */
+#define MTD_PHY_POWDWN		0x00000800	/* Power-down */
+#define MTD_PHY_RSRVD1		0x00000400	/* Bit 10 is reserved */
+#define MTD_PHY_RESTAN		0x00000200	/* Restart Autoneg */
+#define MTD_PHY_DUPLEX		0x00000100	/* Duplex select */
+#define MTD_PHY_COLTST		0x00000080	/* Collision test enable */
+#define MTD_PHY_RSRVD0		0x0000007f	/* Bits [6:0] are reserved */
+
+/* OUI register */
+#define MTD_OUI_HIGH		0xfc000000	/* OUI High register (0x34) */
+#define MTD_OUI_PARTNO		0x02f00000	/* Part number (0x0) */
+#define MTD_OUI_REVISION	0x000f0000	/* Revision number (0x0) */
+#define MTD_OUI_LOW		0x0000ffff	/* OUI Low register (0x0302) */
+
+/* Link Partner Ability Register and Advertisment Register */
+#define MTD_LPAR_LP_NEXTPAGE	0x80000000	/* Next page */
+#define MTD_LPAR_LP_ACK		0x40000000	/* Acknowledge */
+#define MTD_LPAR_LP_RMTFAULT	0x20000000	/* Remote fault detected */
+#define MTD_LPAR_RSRVD1		0x1c000000	/* Bits [28:26] are reserved */
+#define MTD_LPAR_LP_T4		0x02000000	/* Capable of T4 operation */
+#define MTD_LPAR_LP_TXFD	0x01000000	/* Cap. of 100-TX Full Duplex */
+#define MTD_LPAR_LP_TXHD	0x00800000	/* Cap. of 100-TX Half Duplex */
+#define MTD_LPAR_LP_TPFD	0x00400000	/* Cap. of 10-TP Full Duplex */
+#define MTD_LPAR_LP_TPHD	0x00200000	/* Cap. of 10-TP Half Duplex */
+#define MTD_LPAR_SELECTOR1	0x001f0000	/* Selector field 1 */
+#define MTD_LPAR_AD_NEXTPAGE	0x00008000	/* Next page */
+#define MTD_LPAR_AD_ACK		0x00004000	/* Acknowledge */
+#define MTD_LPAR_AD_RMTFAULT	0x00002000	/* Remote fault detected */
+#define MTD_LPAR_RSRVD0		0x00001c00	/* Bits [12:10] are reserved */
+#define MTD_LPAR_AD_T4		0x00000200	/* Capable of T4 operation */
+#define MTD_LPAR_AD_TXFD	0x00000100	/* Cap. of 100-TX Full Duplex */
+#define MTD_LPAR_AD_TXHD	0x00000080	/* Cap. of 100-TX Half Duplex */
+#define MTD_LPAR_AD_TPFD	0x00000040	/* Cap. of 10-TP Full Duplex */
+#define MTD_LPAR_AD_TPHD	0x00000020	/* Cap. of 10-TP Half Duplex */
+#define MTD_LPAR_SELECTOR0	0x0000001f	/* Selector field 0 */
+
+#endif	/* __DEV_IC_MTD803REG_H__ */
diff --git a/sys/dev/ic/mtd803var.h b/sys/dev/ic/mtd803var.h
new file mode 100644
index 00000000000..5d84ee3e41d
--- /dev/null
+++ b/sys/dev/ic/mtd803var.h
@@ -0,0 +1,135 @@
+/* $NetBSD: mtd803var.h,v 1.1 2002/11/07 21:57:00 martin Exp $ */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Peter Bex <Peter.Bex@student.kun.nl>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DEV_IC_MTD803VAR_H__
+#define __DEV_IC_MTD803VAR_H__
+
+#include <dev/mii/miivar.h>
+
+/* Number of Tx and Rx descriptors */
+#define MTD_NUM_TXD		128
+#define MTD_NUM_RXD		128
+/* Tx and Rx buffer size */
+#define MTD_RXBUF_SIZE		768
+#define MTD_TXBUF_SIZE		768
+
+/* DMA mem must be longword (4 bytes) aligned */
+#define MTD_DMA_ALIGN		4
+
+
+/* Descriptor structure */
+struct mtd_desc {
+	u_int32_t stat;			/* Status field */
+	u_int32_t conf;			/* Config field */
+	u_int32_t data;			/* Data buffer start address */
+	u_int32_t next;			/* Next descriptor address */
+};
+
+/* Softc struct */
+struct mtd_softc {
+	struct device		dev;
+	struct mii_data		mii;
+	struct arpcom		arpcom;
+	bus_space_tag_t		bus_tag;
+	bus_space_handle_t	bus_handle;
+	void *			sd_hook;
+	volatile unsigned int	cur_tx;
+	volatile unsigned int	cur_rx;
+
+	bus_dma_tag_t		dma_tag;
+	struct mtd_desc *	desc;
+	bus_dmamap_t		desc_dma_map;
+	caddr_t			buf;
+	bus_dmamap_t		buf_dma_map;
+};
+
+
+/* Transmit descriptor layout */
+	/* Status register */
+#define MTD_TXD_OWNER		0x80000000	/* Owner bit */
+#define MTD_TXD_RSRVD0		0x7fffc000	/* Bits [30:14] are reserved */
+#define MTD_TXD_ABORT		0x00002000	/* Transmit aborted */
+#define MTD_TXD_CSL		0x00001000	/* Carrier Sense Loss */
+#define MTD_TXD_LCOL		0x00000800	/* Late collision */
+#define MTD_TXD_EXCOL		0x00000400	/* Excessive collisions */
+#define MTD_TXD_DFD		0x00000200	/* Deferred */
+#define MTD_TXD_HBFAIL		0x00000100	/* Heart-beat failure */
+#define MTD_TXD_NRC		0x000000ff	/* Collision Retry Count */
+	/* Configuration register */
+#define MTD_TXD_CONF_IRQC	0x80000000	/* Interrupt control */
+#define MTD_TXD_CONF_EIRQC	0x40000000	/* Early interrupt control */
+#define MTD_TXD_CONF_LSD	0x20000000	/* Last descriptor */
+#define MTD_TXD_CONF_FSD	0x10000000	/* First descriptor */
+#define MTD_TXD_CONF_CRC	0x08000000	/* CRC append */
+#define MTD_TXD_CONF_PAD	0x04000000	/* Pad control */
+#define MTD_TXD_CONF_RLCOL	0x02000000	/* Retry Late Collision */
+#define MTD_TXD_CONF_RSRVD0	0x01c00000	/* Bits [24:22] are reserved */
+#define MTD_TXD_CONF_PKTS	0x003ff800	/* Packet size */
+#define MTD_TXD_CONF_BUFS	0x000007ff	/* Transmit buffer size */
+
+#define MTD_TXD_PKTS_SHIFT	11
+
+/* Receive descriptor layout */
+	/* Status register */
+#define MTD_RXD_OWNER		0x80000000	/* Owner bit */
+#define MTD_RXD_RSRVD3		0x70000000	/* Bits [30:28] are reserved */
+#define MTD_RXD_FLEN		0x0fff0000	/* Frame length */
+#define MTD_RXD_RSRVD2		0x00008000	/* Bit 15 is reserved */
+#define MTD_RXD_MAR		0x00004000	/* Multicast Address Received */
+#define MTD_RXD_BAR		0x00002000	/* Broadcast Address Received */
+#define MTD_RXD_PAR		0x00001000	/* Physical Address Received */
+#define MTD_RXD_FSD		0x00000800	/* First Descriptor */
+#define MTD_RXD_LSD		0x00000400	/* Last Descriptor */
+#define MTD_RXD_RSRVD1		0x00000300	/* Bits [9:8] are reserved */
+#define MTD_RXD_ERRSUM		0x00000080	/* Error summary */
+#define MTD_RXD_RUNT		0x00000040	/* Runt packet received */
+#define MTD_RXD_LONG		0x00000020	/* Long packet received */
+#define MTD_RXD_FALERR		0x00000010	/* Frame alignment error */
+#define MTD_RXD_CRC		0x00000008	/* CRC error. See manual :) */
+#define MTD_RXD_RXERR		0x00000004	/* Receive error */
+#define MTD_RXD_RSRVD0		0x00000003	/* Bits [1:0] are reserved */
+	/* Configuration register */
+#define MTD_RXD_CONF_RSRVD0	0xfffffc00	/* Bits [31:11] are reserved */
+#define MTD_RXD_CONF_BUFS	0x000003ff	/* Receive buffer size */
+
+#define MTD_RXD_FLEN_SHIFT	16
+
+extern int mtd_config __P((struct mtd_softc *));
+extern int mtd_irq_h __P((void *));
+
+#endif	/* __DEV_IC_MTD803VAR_H__ */
diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci
index c95dd4effa3..68d66ccd9b3 100644
--- a/sys/dev/pci/files.pci
+++ b/sys/dev/pci/files.pci
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.pci,v 1.148 2003/08/12 18:48:13 jason Exp $
+#	$OpenBSD: files.pci,v 1.149 2003/08/19 03:36:21 mickey Exp $
 #	$NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $
 #
 # Config file and device description for machine-independent PCI code.
@@ -228,6 +228,10 @@ file	dev/pci/if_lmc_common.c		lmc
 file	dev/pci/if_lmc_media.c		lmc
 file	dev/pci/if_lmc_obsd.c		lmc
 
+# Myson Century MTD800/MTD803/MTD891
+attach	mtd at pci with mtd_pci
+file	dev/pci/if_mtd_pci.c		mtd_pci
+
 # RealTek 8129/8139
 attach	rl at pci with rl_pci
 file	dev/pci/if_rl_pci.c		rl_pci
diff --git a/sys/dev/pci/if_mtd_pci.c b/sys/dev/pci/if_mtd_pci.c
new file mode 100644
index 00000000000..ba2bd0d189c
--- /dev/null
+++ b/sys/dev/pci/if_mtd_pci.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2003 Oleg Safiullin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+#include <sys/socket.h>
+#include <net/if.h>
+#include <net/if_media.h>
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+#endif
+#include <machine/bus.h>
+#include <dev/mii/miivar.h>
+#include <dev/pci/pcidevs.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/ic/mtd803reg.h>
+#include <dev/ic/mtd803var.h>
+
+static int mtd_pci_match(struct device *, void *, void *);
+static void mtd_pci_attach(struct device *, struct device *, void *);
+
+struct cfattach mtd_pci_ca = {
+	sizeof(struct mtd_softc), mtd_pci_match, mtd_pci_attach
+};
+
+const static struct pci_matchid mtd_pci_devices[] = {
+	{ PCI_VENDOR_MYSON, PCI_PRODUCT_MYSON_MTD803 },
+};
+
+static int
+mtd_pci_match(struct device *parent, void *match, void *aux)
+{
+	return (pci_matchbyid((struct pci_attach_args *)aux, mtd_pci_devices,
+	    sizeof(mtd_pci_devices) / sizeof(mtd_pci_devices[0])));
+}
+
+static void
+mtd_pci_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct mtd_softc *sc = (void *)self;
+	struct pci_attach_args *pa = aux;
+	pci_intr_handle_t ih;
+	const char *intrstr = NULL;
+	bus_addr_t iobase;
+	bus_size_t iosize;
+	u_int32_t command;
+
+	command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
+
+#ifdef MTD_USE_MEMIO
+	if (!(command & PCI_COMMAND_MEM_ENABLE)) {
+		printf(": failed to enable memory mapping\n");
+		return;
+	}
+	if (pci_mem_find(pa->pa_pc, pa->pa_tag, MTD_PCI_LOMEM, &iobase,
+	    &iosize, NULL)) {
+		printf(": can't find mem space\n");
+		return;
+	}
+	if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->bus_handle)) {
+		printf(": can't map mem space\n");
+		return;
+	}
+	sc->bus_tag = pa->pa_memt;
+#else	/* !MTD_USE_MEMIO */
+	if (!(command & PCI_COMMAND_IO_ENABLE)) {
+		printf(": failed to enable i/o ports\n");
+		return;
+	}
+
+	if (pci_io_find(pa->pa_pc, pa->pa_tag, MTD_PCI_LOIO, &iobase,
+	    &iosize)) {
+		printf(": can't find i/o space\n");
+		return;
+	}
+	if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->bus_handle)) {
+		printf(": can't map i/o space\n");
+		return;
+	}
+	sc->bus_tag = pa->pa_iot;
+#endif	/* MTD_USE_MEMIO */
+
+	/*
+	 * Allocate our interrupt.
+	 */
+	if (pci_intr_map(pa, &ih)) {
+		printf(": couldn't map interrupt\n");
+		return;
+	}
+
+	intrstr = pci_intr_string(pa->pa_pc, ih);
+	if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, mtd_irq_h, sc,
+	    self->dv_xname) == NULL) {
+		printf(": couldn't establish interrupt");
+		if (intrstr != NULL)
+			printf(" at %s", intrstr);
+		printf("\n");
+		return;
+	}
+	printf(": %s", intrstr);
+
+	sc->dma_tag = pa->pa_dmat;
+	mtd_config(sc);
+}