Add Trident 9750

3 files changed, 44 insertions, 37 deletions

diff --git a/sys/arch/i386/isa/pcvt/Util/scon/scon.c b/sys/arch/i386/isa/pcvt/Util/scon/scon.c
index 8577347cf33..d22756c5442 100644
--- a/sys/arch/i386/isa/pcvt/Util/scon/scon.c
+++ b/sys/arch/i386/isa/pcvt/Util/scon/scon.c
@@ -640,6 +640,7 @@ char *vga_type(int number)
 		"TVGA 9200",
 		"TVGA 9440",
 		"TVGA 9660",
+		"TVGA 9750 (3DImage)",
 		"Unknown TRIDENT",
 		"S3 80C911",
 		"S3 80C924",
diff --git a/sys/arch/i386/isa/pcvt/pcvt_ext.c b/sys/arch/i386/isa/pcvt/pcvt_ext.c
index 6730ccd2a3e..c9a89c09bf3 100644
--- a/sys/arch/i386/isa/pcvt/pcvt_ext.c
+++ b/sys/arch/i386/isa/pcvt/pcvt_ext.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pcvt_ext.c,v 1.16 1998/07/19 10:47:53 downsj Exp $	*/
+/*	$OpenBSD: pcvt_ext.c,v 1.17 1998/09/28 03:00:27 downsj Exp $	*/
 
 /*
  * Copyright (c) 1992, 1995 Hellmuth Michaelis and Joerg Wunsch.
@@ -123,6 +123,7 @@ static int regsaved = 0;	/* registers are saved to savearea */
  *	###############################################################
  *
  *---------------------------------------------------------------------------*/
+
 u_char
 vga_chipset(void)
 {
@@ -273,6 +274,9 @@ vga_chipset(void)
 				can_do_132col = 1;
 				return(VGA_TR9660);
 
+			case 0xf3:
+				return(VGA_TR9750);
+
 			default:
 				return(VGA_TRUNKNOWN);
 		}
@@ -642,6 +646,7 @@ vga_string(int number)
 		"TVGA 9200",
 		"TVGA 9440",
 		"TVGA 9660",
+		"TVGA 9750 (3DImage)",
 		"unknown Trident",
 		"S3 911",
 		"S3 924",
diff --git a/sys/arch/i386/isa/pcvt/pcvt_ioctl.h b/sys/arch/i386/isa/pcvt/pcvt_ioctl.h
index cc6bb8602f0..2348053a54a 100644
--- a/sys/arch/i386/isa/pcvt/pcvt_ioctl.h
+++ b/sys/arch/i386/isa/pcvt/pcvt_ioctl.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pcvt_ioctl.h,v 1.9 1998/05/29 00:41:05 mickey Exp $	*/
+/*	$OpenBSD: pcvt_ioctl.h,v 1.10 1998/09/28 03:00:28 downsj Exp $	*/
 
 /*
  * Copyright (c) 1992, 1995 Hellmuth Michaelis and Joerg Wunsch.
@@ -255,46 +255,47 @@ struct mousedefs {
 #define VGA_F_TRI	4	/* FAMILY TRIDENT */
 #define VGA_TR8800BR	12	/* Trident TVGA 8800BR */
 #define VGA_TR8800CS	13	/* Trident TVGA 8800CS */
-#define VGA_TR8900B	14	/* Trident TVGA 8900B  */
-#define VGA_TR8900C	15	/* Trident TVGA 8900C  */
+#define VGA_TR8900B	14	/* Trident TVGA 8900B */
+#define VGA_TR8900C	15	/* Trident TVGA 8900C */
 #define VGA_TR8900CL	16	/* Trident TVGA 8900CL */
-#define VGA_TR9000	17	/* Trident TVGA 9000   */
-#define VGA_TR9100	18	/* Trident TVGA 9100   */
-#define VGA_TR9200	19	/* Trident TVGA 9200   */
-#define VGA_TR9440	20	/* Trident TVGA 9440   */
-#define VGA_TR9660	21	/* Trident TVGA 9660   */
-#define VGA_TRUNKNOWN	22	/* Trident unknown     */
+#define VGA_TR9000	17	/* Trident TVGA 9000 */
+#define VGA_TR9100	18	/* Trident TVGA 9100 */
+#define VGA_TR9200	19	/* Trident TVGA 9200 */
+#define VGA_TR9440	20	/* Trident TVGA 9440 */
+#define VGA_TR9660	21	/* Trident TVGA 9660 */
+#define VGA_TR9750	22	/* Trident 3DImage 9750 */
+#define VGA_TRUNKNOWN	23	/* Trident unknown */
 
 #define VGA_F_S3	5	/* FAMILY S3  */
-#define VGA_S3_911	23	/* S3 911 */
-#define VGA_S3_924	24	/* S3 924 */
-#define VGA_S3_80x	25	/* S3 801/805 */
-#define VGA_S3_928	26	/* S3 928 */
-#define	VGA_S3_864	27	/* S3 864 */
-#define	VGA_S3_964	28	/* S3 964 */
-#define	VGA_S3_732	29	/* S3 732 (Trio32) */
-#define	VGA_S3_764	30	/* S3 764 (Trio64) */
-#define	VGA_S3_866	31	/* S3 866 */
-#define VGA_S3_868	32	/* S3 868 */
-#define VGA_S3_968	33	/* S3 968 */
-#define VGA_S3_765	34	/* S3 765 (Trio64 V+) */
-#define VGA_S3_ViRGE	35	/* S3 ViRGE */
-#define VGA_S3_UNKNOWN	36	/* unknown S3 chipset */
+#define VGA_S3_911	24	/* S3 911 */
+#define VGA_S3_924	25	/* S3 924 */
+#define VGA_S3_80x	26	/* S3 801/805 */
+#define VGA_S3_928	27	/* S3 928 */
+#define	VGA_S3_864	28	/* S3 864 */
+#define	VGA_S3_964	29	/* S3 964 */
+#define	VGA_S3_732	30	/* S3 732 (Trio32) */
+#define	VGA_S3_764	31	/* S3 764 (Trio64) */
+#define	VGA_S3_866	32	/* S3 866 */
+#define VGA_S3_868	33	/* S3 868 */
+#define VGA_S3_968	34	/* S3 968 */
+#define VGA_S3_765	35	/* S3 765 (Trio64 V+) */
+#define VGA_S3_ViRGE	36	/* S3 ViRGE */
+#define VGA_S3_UNKNOWN	37	/* unknown S3 chipset */
 
 #define VGA_F_CIR	6	/* FAMILY CIRRUS */
-#define VGA_CL_GD5402	37	/* Cirrus CL-GD5402	*/
-#define VGA_CL_GD5402r1	38	/* Cirrus CL-GD5402r1	*/
-#define VGA_CL_GD5420	39	/* Cirrus CL-GD5420	*/
-#define VGA_CL_GD5420r1	40	/* Cirrus CL-GD5420r1	*/
-#define VGA_CL_GD5422	41	/* Cirrus CL-GD5422	*/
-#define VGA_CL_GD5424	42	/* Cirrus CL-GD5424	*/
-#define VGA_CL_GD5426	43	/* Cirrus CL-GD5426	*/
-#define VGA_CL_GD5428	44	/* Cirrus CL-GD5428	*/
-#define VGA_CL_GD5430	45	/* Cirrus CL-GD543x	*/
-#define	VGA_CL_GD6225	46	/* Cirrus CL-GD62x5	*/
-#define VGA_CL_UNKNOWN	47	/* Unknown Cirrus CL	*/
-
-#define VGA_MAX_CHIPSET	48	/* max no of chips	*/
+#define VGA_CL_GD5402	38	/* Cirrus CL-GD5402	*/
+#define VGA_CL_GD5402r1	39	/* Cirrus CL-GD5402r1	*/
+#define VGA_CL_GD5420	40	/* Cirrus CL-GD5420	*/
+#define VGA_CL_GD5420r1	41	/* Cirrus CL-GD5420r1	*/
+#define VGA_CL_GD5422	42	/* Cirrus CL-GD5422	*/
+#define VGA_CL_GD5424	43	/* Cirrus CL-GD5424	*/
+#define VGA_CL_GD5426	44	/* Cirrus CL-GD5426	*/
+#define VGA_CL_GD5428	45	/* Cirrus CL-GD5428	*/
+#define VGA_CL_GD5430	46	/* Cirrus CL-GD543x	*/
+#define	VGA_CL_GD6225	47	/* Cirrus CL-GD62x5	*/
+#define VGA_CL_UNKNOWN	48	/* Unknown Cirrus CL	*/
+
+#define VGA_MAX_CHIPSET	49	/* max no of chips	*/
 
 /*****************************************************************************/
 /* NOTE: update the 'scon' utility when adding support for more chipsets !!! */