Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY

from FreeBSD

3 files changed, 592 insertions, 1 deletions

diff --git a/sys/dev/mii/files.mii b/sys/dev/mii/files.mii
index 4ddef9a6945..af36b07da82 100644
--- a/sys/dev/mii/files.mii
+++ b/sys/dev/mii/files.mii
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.mii,v 1.20 2003/08/12 19:42:37 mickey Exp $
+#	$OpenBSD: files.mii,v 1.21 2004/06/05 05:49:29 pvalchev Exp $
 #	$NetBSD: files.mii,v 1.13 1998/11/05 00:36:48 thorpej Exp $
 
 file    dev/mii/mii.c				mii
@@ -104,3 +104,7 @@ file dev/mii/nsgphy.c				nsgphy
 device urlphy: mii_phy
 attach urlphy at mii
 file dev/mii/urlphy.c				urlphy
+
+device rgephy: mii_phy
+attach rgephy at mii
+file dev/mii/rgephy.c				rgephy
diff --git a/sys/dev/mii/rgephy.c b/sys/dev/mii/rgephy.c
new file mode 100644
index 00000000000..f44f1b8a1e3
--- /dev/null
+++ b/sys/dev/mii/rgephy.c
@@ -0,0 +1,444 @@
+/*	$OpenBSD: rgephy.c,v 1.1 2004/06/05 05:49:29 pvalchev Exp $	*/
+/*
+ * Copyright (c) 2003
+ *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/socket.h>
+#include <sys/errno.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
+
+#include <dev/mii/rgephyreg.h>
+
+#include <machine/bus.h>
+
+#include <dev/ic/rtl81x9reg.h>
+
+int	rgephymatch(struct device *, void *, void *);
+void	rgephyattach(struct device *, struct device *, void *);
+
+struct cfattach rgephy_ca = {
+	sizeof(struct mii_softc),
+	rgephymatch,
+	rgephyattach,
+	mii_phy_detach,
+	mii_phy_activate
+};
+
+struct cfdriver rgephy_cd = {
+	NULL, "rgephy", DV_DULL
+};
+
+int	rgephy_service(struct mii_softc *, struct mii_data *, int);
+void	rgephy_status(struct mii_softc *);
+int	rgephy_mii_phy_auto(struct mii_softc *);
+void	rgephy_reset(struct mii_softc *);
+void	rgephy_loop(struct mii_softc *);
+void	rgephy_load_dspcode(struct mii_softc *);
+int	rgephy_mii_model;
+
+int
+rgephymatch(parent, match, aux)
+	struct device *parent;
+	void *match;
+	void *aux;
+{
+	struct mii_attach_args *ma = aux;
+
+	if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxREALTEK &&
+	    MII_MODEL(ma->mii_id2) == MII_MODEL_xxREALTEK_RTL8169S) {
+		return(10);
+	}
+
+	return(0);
+}
+
+void
+rgephyattach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct mii_softc *sc = (struct mii_softc *)self;
+	struct mii_attach_args *ma = aux;
+	struct mii_data *mii = ma->mii_data;
+
+	printf(": %s, rev. %d PHY\n", MII_STR_xxREALTEK_RTL8169S,
+	    MII_REV(ma->mii_id2));
+
+	sc->mii_inst = mii->mii_instance;
+	sc->mii_phy = ma->mii_phyno;
+	sc->mii_model = MII_MODEL(ma->mii_id2);
+	sc->mii_rev = MII_REV(ma->mii_id2);
+	sc->mii_service = rgephy_service;
+	sc->mii_status = rgephy_status;
+	sc->mii_pdata = mii;
+	sc->mii_flags = mii->mii_flags | MIIF_NOISOLATE;
+	sc->mii_ticks = 0; /* XXX */
+	sc->mii_anegticks = 5;
+
+	rgephy_reset(sc);
+
+	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
+
+	if (sc->mii_capabilities & BMSR_EXTSTAT)
+		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
+	if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
+	    (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
+		mii_phy_add_media(sc);
+}
+
+int
+rgephy_service(sc, mii, cmd)
+	struct mii_softc *sc;
+	struct mii_data *mii;
+	int cmd;
+{
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+	int reg, speed, gig;
+
+	switch (cmd) {
+	case MII_POLLSTAT:
+		/*
+		 * If we're not polling our PHY instance, just return.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+			return (0);
+		break;
+
+	case MII_MEDIACHG:
+		/*
+		 * If the media indicates a different PHY instance,
+		 * isolate ourselves.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
+			reg = PHY_READ(sc, MII_BMCR);
+			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
+			return (0);
+		}
+
+		/*
+		 * If the interface is not up, don't do anything.
+		 */
+		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+			break;
+
+		rgephy_reset(sc);	/* XXX hardware bug work-around */
+
+		switch (IFM_SUBTYPE(ife->ifm_media)) {
+		case IFM_AUTO:
+#ifdef foo
+			/*
+			 * If we're already in auto mode, just return.
+			 */
+			if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
+				return (0);
+#endif
+			(void) rgephy_mii_phy_auto(sc);
+			break;
+		case IFM_1000_T:
+			speed = RGEPHY_S1000;
+			goto setit;
+		case IFM_100_TX:
+			speed = RGEPHY_S100;
+			goto setit;
+		case IFM_10_T:
+			speed = RGEPHY_S10;
+setit:
+			rgephy_loop(sc);
+			if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
+				speed |= RGEPHY_BMCR_FDX;
+				gig = RGEPHY_1000CTL_AFD;
+			} else {
+				gig = RGEPHY_1000CTL_AHD;
+			}
+
+			PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
+			PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
+			PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
+
+			if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 
+				break;
+
+			PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
+			PHY_WRITE(sc, RGEPHY_MII_BMCR,
+			    speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
+
+			/*
+			 * When settning the link manually, one side must
+			 * be the master and the other the slave. However
+			 * ifmedia doesn't give us a good way to specify
+			 * this, so we fake it by using one of the LINK
+			 * flags. If LINK0 is set, we program the PHY to
+			 * be a master, otherwise it's a slave.
+			 */
+			if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
+				PHY_WRITE(sc, RGEPHY_MII_1000CTL,
+				    gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
+			} else {
+				PHY_WRITE(sc, RGEPHY_MII_1000CTL,
+				    gig|RGEPHY_1000CTL_MSE);
+			}
+			break;
+#ifdef foo
+		case IFM_NONE:
+			PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
+			break;
+#endif
+		case IFM_100_T4:
+		default:
+			return (EINVAL);
+		}
+		break;
+
+	case MII_TICK:
+		/*
+		 * If we're not currently selected, just return.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+			return (0);
+
+		/*
+		 * Is the interface even up?
+		 */
+		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+			return (0);
+
+		/*
+		 * Only used for autonegotiation.
+		 */
+		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
+			break;
+
+		/*
+		 * Check to see if we have link.  If we do, we don't
+		 * need to restart the autonegotiation process.  Read
+		 * the BMSR twice in case it's latched.
+		 */
+		reg = PHY_READ(sc, RL_GMEDIASTAT);
+		if (reg & RL_GMEDIASTAT_LINK)
+			break;
+
+		/*
+		 * Only retry autonegotiation every 5 seconds.
+		 */
+		if (++sc->mii_ticks <= sc->mii_anegticks /*10*/)
+			break;
+		
+		sc->mii_ticks = 0;
+		rgephy_mii_phy_auto(sc);
+		return (0);
+	}
+
+	/* Update the media status. */
+	rgephy_status(sc);
+
+	/*
+	 * Callback if something changed. Note that we need to poke
+	 * the DSP on the RealTek PHYs if the media changes.
+	 *
+	 */
+	if (sc->mii_media_active != mii->mii_media_active || 
+	    sc->mii_media_status != mii->mii_media_status ||
+	    cmd == MII_MEDIACHG) {
+		rgephy_load_dspcode(sc);
+	}
+	mii_phy_update(sc, cmd);
+	return (0);
+}
+
+void
+rgephy_status(sc)
+	struct mii_softc *sc;
+{
+	struct mii_data *mii = sc->mii_pdata;
+	int bmsr, bmcr;
+
+	mii->mii_media_status = IFM_AVALID;
+	mii->mii_media_active = IFM_ETHER;
+
+	bmsr = PHY_READ(sc, RL_GMEDIASTAT);
+
+	if (bmsr & RL_GMEDIASTAT_LINK)
+		mii->mii_media_status |= IFM_ACTIVE;
+	bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
+
+	bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
+
+	if (bmcr & RGEPHY_BMCR_LOOP)
+		mii->mii_media_active |= IFM_LOOP;
+
+	if (bmcr & RGEPHY_BMCR_AUTOEN) {
+		if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
+			/* Erg, still trying, I guess... */
+			mii->mii_media_active |= IFM_NONE;
+			return;
+		}
+	}
+
+	bmsr = PHY_READ(sc, RL_GMEDIASTAT);
+	if (bmsr & RL_GMEDIASTAT_10MBPS)
+		mii->mii_media_active |= IFM_10_T;
+	if (bmsr & RL_GMEDIASTAT_100MBPS)
+		mii->mii_media_active |= IFM_100_TX;
+	if (bmsr & RL_GMEDIASTAT_1000MBPS)
+		mii->mii_media_active |= IFM_1000_T;
+	if (bmsr & RL_GMEDIASTAT_FDX)
+		mii->mii_media_active |= IFM_FDX;
+}
+
+
+int
+rgephy_mii_phy_auto(mii)
+	struct mii_softc *mii;
+{
+	rgephy_loop(mii);
+	rgephy_reset(mii);
+
+	PHY_WRITE(mii, RGEPHY_MII_ANAR,
+	    BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
+	DELAY(1000);
+	PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD);
+	DELAY(1000);
+	PHY_WRITE(mii, RGEPHY_MII_BMCR,
+	    RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
+	DELAY(100);
+
+	return (EJUSTRETURN);
+}
+
+void
+rgephy_loop(struct mii_softc *sc)
+{
+	u_int32_t bmsr;
+	int i;
+
+	PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
+	DELAY(1000);
+
+	for (i = 0; i < 15000; i++) {
+		bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
+		if (!(bmsr & RGEPHY_BMSR_LINK)) {
+#if 0
+			device_printf(sc->mii_dev, "looped %d\n", i);
+#endif
+			break;
+		}
+		DELAY(10);
+	}
+}
+
+#define PHY_SETBIT(x, y, z) \
+	PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
+#define PHY_CLRBIT(x, y, z) \
+	PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
+
+/*
+ * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
+ * existing revisions of the 8169S/8110S chips need to be tuned in
+ * order to reliably negotiate a 1000Mbps link. Later revs of the
+ * chips may not require this software tuning.
+ */
+void
+rgephy_load_dspcode(struct mii_softc *sc)
+{
+	int val;
+
+	PHY_WRITE(sc, 31, 0x0001);
+	PHY_WRITE(sc, 21, 0x1000);
+	PHY_WRITE(sc, 24, 0x65C7);
+	PHY_CLRBIT(sc, 4, 0x0800);
+	val = PHY_READ(sc, 4) & 0xFFF;
+	PHY_WRITE(sc, 4, val);
+	PHY_WRITE(sc, 3, 0x00A1);
+	PHY_WRITE(sc, 2, 0x0008);
+	PHY_WRITE(sc, 1, 0x1020);
+	PHY_WRITE(sc, 0, 0x1000);
+	PHY_SETBIT(sc, 4, 0x0800);
+	PHY_CLRBIT(sc, 4, 0x0800);
+	val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
+	PHY_WRITE(sc, 4, val);
+	PHY_WRITE(sc, 3, 0xFF41);
+	PHY_WRITE(sc, 2, 0xDE60);
+	PHY_WRITE(sc, 1, 0x0140);
+	PHY_WRITE(sc, 0, 0x0077);
+	val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
+	PHY_WRITE(sc, 4, val);
+	PHY_WRITE(sc, 3, 0xDF01);
+	PHY_WRITE(sc, 2, 0xDF20);
+	PHY_WRITE(sc, 1, 0xFF95);
+	PHY_WRITE(sc, 0, 0xFA00);
+	val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
+	PHY_WRITE(sc, 4, val);
+	PHY_WRITE(sc, 3, 0xFF41);
+	PHY_WRITE(sc, 2, 0xDE20);
+	PHY_WRITE(sc, 1, 0x0140);
+	PHY_WRITE(sc, 0, 0x00BB);
+	val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
+	PHY_WRITE(sc, 4, val);
+	PHY_WRITE(sc, 3, 0xDF01);
+	PHY_WRITE(sc, 2, 0xDF20);
+	PHY_WRITE(sc, 1, 0xFF95);
+	PHY_WRITE(sc, 0, 0xBF00);
+	PHY_SETBIT(sc, 4, 0x0800);
+	PHY_CLRBIT(sc, 4, 0x0800);
+	PHY_WRITE(sc, 31, 0x0000);
+	
+	DELAY(40);
+}
+
+void
+rgephy_reset(struct mii_softc *sc)
+{
+	mii_phy_reset(sc);
+	DELAY(1000);
+	rgephy_load_dspcode(sc);
+}
diff --git a/sys/dev/mii/rgephyreg.h b/sys/dev/mii/rgephyreg.h
new file mode 100644
index 00000000000..5c054ead464
--- /dev/null
+++ b/sys/dev/mii/rgephyreg.h
@@ -0,0 +1,143 @@
+/*	$OpenBSD: rgephyreg.h,v 1.1 2004/06/05 05:49:29 pvalchev Exp $	*/
+/*
+ * Copyright (c) 2003
+ *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _DEV_MII_RGEPHYREG_H_
+#define	_DEV_MII_RGEPHYREG_H_
+
+/*
+ * RealTek 8169S/8110S gigE PHY registers
+ */
+
+#define RGEPHY_MII_BMCR		0x00
+#define RGEPHY_BMCR_RESET	0x8000
+#define RGEPHY_BMCR_LOOP	0x4000
+#define RGEPHY_BMCR_SPD0	0x2000	/* speed select, lower bit */
+#define RGEPHY_BMCR_AUTOEN	0x1000	/* Autoneg enabled */
+#define RGEPHY_BMCR_PDOWN	0x0800	/* Power down */
+#define RGEPHY_BMCR_ISO		0x0400	/* Isolate */
+#define RGEPHY_BMCR_STARTNEG	0x0200	/* Restart autoneg */
+#define RGEPHY_BMCR_FDX		0x0100	/* Duplex mode */
+#define RGEPHY_BMCR_CTEST	0x0080	/* Collision test enable */
+#define RGEPHY_BMCR_SPD1	0x0040	/* Speed select, upper bit */
+
+#define RGEPHY_S1000		RGEPHY_BMCR_SPD1	/* 1000mbps */
+#define RGEPHY_S100		RGEPHY_BMCR_SPD0	/* 100mpbs */
+#define RGEPHY_S10		0			/* 10mbps */
+
+#define RGEPHY_MII_BMSR		0x01
+#define RGEPHY_BMSR_100T4	0x8000	/* 100 base T4 capable */
+#define RGEPHY_BMSR_100TXFDX	0x4000	/* 100 base Tx full duplex capable */
+#define RGEPHY_BMSR_100TXHDX	0x2000	/* 100 base Tx half duplex capable */
+#define RGEPHY_BMSR_10TFDX	0x1000	/* 10 base T full duplex capable */
+#define RGEPHY_BMSR_10THDX	0x0800	/* 10 base T half duplex capable */
+#define RGEPHY_BMSR_100T2FDX	0x0400	/* 100 base T2 full duplex capable */
+#define RGEPHY_BMSR_100T2HDX	0x0200	/* 100 base T2 half duplex capable */
+#define RGEPHY_BMSR_EXTSTS	0x0100	/* Extended status present */
+#define RGEPHY_BMSR_PRESUB	0x0040	/* Preamble surpression */
+#define RGEPHY_BMSR_ACOMP	0x0020	/* Autoneg complete */
+#define RGEPHY_BMSR_RFAULT	0x0010	/* Remote fault condition occured */
+#define RGEPHY_BMSR_ANEG	0x0008	/* Autoneg capable */
+#define RGEPHY_BMSR_LINK	0x0004	/* Link status */
+#define RGEPHY_BMSR_JABBER	0x0002	/* Jabber detected */
+#define RGEPHY_BMSR_EXT		0x0001	/* Extended capability */
+
+#define RGEPHY_MII_ANAR		0x04
+#define RGEPHY_ANAR_NP		0x8000	/* Next page */
+#define RGEPHY_ANAR_RF		0x2000	/* Remote fault */
+#define RGEPHY_ANAR_ASP		0x0800	/* Asymmetric Pause */
+#define RGEPHY_ANAR_PC		0x0400	/* Pause capable */
+#define RGEPHY_ANAR_T4		0x0200	/* local device supports 100bT4 */
+#define RGEPHY_ANAR_TX_FD	0x0100	/* local device supports 100bTx FD */
+#define RGEPHY_ANAR_TX		0x0080	/* local device supports 100bTx */
+#define RGEPHY_ANAR_10_FD	0x0040	/* local device supports 10bT FD */
+#define RGEPHY_ANAR_10		0x0020	/* local device supports 10bT */
+#define RGEPHY_ANAR_SEL		0x001F	/* selector field, 00001=Ethernet */
+
+#define RGEPHY_MII_ANLPAR	0x05
+#define RGEPHY_ANLPAR_NP	0x8000	/* Next page */
+#define RGEPHY_ANLPAR_RF	0x2000	/* Remote fault */
+#define RGEPHY_ANLPAR_ASP	0x0800	/* Asymmetric Pause */
+#define RGEPHY_ANLPAR_PC	0x0400	/* Pause capable */
+#define RGEPHY_ANLPAR_T4	0x0200	/* link partner supports 100bT4 */
+#define RGEPHY_ANLPAR_TX_FD	0x0100	/* link partner supports 100bTx FD */
+#define RGEPHY_ANLPAR_TX	0x0080	/* link partner supports 100bTx */
+#define RGEPHY_ANLPAR_10_FD	0x0040	/* link partner supports 10bT FD */
+#define RGEPHY_ANLPAR_10	0x0020	/* link partner supports 10bT */
+#define RGEPHY_ANLPAR_SEL	0x001F	/* selector field, 00001=Ethernet */
+
+#define RGEPHY_SEL_TYPE		0x0001	/* ethernet */
+
+#define RGEPHY_MII_ANER		0x06
+#define RGEPHY_ANER_PDF		0x0010	/* Parallel detection fault */
+#define RGEPHY_ANER_LPNP	0x0008	/* Link partner can next page */
+#define RGEPHY_ANER_NP		0x0004	/* Local PHY can next page */
+#define RGEPHY_ANER_RX		0x0002	/* Next page received */
+#define RGEPHY_ANER_LPAN	0x0001 	/* Link partner autoneg capable */
+
+#define RGEPHY_MII_NEXTP	0x07	/* Next page */
+
+#define RGEPHY_MII_NEXTP_LP	0x08	/* Next page of link partner */
+
+#define RGEPHY_MII_1000CTL	0x09	/* 1000baseT control */
+#define RGEPHY_1000CTL_TST	0xE000	/* test modes */
+#define RGEPHY_1000CTL_MSE	0x1000	/* Master/Slave manual enable */
+#define RGEPHY_1000CTL_MSC	0x0800	/* Master/Slave select */
+#define RGEPHY_1000CTL_RD	0x0400	/* Repeater/DTE */
+#define RGEPHY_1000CTL_AFD	0x0200	/* Advertise full duplex */
+#define RGEPHY_1000CTL_AHD	0x0100	/* Advertise half duplex */
+
+#define RGEPHY_TEST_TX_JITTER			0x2000
+#define RGEPHY_TEST_TX_JITTER_MASTER_MODE	0x4000
+#define RGEPHY_TEST_TX_JITTER_SLAVE_MODE	0x6000
+#define RGEPHY_TEST_TX_DISTORTION		0x8000
+
+#define RGEPHY_MII_1000STS	0x0A	/* 1000baseT status */
+#define RGEPHY_1000STS_MSF	0x8000	/* Master/slave fault */
+#define RGEPHY_1000STS_MSR	0x4000	/* Master/slave result */
+#define RGEPHY_1000STS_LRS	0x2000	/* Local receiver status */
+#define RGEPHY_1000STS_RRS	0x1000	/* Remote receiver status */
+#define RGEPHY_1000STS_LPFD	0x0800	/* Link partner can FD */
+#define RGEPHY_1000STS_LPHD	0x0400	/* Link partner can HD */
+#define RGEPHY_1000STS_IEC	0x00FF	/* Idle error count */
+
+#define RGEPHY_MII_EXTSTS	0x0F	/* Extended status */
+#define RGEPHY_EXTSTS_X_FD_CAP	0x8000	/* 1000base-X FD capable */
+#define RGEPHY_EXTSTS_X_HD_CAP	0x4000	/* 1000base-X HD capable */
+#define RGEPHY_EXTSTS_T_FD_CAP	0x2000	/* 1000base-T FD capable */
+#define RGEPHY_EXTSTS_T_HD_CAP	0x1000	/* 1000base-T HD capable */
+
+
+
+#endif /* _DEV_RGEPHY_MIIREG_H_ */