Add defines for RealTek 8139C+/8169/8169S/8110S; from FreeBSD

1 files changed, 290 insertions, 1 deletions

diff --git a/sys/dev/ic/rtl81x9reg.h b/sys/dev/ic/rtl81x9reg.h
index 587db89b156..693e367d89e 100644
--- a/sys/dev/ic/rtl81x9reg.h
+++ b/sys/dev/ic/rtl81x9reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rtl81x9reg.h,v 1.10 2004/05/19 11:36:59 brad Exp $	*/
+/*	$OpenBSD: rtl81x9reg.h,v 1.11 2004/06/05 06:00:46 pvalchev Exp $	*/
 
 /*
  * Copyright (c) 1997, 1998
@@ -101,15 +101,64 @@
 #define RL_RX_ER	0x0072		/* RX_ER counter */
 #define RL_CSCFG	0x0074		/* CS configuration register */
 
+/*
+ * When operating in special C+ mode, some of the registers in an
+ * 8139C+ chip have different definitions. These are also used for
+ * the 8169 gigE chip.
+ */
+#define RL_DUMPSTATS_LO	0x0010	/* counter dump command register */
+#define RL_DUMPSTATS_HI	0x0014	/* counter dump command register */
+#define RL_TXLIST_ADDR_LO	0x0020	/* 64 bits, 256 byte alignment */
+#define RL_TXLIST_ADDR_HI	0x0024	/* 64 bits, 256 byte alignment */
+#define RL_TXLIST_ADDR_HPRIO_LO	0x0028	/* 64 bits, 256 byte aligned */
+#define RL_TXLIST_ADDR_HPRIO_HI	0x002C	/* 64 bits, 256 byte aligned */
+#define RL_CFG2		0x0053
+#define RL_TIMERINT		0x0054	/* interrupt on timer expire */
+#define RL_TXSTART		0x00D9	/* 8 bits */
+#define RL_CPLUS_CMD		0x00E0	/* 16 bits */
+#define RL_RXLIST_ADDR_LO	0x00E4	/* 64 bits, 256 byte alignment */
+#define RL_RXLIST_ADDR_HI	0x00E8	/* 64 bits, 256 byte alignment */
+#define RL_EARLY_TX_THRESH	0x00EC	/* 8 bits */
 
 /*
+ * Registers specific to the 8169 gigE chip
+ */
+#define RL_TIMERINT_8169	0x0058	/* different offset than 8139 */
+#define RL_PHYAR		0x0060
+#define RL_TBICSR		0x0064
+#define RL_TBI_ANAR		0x0068
+#define RL_TBI_LPAR		0x006A
+#define RL_GMEDIASTAT		0x006C	/* 8 bits */
+#define RL_MAXRXPKTLEN		0x00DA	/* 16 bits, chip multiplies by 8 */
+#define RL_GTXSTART		0x0038	/* 16 bits */
+/*
  * TX config register bits
  */
 #define RL_TXCFG_CLRABRT	0x00000001	/* retransmit aborted pkt */
 #define RL_TXCFG_MAXDMA		0x00000700	/* max DMA burst size */
 #define RL_TXCFG_CRCAPPEND	0x00010000	/* CRC append (0 = yes) */
 #define RL_TXCFG_LOOPBKTST	0x00060000	/* loopback test */
+#define RL_TXCFG_IFG2		0x00080000	/* 8169 only */
 #define RL_TXCFG_IFG		0x03000000	/* interframe gap */
+#define RL_TXCFG_HWREV		0x7CC00000
+
+#define RL_LOOPTEST_OFF		0x00000000
+#define RL_LOOPTEST_ON		0x00020000
+#define RL_LOOPTEST_ON_CPLUS	0x00060000
+
+#define RL_HWREV_8169		0x00000000
+#define RL_HWREV_8169S		0x04000000
+#define RL_HWREV_8110S		0x00800000
+#define RL_HWREV_8139		0x60000000
+#define RL_HWREV_8139A		0x70000000
+#define RL_HWREV_8139AG	0x70800000
+#define RL_HWREV_8139B		0x78000000
+#define RL_HWREV_8130		0x7C000000
+#define RL_HWREV_8139C		0x74000000
+#define RL_HWREV_8139D		0x74400000
+#define RL_HWREV_8139CPLUS	0x74800000
+#define RL_HWREV_8101		0x74c00000
+#define RL_HWREV_8100		0x78800000
 
 #define RL_TXDMA_16BYTES	0x00000000
 #define RL_TXDMA_32BYTES	0x00000100
@@ -143,8 +192,13 @@
 #define RL_ISR_TX_ERR		0x0008
 #define RL_ISR_RX_OVERRUN	0x0010
 #define RL_ISR_PKT_UNDERRUN	0x0020
+#define RL_ISR_LINKCHG		0x0020	/* 8169 only */
 #define RL_ISR_FIFO_OFLOW	0x0040	/* 8139 only */
+#define RL_ISR_TX_DESC_UNAVAIL	0x0080	/* C+ only */
+#define RL_ISR_SWI		0x0100	/* C+ only */
+#define RL_ISR_CABLE_LEN_CHGD	0x2000
 #define RL_ISR_PCS_TIMEOUT	0x4000	/* 8129 only */
+#define RL_ISR_TIMEOUT_EXPIRED	0x4000
 #define RL_ISR_SYSTEM_ERR	0x8000
 
 #define RL_INTRS	\
@@ -152,6 +206,12 @@
 	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
 	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
 
+#define RL_INTRS_CPLUS	\
+	(RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|			\
+	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
+	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
+
+
 /*
  * Media status register. (8139 only)
  */
@@ -247,6 +307,9 @@
 #define RL_EEADDR_LEN0		6	/* 9346 */
 #define RL_EEADDR_LEN1		8	/* 9356 */
 
+#define RL_EECMD_READ_6BIT	0x180	/* XXX  */
+#define RL_EECMD_READ_8BIT	0x600	/* EECMD_READ above maybe wrong? */
+
 #define RL_EE_ID		0x00
 #define RL_EE_PCI_VID		0x01
 #define RL_EE_PCI_DID		0x02
@@ -287,6 +350,66 @@
 #define RL_CFG1_LED1		0x80
 
 /*
+ * 8139C+ register definitions
+ */
+
+/* RL_DUMPSTATS_LO register */
+
+#define RL_DUMPSTATS_START	0x00000008
+
+/* Transmit start register */
+
+#define RL_TXSTART_SWI		0x01	/* generate TX interrupt */
+#define RL_TXSTART_START	0x40	/* start normal queue transmit */
+#define RL_TXSTART_HPRIO_START	0x80	/* start hi prio queue transmit */
+
+/*
+ * Config 2 register, 8139C+/8169/8169S/8110S only
+ */
+#define RL_CFG2_BUSFREQ		0x07
+#define RL_CFG2_BUSWIDTH	0x08
+#define RL_CFG2_AUXPWRSTS	0x10
+
+#define RL_BUSFREQ_33MHZ	0x00
+#define RL_BUSFREQ_66MHZ	0x01
+                                        
+#define RL_BUSWIDTH_32BITS	0x00
+#define RL_BUSWIDTH_64BITS	0x08
+
+/* C+ mode command register */
+
+#define RL_CPLUSCMD_TXENB	0x0001	/* enable C+ transmit mode */
+#define RL_CPLUSCMD_RXENB	0x0002	/* enable C+ receive mode */
+#define RL_CPLUSCMD_PCI_MRW	0x0008	/* enable PCI multi-read/write */
+#define RL_CPLUSCMD_PCI_DAC	0x0010	/* PCI dual-address cycle only */
+#define RL_CPLUSCMD_RXCSUM_ENB	0x0020	/* enable RX checksum offload */
+#define RL_CPLUSCMD_VLANSTRIP	0x0040	/* enable VLAN tag stripping */
+
+/* C+ early transmit threshold */
+
+#define RL_EARLYTXTHRESH_CNT	0x003F	/* byte count times 8 */ 
+
+/*
+ * Gigabit PHY access register (8169 only)
+ */
+
+#define RL_PHYAR_PHYDATA	0x0000FFFF
+#define RL_PHYAR_PHYREG		0x001F0000
+#define RL_PHYAR_BUSY		0x80000000
+
+/*
+ * Gigabit media status (8169 only)
+ */
+#define RL_GMEDIASTAT_FDX	0x01	/* full duplex */
+#define RL_GMEDIASTAT_LINK	0x02	/* link up */
+#define RL_GMEDIASTAT_10MBPS	0x04	/* 10mps link */
+#define RL_GMEDIASTAT_100MBPS	0x08	/* 100mbps link */
+#define RL_GMEDIASTAT_1000MBPS	0x10	/* gigE link */
+#define RL_GMEDIASTAT_RXFLOW	0x20	/* RX flow control on */
+#define RL_GMEDIASTAT_TXFLOW	0x40	/* TX flow control on */
+#define RL_GMEDIASTAT_TBI	0x80	/* TBI enabled */
+
+/*
  * The RealTek doesn't use a fragment-based descriptor mechanism.
  * Instead, there are only four register sets, each or which represents
  * one 'descriptor.' Basically, each TX descriptor is just a contiguous
@@ -324,6 +447,136 @@ struct rl_chain_data {
 	u_int8_t		cur_tx;
 };
 
+
+/*
+ * The 8139C+ and 8160 gigE chips support descriptor-based TX
+ * and RX. In fact, they even support TCP large send. Descriptors
+ * must be allocated in contiguous blocks that are aligned on a
+ * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
+ */
+
+/*
+ * RX/TX descriptor definition. When large send mode is enabled, the
+ * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
+ * the checksum offload bits are disabled. The structure layout is
+ * the same for RX and TX descriptors
+ */
+
+struct rl_desc {
+	u_int32_t		rl_cmdstat;
+	u_int32_t		rl_vlanctl;
+	u_int32_t		rl_bufaddr_lo;
+	u_int32_t		rl_bufaddr_hi;
+};
+
+#define RL_TDESC_CMD_FRAGLEN	0x0000FFFF
+#define RL_TDESC_CMD_TCPCSUM	0x00010000	/* TCP checksum enable */
+#define RL_TDESC_CMD_UDPCSUM	0x00020000	/* UDP checksum enable */
+#define RL_TDESC_CMD_IPCSUM	0x00040000	/* IP header checksum enable */
+#define RL_TDESC_CMD_MSSVAL	0x07FF0000	/* Large send MSS value */
+#define RL_TDESC_CMD_LGSEND	0x08000000	/* TCP large send enb */
+#define RL_TDESC_CMD_EOF	0x10000000	/* end of frame marker */
+#define RL_TDESC_CMD_SOF	0x20000000	/* start of frame marker */
+#define RL_TDESC_CMD_EOR	0x40000000	/* end of ring marker */
+#define RL_TDESC_CMD_OWN	0x80000000	/* chip owns descriptor */
+
+#define RL_TDESC_VLANCTL_TAG	0x00020000	/* Insert VLAN tag */
+#define RL_TDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
+
+/*
+ * Error bits are valid only on the last descriptor of a frame
+ * (i.e. RL_TDESC_CMD_EOF == 1)
+ */
+
+#define RL_TDESC_STAT_COLCNT	0x000F0000	/* collision count */
+#define RL_TDESC_STAT_EXCESSCOL	0x00100000	/* excessive collisions */
+#define RL_TDESC_STAT_LINKFAIL	0x00200000	/* link faulure */
+#define RL_TDESC_STAT_OWINCOL	0x00400000	/* out-of-window collision */
+#define RL_TDESC_STAT_TXERRSUM	0x00800000	/* transmit error summary */
+#define RL_TDESC_STAT_UNDERRUN	0x02000000	/* TX underrun occured */
+#define RL_TDESC_STAT_OWN	0x80000000
+
+/*
+ * RX descriptor cmd/vlan definitions
+ */
+
+#define RL_RDESC_CMD_EOR	0x40000000
+#define RL_RDESC_CMD_OWN	0x80000000
+#define RL_RDESC_CMD_BUFLEN	0x00001FFF
+
+#define RL_RDESC_STAT_OWN	0x80000000
+#define RL_RDESC_STAT_EOR	0x40000000
+#define RL_RDESC_STAT_SOF	0x20000000
+#define RL_RDESC_STAT_EOF	0x10000000
+#define RL_RDESC_STAT_FRALIGN	0x08000000	/* frame alignment error */
+#define RL_RDESC_STAT_MCAST	0x04000000	/* multicast pkt received */
+#define RL_RDESC_STAT_UCAST	0x02000000	/* unicast pkt received */
+#define RL_RDESC_STAT_BCAST	0x01000000	/* broadcast pkt received */
+#define RL_RDESC_STAT_BUFOFLOW	0x00800000	/* out of buffer space */
+#define RL_RDESC_STAT_FIFOOFLOW	0x00400000	/* FIFO overrun */
+#define RL_RDESC_STAT_GIANT	0x00200000	/* pkt > 4096 bytes */
+#define RL_RDESC_STAT_RXERRSUM	0x00100000	/* RX error summary */
+#define RL_RDESC_STAT_RUNT	0x00080000	/* runt packet received */
+#define RL_RDESC_STAT_CRCERR	0x00040000	/* CRC error */
+#define RL_RDESC_STAT_PROTOID	0x00030000	/* Protocol type */
+#define RL_RDESC_STAT_IPSUMBAD	0x00008000	/* IP header checksum bad */
+#define RL_RDESC_STAT_UDPSUMBAD	0x00004000	/* UDP checksum bad */
+#define RL_RDESC_STAT_TCPSUMBAD	0x00002000	/* TCP checksum bad */
+#define RL_RDESC_STAT_FRAGLEN	0x00001FFF	/* RX'ed frame/frag len */
+#define RL_RDESC_STAT_GFRAGLEN	0x00003FFF	/* RX'ed frame/frag len */
+
+#define RL_RDESC_VLANCTL_TAG	0x00010000	/* VLAN tag available
+						   (rl_vlandata valid)*/
+#define RL_RDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
+
+#define RL_PROTOID_NONIP	0x00000000
+#define RL_PROTOID_TCPIP	0x00010000
+#define RL_PROTOID_UDPIP	0x00020000
+#define RL_PROTOID_IP		0x00030000
+#define RL_TCPPKT(x)		(((x) & RL_RDESC_STAT_PROTOID) == \
+				 RL_PROTOID_TCPIP)
+#define RL_UDPPKT(x)		(((x) & RL_RDESC_STAT_PROTOID) == \
+				 RL_PROTOID_UDPIP)
+
+/*
+ * Statistics counter structure (8139C+ and 8169 only)
+ */
+struct rl_stats {
+	u_int32_t		rl_tx_pkts_lo;
+	u_int32_t		rl_tx_pkts_hi;
+	u_int32_t		rl_tx_errs_lo;
+	u_int32_t		rl_tx_errs_hi;
+	u_int32_t		rl_tx_errs;
+	u_int16_t		rl_missed_pkts;
+	u_int16_t		rl_rx_framealign_errs;
+	u_int32_t		rl_tx_onecoll;
+	u_int32_t		rl_tx_multicolls;
+	u_int32_t		rl_rx_ucasts_hi;
+	u_int32_t		rl_rx_ucasts_lo;
+	u_int32_t		rl_rx_bcasts_lo;
+	u_int32_t		rl_rx_bcasts_hi;
+	u_int32_t		rl_rx_mcasts;
+	u_int16_t		rl_tx_aborts;
+	u_int16_t		rl_rx_underruns;
+};
+
+#define RL_RX_DESC_CNT		64
+#define RL_TX_DESC_CNT		64
+#define RL_RX_LIST_SZ		(RL_RX_DESC_CNT * sizeof(struct rl_desc))
+#define RL_TX_LIST_SZ		(RL_TX_DESC_CNT * sizeof(struct rl_desc))
+#define RL_RING_ALIGN		256
+#define RL_IFQ_MAXLEN		512
+#define RL_DESC_INC(x)		(x = (x + 1) % RL_TX_DESC_CNT)
+#define RL_OWN(x)		(letoh32((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
+#define RL_RXBYTES(x)		(letoh32((x)->rl_cmdstat) & sc->rl_rxlenmask)
+#define RL_PKTSZ(x)		((x)/* >> 3*/)
+
+#define RL_ADDR_LO(y)	((u_int64_t) (y) & 0xFFFFFFFF)
+#define RL_ADDR_HI(y)	((u_int64_t) (y) >> 32)
+
+#define RL_JUMBO_FRAMELEN	9018
+#define RL_JUMBO_MTU		(RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
+
 #define RL_INC(x)		(x = (x + 1) % RL_TX_LIST_CNT)
 #define RL_CUR_TXADDR(x)	((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
 #define RL_CUR_TXSTAT(x)	((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
@@ -356,6 +609,28 @@ struct rl_mii_frame {
 
 #define RL_8129			1
 #define RL_8139			2
+#define RL_8139CPLUS		3
+#define RL_8169			4
+
+#define RL_ISCPLUS(x)	((x)->rl_type == RL_8139CPLUS || \
+			 (x)->rl_type == RL_8169)
+
+struct rl_list_data {
+	struct mbuf		*rl_tx_mbuf[RL_TX_DESC_CNT];
+	struct mbuf		*rl_rx_mbuf[RL_RX_DESC_CNT];
+	int			rl_tx_prodidx;
+	int			rl_rx_prodidx;
+	int			rl_tx_considx;
+	int			rl_tx_free;
+	bus_dmamap_t		rl_tx_dmamap[RL_TX_DESC_CNT];
+	bus_dmamap_t		rl_rx_dmamap[RL_RX_DESC_CNT];
+	bus_dmamap_t		rl_rx_list_map;
+	struct rl_desc		*rl_rx_list;
+	bus_dma_segment_t	rl_rx_listseg;
+	bus_dmamap_t		rl_tx_list_map;
+	struct rl_desc		*rl_tx_list;
+	bus_dma_segment_t	rl_tx_listseg;
+};
 
 struct rl_softc {
 	struct device		sc_dev;		/* us, as a device */
@@ -366,13 +641,26 @@ struct rl_softc {
 	struct arpcom		sc_arpcom;		/* interface info */
 	struct mii_data		sc_mii;		/* MII information */
 	u_int8_t		rl_type;
+	int			rl_eecmd_read;
 	void			*sc_sdhook;	/* shutdownhook */
 	void			*sc_pwrhook;
 	int			rl_txthresh;
+	int			sc_flags;	/* misc flags */
 	struct rl_chain_data	rl_cdata;
 	struct timeout		sc_tick_tmo;
+
+	struct rl_list_data	rl_ldata;
+	struct mbuf		*rl_head;
+	struct mbuf		*rl_tail;
+	u_int32_t		rl_rxlenmask;
+	int			rl_testmode;
+	struct timeout		timer_handle;
 };
 
+#define RL_ATTACHED	0x00000001	/* attach has succeeded */
+#define RL_ENABLED	0x00000002	/* chip is enabled      */
+#define RL_IS_ENABLED(sc)	((sc)->sc_flags & RL_ENABLED)
+
 /*
  * register space access macros
  */
@@ -489,3 +777,4 @@ struct rl_softc {
 extern int rl_attach(struct rl_softc *);
 extern int rl_detach(struct rl_softc *);
 extern int rl_intr(void *);
+extern void rl_setmulti(struct rl_softc *);