Add minimal support for gen7/ivy bridge in inteldrm.

Like gen6/sandy bridge this is enough to manage memory but
does not attempt to setup the rings.
ok kettenis@

5 files changed, 76 insertions, 27 deletions

diff --git a/sys/dev/pci/agp_i810.c b/sys/dev/pci/agp_i810.c
index 0c2bc0e97b9..e57ee91afc3 100644
--- a/sys/dev/pci/agp_i810.c
+++ b/sys/dev/pci/agp_i810.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: agp_i810.c,v 1.70 2011/09/14 10:26:16 oga Exp $	*/
+/*	$OpenBSD: agp_i810.c,v 1.71 2012/09/25 10:19:46 jsg Exp $	*/
 
 /*-
  * Copyright (c) 2000 Doug Rabson
@@ -72,6 +72,7 @@ enum {
 	CHIP_PINEVIEW	= 8,	/* Pineview/Pineview M */
 	CHIP_IRONLAKE	= 9,	/* Clarkdale/Arrandale */
 	CHIP_SANDYBRIDGE=10,	/* Sandybridge */
+	CHIP_IVYBRIDGE	=11,	/* Ivybridge */
 };
 
 struct agp_i810_softc {
@@ -201,7 +202,16 @@ agp_i810_get_chiptype(struct pci_attach_args *pa)
 	case PCI_PRODUCT_INTEL_CORE2G_M_GT2_PLUS:
 		return (CHIP_SANDYBRIDGE);
 		break;
+	case PCI_PRODUCT_INTEL_CORE3G_D_GT1:
+	case PCI_PRODUCT_INTEL_CORE3G_M_GT1:
+	case PCI_PRODUCT_INTEL_CORE3G_S_GT1:
+	case PCI_PRODUCT_INTEL_CORE3G_D_GT2:
+	case PCI_PRODUCT_INTEL_CORE3G_M_GT2:
+	case PCI_PRODUCT_INTEL_CORE3G_S_GT2:
+		return (CHIP_IVYBRIDGE);
+		break;
 	}
+	
 	return (CHIP_NONE);
 }
 
@@ -258,6 +268,7 @@ agp_i810_attach(struct device *parent, struct device *self, void *aux)
 	case CHIP_G4X:
 	case CHIP_IRONLAKE:
 	case CHIP_SANDYBRIDGE:
+	case CHIP_IVYBRIDGE:
 		gmaddr = AGP_I965_GMADR;
 		mmaddr = AGP_I965_MMADR;
 		memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT;
@@ -490,6 +501,7 @@ agp_i810_attach(struct device *parent, struct device *self, void *aux)
 		break;
 
 	case CHIP_SANDYBRIDGE:
+	case CHIP_IVYBRIDGE:
 
 		/* Stolen memory is set up at the beginning of the aperture by
 		 * the BIOS, consisting of the GATT followed by 4kb for the
@@ -624,6 +636,7 @@ agp_i810_activate(struct device *arg, int act)
 	case CHIP_G4X:
 	case CHIP_IRONLAKE:
 	case CHIP_SANDYBRIDGE:
+	case CHIP_IVYBRIDGE:
 		offset = AGP_G4X_GTT;
 		break;
 	default:
@@ -937,7 +950,8 @@ intagp_write_gtt(struct agp_i810_softc *isc, bus_size_t off, paddr_t v)
 		    isc->chiptype == CHIP_PINEVIEW ||
 		    isc->chiptype == CHIP_G33 ||
 		    isc->chiptype == CHIP_IRONLAKE ||
-		    isc->chiptype == CHIP_SANDYBRIDGE) {
+		    isc->chiptype == CHIP_SANDYBRIDGE ||
+		    isc->chiptype == CHIP_IVYBRIDGE) {
 			pte |= (v & 0x0000000f00000000ULL) >> 28;
 		}
 	}
@@ -958,6 +972,7 @@ intagp_write_gtt(struct agp_i810_softc *isc, bus_size_t off, paddr_t v)
 	case CHIP_G4X:
 	case CHIP_IRONLAKE:
 	case CHIP_SANDYBRIDGE:
+	case CHIP_IVYBRIDGE:
 		baseoff = AGP_G4X_GTT;
 		break;
 	default:
diff --git a/sys/dev/pci/drm/i915_drv.c b/sys/dev/pci/drm/i915_drv.c
index e73fa152573..394d92fb5d2 100644
--- a/sys/dev/pci/drm/i915_drv.c
+++ b/sys/dev/pci/drm/i915_drv.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: i915_drv.c,v 1.122 2012/05/26 19:30:53 kettenis Exp $ */
+/* $OpenBSD: i915_drv.c,v 1.123 2012/09/25 10:19:46 jsg Exp $ */
 /*
  * Copyright (c) 2008-2009 Owain G. Ainsworth <oga@openbsd.org>
  *
@@ -267,6 +267,18 @@ const static struct drm_pcidev inteldrm_pciidlist[] = {
 	    CHIP_SANDYBRIDGE|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN6},
 	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE2G_M_GT2_PLUS,
 	    CHIP_SANDYBRIDGE|CHIP_M|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN6},
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_D_GT1,
+	    CHIP_IVYBRIDGE|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_M_GT1,
+	    CHIP_IVYBRIDGE|CHIP_M|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_S_GT1,
+	    CHIP_IVYBRIDGE|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_D_GT2,
+	    CHIP_IVYBRIDGE|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_M_GT2,
+	    CHIP_IVYBRIDGE|CHIP_M|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_S_GT2,
+	    CHIP_IVYBRIDGE|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
 	{0, 0, 0}
 };
 
@@ -344,6 +356,8 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
 		dev_priv->gen = 5;
 	else if (dev_priv->flags & CHIP_GEN6)
 		dev_priv->gen = 6;
+	else if (dev_priv->flags & CHIP_GEN7)
+		dev_priv->gen = 7;
 	KASSERT(dev_priv->gen != 0);
 
 	dev_priv->pc = pa->pa_pc;
@@ -442,7 +456,7 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
 		dev_priv->num_fence_regs = 8;
 
 	/* Initialise fences to zero, else on some macs we'll get corruption */
-	if (IS_GEN6(dev_priv)) {
+	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
 		for (i = 0; i < 16; i++)
 			I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
 	} else if (IS_I965G(dev_priv)) {
@@ -683,7 +697,7 @@ inteldrm_ironlake_intr(void *arg)
 	struct inteldrm_softc	*dev_priv = arg;
 	struct drm_device	*dev = (struct drm_device *)dev_priv->drmdev;
 	u_int32_t		 de_iir, gt_iir, de_ier, pch_iir;
-	int			 ret = 0;
+	int			 ret = 0, i;
 
 	de_ier = I915_READ(DEIER);
 	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
@@ -705,10 +719,17 @@ inteldrm_ironlake_intr(void *arg)
 	if (gt_iir & GT_MASTER_ERROR)
 		inteldrm_error(dev_priv);
 
-	if (de_iir & DE_PIPEA_VBLANK)
-		drm_handle_vblank(dev, 0);
-	if (de_iir & DE_PIPEB_VBLANK)
-		drm_handle_vblank(dev, 1);
+	if (IS_GEN7(dev_priv)) {
+		for (i = 0; i < 3; i++) {
+			if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
+				drm_handle_vblank(dev, i);
+		}
+	} else {
+		if (de_iir & DE_PIPEA_VBLANK)
+			drm_handle_vblank(dev, 0);
+		if (de_iir & DE_PIPEB_VBLANK)
+			drm_handle_vblank(dev, 1);
+	}
 
 	/* should clear PCH hotplug event before clearing CPU irq */
 	I915_WRITE(SDEIIR, pch_iir);
@@ -1638,7 +1659,7 @@ i915_add_request(struct inteldrm_softc *dev_priv)
 	if (dev_priv->mm.next_gem_seqno == 0)
 		dev_priv->mm.next_gem_seqno++;
 
-	if (IS_GEN6(dev_priv))
+	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 		BEGIN_LP_RING(10);
 	else 
 		BEGIN_LP_RING(4);
@@ -2392,7 +2413,7 @@ again:
 	reg->obj = obj;
 	TAILQ_INSERT_TAIL(&dev_priv->mm.fence_list, reg, list);
 
-	if (IS_GEN6(dev_priv))
+	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 		sandybridge_write_fence_reg(reg);
 	else if (IS_I965G(dev_priv))
 		i965_write_fence_reg(reg);
@@ -3237,7 +3258,7 @@ i915_dispatch_gem_execbuffer(struct drm_device *dev,
 	} else {
 		BEGIN_LP_RING(4);
 		if (IS_I965G(dev_priv)) {
-			if (IS_GEN6(dev_priv))
+			if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 				OUT_RING(MI_BATCH_BUFFER_START |
 				    MI_BATCH_NON_SECURE_I965);
 			else
@@ -4184,7 +4205,7 @@ inteldrm_start_ring(struct inteldrm_softc *dev_priv)
 	/* Update our cache of the ring state */
 	inteldrm_update_ring(dev_priv);
 
-	if (IS_GEN6(dev_priv))
+	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 		I915_WRITE(MI_MODE | MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE,
 		    (VS_TIMER_DISPATCH) << 15 | VS_TIMER_DISPATCH);
 	else if (IS_I9XX(dev_priv) && !IS_GEN3(dev_priv))
@@ -4218,7 +4239,7 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 	int ret;
 
 	/* XXX until we have support for the rings on sandybridge */
-	if (IS_GEN6(dev_priv))
+	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 		return (0);
 
 	if (dev_priv->mm.wedged) {
@@ -4294,7 +4315,7 @@ inteldrm_error(struct inteldrm_softc *dev_priv)
 	}
 
 	printf("render error detected, EIR: %b\n", eir, errbitstr);
-	if (IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv)) {
+	if (IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
 		if (eir & I915_ERROR_PAGE_TABLE) {
 			dev_priv->mm.wedged = 1;
 			reset = GRDOM_FULL;
@@ -4380,7 +4401,8 @@ inteldrm_error(struct inteldrm_softc *dev_priv)
 		if (dev_priv->mm.wedged == 0)
 			DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 		I915_WRITE(EMR, I915_READ(EMR) | eir);
-		if (IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv)) {
+		if (IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv) ||
+		    IS_GEN7(dev_priv)) {
 			I915_WRITE(GTIIR, GT_MASTER_ERROR);
 		} else {
 			I915_WRITE(IIR,
diff --git a/sys/dev/pci/drm/i915_drv.h b/sys/dev/pci/drm/i915_drv.h
index 49f33b9b201..8c17a67a048 100644
--- a/sys/dev/pci/drm/i915_drv.h
+++ b/sys/dev/pci/drm/i915_drv.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: i915_drv.h,v 1.72 2012/05/26 19:30:53 kettenis Exp $ */
+/* $OpenBSD: i915_drv.h,v 1.73 2012/09/25 10:19:46 jsg Exp $ */
 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  */
 /*
@@ -444,6 +444,8 @@ struct inteldrm_file {
 #define CHIP_IRONLAKE_D	0x400000
 #define CHIP_IRONLAKE_M	0x800000
 #define CHIP_SANDYBRIDGE	0x1000000
+#define CHIP_IVYBRIDGE	0x2000000
+#define CHIP_GEN7	0x4000000
 
 /* flags we use in drm_obj's do_flags */
 #define I915_ACTIVE		0x0010	/* being used by the gpu. */
@@ -639,16 +641,19 @@ read64(struct inteldrm_softc *dev_priv, bus_size_t off)
 
 #define I915_NEED_GFX_HWS(dev_priv) (dev_priv->flags & CHIP_HWS)
 
-#define HAS_RESET(dev_priv)	IS_I965G(dev_priv) && (!IS_GEN6(dev_priv))
+#define HAS_RESET(dev_priv)	IS_I965G(dev_priv) && (!IS_GEN6(dev_priv)) \
+    && (!IS_GEN7(dev_priv))
 
 #define IS_GEN2(dev_priv)	(dev_priv->flags & CHIP_GEN2)
 #define IS_GEN3(dev_priv)	(dev_priv->flags & CHIP_GEN3)
 #define IS_GEN4(dev_priv)	(dev_priv->flags & CHIP_GEN4)
 #define IS_GEN6(dev_priv)	(dev_priv->flags & CHIP_GEN6)
+#define IS_GEN7(dev_priv)	(dev_priv->flags & CHIP_GEN7)
 
 #define I915_HAS_FBC(dev)	(IS_I965GM(dev) || IS_GM45(dev))
 
-#define HAS_PCH_SPLIT(dev)	(IS_IRONLAKE(dev) || IS_GEN6(dev))
+#define HAS_PCH_SPLIT(dev)	(IS_IRONLAKE(dev) || IS_GEN6(dev) || \
+    IS_GEN7(dev))
 
 #define INTEL_INFO(dev)		(dev)
 
diff --git a/sys/dev/pci/drm/i915_irq.c b/sys/dev/pci/drm/i915_irq.c
index a61eea60a9c..99edae49483 100644
--- a/sys/dev/pci/drm/i915_irq.c
+++ b/sys/dev/pci/drm/i915_irq.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: i915_irq.c,v 1.53 2012/05/19 18:02:53 kettenis Exp $ */
+/* $OpenBSD: i915_irq.c,v 1.54 2012/09/25 10:19:46 jsg Exp $ */
 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  */
 /*
@@ -68,7 +68,7 @@ ironlake_enable_graphics_irq(struct inteldrm_softc *dev_priv, u_int32_t mask)
 	if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
 		/* XXX imr bullshit */
 		dev_priv->gt_irq_mask_reg &= ~mask;
-		if (IS_GEN6(dev_priv)) {
+		if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
 			I915_WRITE(0x20a8, dev_priv->gt_irq_mask_reg);
 			(void)I915_READ(0x20a8);
 		} else {
@@ -83,7 +83,7 @@ ironlake_disable_graphics_irq(struct inteldrm_softc *dev_priv, u_int32_t mask)
 {
 	if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
 		dev_priv->gt_irq_mask_reg |= mask;
-		if (IS_GEN6(dev_priv)) {
+		if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
 			I915_WRITE(0x20a8, dev_priv->gt_irq_mask_reg);
 			(void)I915_READ(0x20a8);
 		} else {
@@ -172,7 +172,7 @@ i915_get_vblank_counter(struct drm_device *dev, int pipe)
 
 	/* GM45 just had to be different... */
 	if (IS_GM45(dev_priv) || IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
-	IS_GEN6(dev_priv)) {
+	    IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
 		return (I915_READ(PIPE_FRMCOUNT_GM45(pipe)));
 	}
 
@@ -226,7 +226,10 @@ i915_enable_vblank(struct drm_device *dev, int pipe)
 		return (EINVAL);
 
 	mtx_enter(&dev_priv->user_irq_lock);
-	if (HAS_PCH_SPLIT(dev_priv))
+	if (IS_GEN7(dev_priv))
+		ironlake_enable_display_irq(dev_priv,
+		    DE_PIPEA_VBLANK_IVB << (5 * pipe));
+	else if (HAS_PCH_SPLIT(dev_priv))
 		ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
 		    DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
 	else
@@ -244,7 +247,10 @@ i915_disable_vblank(struct drm_device *dev, int pipe)
 	struct inteldrm_softc	*dev_priv = dev->dev_private;
 
 	mtx_enter(&dev_priv->user_irq_lock);
-	if (HAS_PCH_SPLIT(dev_priv))
+	if (IS_GEN7(dev_priv))
+		ironlake_disable_display_irq(dev_priv,
+		    DE_PIPEA_VBLANK_IVB << (pipe * 5));
+	else if (HAS_PCH_SPLIT(dev_priv))
 		ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
 		    DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
 	else
@@ -262,7 +268,8 @@ i915_driver_irq_install(struct drm_device *dev)
 	struct inteldrm_softc	*dev_priv = dev->dev_private;
 
 	dev->vblank->vb_max = 0xffffff; /* only 24 bits of frame count */
-	if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv))
+	if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv) ||
+	    IS_GEN7(dev_priv))
 		dev->vblank->vb_max = 0xffffffff;
 
 	I915_WRITE(HWSTAM, 0xeffe);
diff --git a/sys/dev/pci/drm/i915_suspend.c b/sys/dev/pci/drm/i915_suspend.c
index 7bd1257e94b..ce6471cdce6 100644
--- a/sys/dev/pci/drm/i915_suspend.c
+++ b/sys/dev/pci/drm/i915_suspend.c
@@ -425,7 +425,7 @@ i915_restore_modeset_reg(struct inteldrm_softc *dev)
 	int i;
 
 	/* XXX until we have FDI link training */
-	if (IS_GEN6(dev_priv))
+	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 		return;
 
 	/* Fences */