Switch from bus_space_read/write to linux io.h interfaces for all

pci "memory space" io.  Further reduces the diff to linux.

ok kettenis@

6 files changed, 30 insertions, 71 deletions

diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu.h b/sys/dev/pci/drm/amd/amdgpu/amdgpu.h
index fd87c9b2b50..9bfa4a63910 100644
--- a/sys/dev/pci/drm/amd/amdgpu/amdgpu.h
+++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu.h
@@ -785,9 +785,7 @@ struct amdgpu_device {
 	/* Register/doorbell mmio */
 	resource_size_t			rmmio_base;
 	resource_size_t			rmmio_size;
-#ifdef __linux__
 	void __iomem			*rmmio;
-#endif
 	bus_space_tag_t			rmmio_bst;
 	bus_space_handle_t		rmmio_bsh;
 	/* protects concurrent MM_INDEX/DATA based register access */
diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
index 483850c7811..b3e7d8da763 100644
--- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
+++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
@@ -251,16 +251,13 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 		return amdgpu_kiq_rreg(adev, reg);
 
 	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
-		ret = bus_space_read_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    reg * 4);
+		ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 	else {
 		unsigned long flags;
 
 		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
-		bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    mmMM_INDEX * 4, reg * 4);
-		ret = bus_space_read_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    mmMM_DATA * 4);
+		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
+		ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 	}
 	trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
@@ -283,8 +280,7 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  */
 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 	if (offset < adev->rmmio_size)
-		return bus_space_read_1(adev->rmmio_bst, adev->rmmio_bsh, 
-		    offset);
+		return (readb(adev->rmmio + offset));
 	BUG();
 }
 
@@ -305,8 +301,7 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
  */
 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 	if (offset < adev->rmmio_size)
-		bus_space_write_1(adev->rmmio_bst, adev->rmmio_bsh,
-		    offset, value);
+		writeb(value, adev->rmmio + offset);
 	else
 		BUG();
 }
@@ -316,16 +311,13 @@ void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg,
 	trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 
 	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
-		bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    reg * 4, v);
+		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 	else {
 		unsigned long flags;
 
 		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
-		bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    mmMM_INDEX * 4, reg * 4);
-		bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    mmMM_DATA * 4, v);
+		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
+		writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 	}
 
@@ -439,8 +431,7 @@ void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 {
 	if (index < adev->doorbell.num_doorbells) {
-		return bus_space_read_4(adev->doorbell.bst, adev->doorbell.bsh,
-		    index * 4);
+		return readl(adev->doorbell.ptr + index);
 	} else {
 		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 		return 0;
@@ -460,8 +451,7 @@ u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 {
 	if (index < adev->doorbell.num_doorbells) {
-		bus_space_write_4(adev->doorbell.bst, adev->doorbell.bsh,
-		    index * 4, v);
+		writel(v, adev->doorbell.ptr + index);
 	} else {
 		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 	}
@@ -479,8 +469,7 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 {
 	if (index < adev->doorbell.num_doorbells) {
-		return bus_space_read_8(adev->doorbell.bst, adev->doorbell.bsh,
-		    index * 4);
+		return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 	} else {
 		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 		return 0;
@@ -500,8 +489,7 @@ u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 {
 	if (index < adev->doorbell.num_doorbells) {
-		bus_space_write_8(adev->doorbell.bst, adev->doorbell.bsh,
-		    index * 4, v);
+		atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 	} else {
 		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 	}
@@ -715,9 +703,7 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 		adev->doorbell.base = 0;
 		adev->doorbell.size = 0;
 		adev->doorbell.num_doorbells = 0;
-#ifdef __linux__
 		adev->doorbell.ptr = NULL;
-#endif
 		return 0;
 	}
 
@@ -770,12 +756,12 @@ static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 {
 #ifdef __linux__
 	iounmap(adev->doorbell.ptr);
-	adev->doorbell.ptr = NULL;
 #else
 	if (adev->doorbell.size > 0)
 		bus_space_unmap(adev->doorbell.bst, adev->doorbell.bsh,
 		    adev->doorbell.size);
 #endif
+	adev->doorbell.ptr = NULL;
 }
 
 
@@ -3362,7 +3348,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
 		pci_iounmap(adev->pdev, adev->rio_mem);
 	adev->rio_mem = NULL;
 	iounmap(adev->rmmio);
-	adev->rmmio = NULL;
 #else
 	if (adev->rio_mem_size > 0)
 		bus_space_unmap(adev->rio_mem_bst, adev->rio_mem_bsh,
@@ -3374,6 +3359,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
 		    adev->rmmio_size);
 	adev->rmmio_size = 0;
 #endif
+	adev->rmmio = NULL;
 	amdgpu_device_doorbell_fini(adev);
 
 	device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h b/sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h
index 6718491c29c..5836b411b36 100644
--- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -28,12 +28,9 @@ struct amdgpu_doorbell {
 	/* doorbell mmio */
 	resource_size_t		base;
 	resource_size_t		size;
-#ifdef __linux__
 	u32 __iomem		*ptr;
-#else
 	bus_space_tag_t		bst;
 	bus_space_handle_t	bsh;
-#endif
 	u32			num_doorbells;	/* Number of doorbells actually reserved for amdgpu. */
 };
 
diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
index a77a6c97ff9..798b25ea337 100644
--- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
+++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
@@ -1623,12 +1623,14 @@ amdgpu_attach(struct device *parent, struct device *self, void *aux)
 	if (adev->family >= CHIP_BONAIRE) {
 		type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x18);
 		if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM ||
-		    pci_mapreg_map(pa, 0x18, type, 0,
+		    pci_mapreg_map(pa, 0x18, type, BUS_SPACE_MAP_LINEAR,
 		    &adev->doorbell.bst, &adev->doorbell.bsh,
 		    &adev->doorbell.base, &adev->doorbell.size, 0)) {
 			printf(": can't map doorbell space\n");
 			return;
 		}
+		adev->doorbell.ptr = bus_space_vaddr(adev->doorbell.bst,
+		    adev->doorbell.bsh);
 	}
 
 	if (adev->family >= CHIP_BONAIRE)
@@ -1638,12 +1640,13 @@ amdgpu_attach(struct device *parent, struct device *self, void *aux)
 
 	type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar);
 	if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM ||
-	    pci_mapreg_map(pa, rmmio_bar, type, 0,
+	    pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR,
 	    &adev->rmmio_bst, &adev->rmmio_bsh, &adev->rmmio_base,
 	    &adev->rmmio_size, 0)) {
 		printf(": can't map rmmio space\n");
 		return;
 	}
+	adev->rmmio = bus_space_vaddr(adev->rmmio_bst, adev->rmmio_bsh);
 
 	/*
 	 * Make sure we have a base address for the ROM such that we
diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
index b558cc6ad31..af5909c2369 100644
--- a/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
+++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
@@ -226,25 +226,21 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
 
 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
 {
-#ifdef __linux__
 	static void *scratch_reg0;
 	static void *scratch_reg1;
 	static void *scratch_reg2;
 	static void *scratch_reg3;
 	static void *spare_int;
-#endif
 	static uint32_t grbm_cntl;
 	static uint32_t grbm_idx;
 	uint32_t i = 0;
 	uint32_t retries = 50000;
 
-#ifdef __linux__
 	scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
 	scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
 	scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
 	scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
 	spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
-#endif
 
 	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
 	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
@@ -254,20 +250,13 @@ static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
 		return;
 	}
 
-	bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-	    (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4,
-	    v);
-	bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-	    (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4,
-	    offset | 0x80000000);
-	bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-	    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4,
-	    1);
+	writel(v, scratch_reg0);
+	writel(offset | 0x80000000, scratch_reg1);
+	writel(1, spare_int);
 	for (i = 0; i < retries; i++) {
 		u32 tmp;
 
-		tmp = bus_space_read_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4);
+		tmp = readl(scratch_reg1);
 		if (!(tmp & 0x80000000))
 			break;
 
diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
index 262a0da94e0..50140375314 100644
--- a/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
+++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
@@ -728,23 +728,19 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 
 void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
 {
-#ifdef __linux__
 	static void *scratch_reg0;
 	static void *scratch_reg1;
 	static void *scratch_reg2;
 	static void *scratch_reg3;
 	static void *spare_int;
-#endif
 	static uint32_t grbm_cntl;
 	static uint32_t grbm_idx;
 
-#ifdef __linux__
 	scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
 	scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
 	scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
 	scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
 	spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
-#endif
 
 	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
 	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
@@ -756,32 +752,22 @@ void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
 
 	if (offset == grbm_cntl || offset == grbm_idx) {
 		if (offset  == grbm_cntl)
-			bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-			    (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4, v);
+			writel(v, scratch_reg2);
 		else if (offset == grbm_idx)
-			bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-			    (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4, v);
+			writel(v, scratch_reg3);
 
-		bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    offset * 4, v);
-		
+		writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
 	} else {
 		uint32_t i = 0;
 		uint32_t retries = 50000;
 
-		bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4, v);
-		bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4,
-		    offset | 0x80000000);
-		bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh,
-		    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4,
-		    1);
+		writel(v, scratch_reg0);
+		writel(offset | 0x80000000, scratch_reg1);
+		writel(1, spare_int);
 		for (i = 0; i < retries; i++) {
 			u32 tmp;
 
-			tmp = bus_space_read_4(adev->rmmio_bst, adev->rmmio_bsh,
-			    (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4);
+			tmp = readl(scratch_reg1);
 			if (!(tmp & 0x80000000))
 				break;