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authorHenning Brauer <henning@cvs.openbsd.org>2003-12-09 23:37:05 +0000
committerHenning Brauer <henning@cvs.openbsd.org>2003-12-09 23:37:05 +0000
commitea5717fddb2625c4aa54f8e35eb92a495197042f (patch)
tree1af085c465ef55881f7be68a80c0dcecea3604f4
parentc5d8eb6e64e891202326fbadf75bbaf33a549c1b (diff)
sync with FreeBSD
allow for support of several newer chips that apparently are all sold as PROO/1000 and PRO/1000MT tested by naddy@ and ho@ ok deraadt@
Diffstat
-rw-r--r--sys/dev/pci/if_em_hw.c2052
-rw-r--r--sys/dev/pci/if_em_hw.h416
2 files changed, 1543 insertions, 925 deletions
diff --git a/sys/dev/pci/if_em_hw.c b/sys/dev/pci/if_em_hw.c
index 8cc744ed42c..9a889d13509 100644
--- a/sys/dev/pci/if_em_hw.c
+++ b/sys/dev/pci/if_em_hw.c
@@ -31,12 +31,12 @@
*******************************************************************************/
-/*$FreeBSD: if_em_hw.c,v 1.9 2003/06/05 17:51:38 pdeuskar Exp $*/
-/* $OpenBSD: if_em_hw.c,v 1.2 2003/06/13 19:21:21 henric Exp $ */
+/* $FreeBSD: if_em_hw.c,v 1.12 2003/11/14 18:02:24 pdeuskar Exp $ */
+/* $OpenBSD: if_em_hw.c,v 1.3 2003/12/09 23:37:03 henning Exp $ */
/* if_em_hw.c
* Shared functions for accessing and configuring the MAC
*/
-
+
#include "bpfilter.h"
#include "vlan.h"
@@ -80,14 +80,15 @@
static int32_t em_set_phy_type(struct em_hw *hw);
static void em_phy_init_script(struct em_hw *hw);
-static int32_t em_setup_fiber_link(struct em_hw *hw);
static int32_t em_setup_copper_link(struct em_hw *hw);
+static int32_t em_setup_fiber_serdes_link(struct em_hw *hw);
+static int32_t em_adjust_serdes_amplitude(struct em_hw *hw);
static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
static int32_t em_config_mac_to_phy(struct em_hw *hw);
-static int32_t em_force_mac_fc(struct em_hw *hw);
static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
-static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count);
+static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data,
+ uint16_t count);
static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
static int32_t em_phy_reset_dsp(struct em_hw *hw);
static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
@@ -98,13 +99,30 @@ static int32_t em_write_eeprom_microwire(struct em_hw *hw,
static int32_t em_spi_eeprom_ready(struct em_hw *hw);
static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
-static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count);
+static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data,
+ uint16_t count);
+static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
+ uint16_t phy_data);
+static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr,
+ uint16_t *phy_data);
static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
static int32_t em_acquire_eeprom(struct em_hw *hw);
static void em_release_eeprom(struct em_hw *hw);
static void em_standby_eeprom(struct em_hw *hw);
static int32_t em_id_led_init(struct em_hw * hw);
+static int32_t em_set_vco_speed(struct em_hw *hw);
+/* IGP cable length table */
+static const
+uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
+ { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+ 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
+ 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
+ 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
+ 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
+ 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
+ 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
/******************************************************************************
@@ -146,41 +164,64 @@ em_phy_init_script(struct em_hw *hw)
DEBUGFUNC("em_phy_init_script");
if(hw->phy_init_script) {
- msec_delay(10);
+ msec_delay(20);
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x0000);
em_write_phy_reg(hw,0x0000,0x0140);
msec_delay(5);
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F95);
- em_write_phy_reg(hw,0x0015,0x0001);
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F71);
- em_write_phy_reg(hw,0x0011,0xBD21);
+ if(hw->mac_type == em_82541 || hw->mac_type == em_82547) {
+ em_write_phy_reg(hw, 0x1F95, 0x0001);
+
+ em_write_phy_reg(hw, 0x1F71, 0xBD21);
+
+ em_write_phy_reg(hw, 0x1F79, 0x0018);
+
+ em_write_phy_reg(hw, 0x1F30, 0x1600);
+
+ em_write_phy_reg(hw, 0x1F31, 0x0014);
+
+ em_write_phy_reg(hw, 0x1F32, 0x161C);
+
+ em_write_phy_reg(hw, 0x1F94, 0x0003);
+
+ em_write_phy_reg(hw, 0x1F96, 0x003F);
+
+ em_write_phy_reg(hw, 0x2010, 0x0008);
+ } else {
+ em_write_phy_reg(hw, 0x1F73, 0x0099);
+ }
+
+ em_write_phy_reg(hw, 0x0000, 0x3300);
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F79);
- em_write_phy_reg(hw,0x0019,0x0018);
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F30);
- em_write_phy_reg(hw,0x0010,0x1600);
+ if(hw->mac_type == em_82547) {
+ uint16_t fused, fine, coarse;
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F31);
- em_write_phy_reg(hw,0x0011,0x0014);
+ /* Move to analog registers page */
+ em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F32);
- em_write_phy_reg(hw,0x0012,0x161C);
+ if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
+ em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F94);
- em_write_phy_reg(hw,0x0014,0x0003);
+ fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
+ coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F96);
- em_write_phy_reg(hw,0x0016,0x003F);
+ if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
+ coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
+ fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
+ } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
+ fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x2010);
- em_write_phy_reg(hw,0x0010,0x0008);
+ fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
+ (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
+ (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
- em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x0000);
- em_write_phy_reg(hw,0x0000,0x3300);
+ em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
+ em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
+ IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
+ }
+ }
}
}
@@ -229,32 +270,89 @@ em_set_mac_type(struct em_hw *hw)
case E1000_DEV_ID_82545EM_FIBER:
hw->mac_type = em_82545;
break;
+ case E1000_DEV_ID_82545GM_COPPER:
+ case E1000_DEV_ID_82545GM_FIBER:
+ case E1000_DEV_ID_82545GM_SERDES:
+ hw->mac_type = em_82545_rev_3;
+ break;
case E1000_DEV_ID_82546EB_COPPER:
case E1000_DEV_ID_82546EB_FIBER:
case E1000_DEV_ID_82546EB_QUAD_COPPER:
hw->mac_type = em_82546;
break;
+ case E1000_DEV_ID_82546GB_COPPER:
+ case E1000_DEV_ID_82546GB_FIBER:
+ case E1000_DEV_ID_82546GB_SERDES:
+ hw->mac_type = em_82546_rev_3;
+ break;
case E1000_DEV_ID_82541EI:
- case E1000_DEV_ID_82541EP:
+ case E1000_DEV_ID_82541EI_MOBILE:
hw->mac_type = em_82541;
break;
+ case E1000_DEV_ID_82541ER:
+ case E1000_DEV_ID_82541GI:
+ case E1000_DEV_ID_82541GI_MOBILE:
+ hw->mac_type = em_82541_rev_2;
+ break;
case E1000_DEV_ID_82547EI:
hw->mac_type = em_82547;
break;
+ case E1000_DEV_ID_82547GI:
+ hw->mac_type = em_82547_rev_2;
+ break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_MAC_TYPE;
}
-
return E1000_SUCCESS;
}
+
+/*****************************************************************************
+ * Set media type and TBI compatibility.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * **************************************************************************/
+void
+em_set_media_type(struct em_hw *hw)
+{
+ uint32_t status;
+
+ DEBUGFUNC("em_set_media_type");
+
+ if(hw->mac_type != em_82543) {
+ /* tbi_compatibility is only valid on 82543 */
+ hw->tbi_compatibility_en = FALSE;
+ }
+
+ switch (hw->device_id) {
+ case E1000_DEV_ID_82545GM_SERDES:
+ case E1000_DEV_ID_82546GB_SERDES:
+ hw->media_type = em_media_type_internal_serdes;
+ break;
+ default:
+ if(hw->mac_type >= em_82543) {
+ status = E1000_READ_REG(hw, STATUS);
+ if(status & E1000_STATUS_TBIMODE) {
+ hw->media_type = em_media_type_fiber;
+ /* tbi_compatibility not valid on fiber */
+ hw->tbi_compatibility_en = FALSE;
+ } else {
+ hw->media_type = em_media_type_copper;
+ }
+ } else {
+ /* This is an 82542 (fiber only) */
+ hw->media_type = em_media_type_fiber;
+ }
+ }
+}
+
/******************************************************************************
* Reset the transmit and receive units; mask and clear all interrupts.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
-void
+int32_t
em_reset_hw(struct em_hw *hw)
{
uint32_t ctrl;
@@ -291,49 +389,75 @@ em_reset_hw(struct em_hw *hw)
*/
msec_delay(10);
- /* Issue a global reset to the MAC. This will reset the chip's
- * transmit, receive, DMA, and link units. It will not effect
- * the current PCI configuration. The global reset bit is self-
- * clearing, and should clear within a microsecond.
- */
- DEBUGOUT("Issuing a global reset to MAC\n");
ctrl = E1000_READ_REG(hw, CTRL);
/* Must reset the PHY before resetting the MAC */
if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
- msec_delay(5);
+ msec_delay(5);
}
+ /* Issue a global reset to the MAC. This will reset the chip's
+ * transmit, receive, DMA, and link units. It will not effect
+ * the current PCI configuration. The global reset bit is self-
+ * clearing, and should clear within a microsecond.
+ */
+ DEBUGOUT("Issuing a global reset to MAC\n");
+
switch(hw->mac_type) {
case em_82544:
case em_82540:
case em_82545:
case em_82546:
case em_82541:
+ case em_82541_rev_2:
/* These controllers can't ack the 64-bit write when issuing the
* reset, so use IO-mapping as a workaround to issue the reset */
E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
break;
+ case em_82545_rev_3:
+ case em_82546_rev_3:
+ /* Reset is performed on a shadow of the control register */
+ E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
+ break;
default:
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
break;
}
- /* Force a reload from the EEPROM if necessary */
- if(hw->mac_type < em_82540) {
- /* Wait for reset to complete */
- usec_delay(10);
- ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
- ctrl_ext |= E1000_CTRL_EXT_EE_RST;
- E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
- E1000_WRITE_FLUSH(hw);
- /* Wait for EEPROM reload */
- msec_delay(2);
- } else {
- /* Wait for EEPROM reload (it happens automatically) */
- msec_delay(5);
- /* Dissable HW ARPs on ASF enabled adapters */
+ /* After MAC reset, force reload of EEPROM to restore power-on settings to
+ * device. Later controllers reload the EEPROM automatically, so just wait
+ * for reload to complete.
+ */
+ switch(hw->mac_type) {
+ case em_82542_rev2_0:
+ case em_82542_rev2_1:
+ case em_82543:
+ case em_82544:
+ /* Wait for reset to complete */
+ usec_delay(10);
+ ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+ ctrl_ext |= E1000_CTRL_EXT_EE_RST;
+ E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+ E1000_WRITE_FLUSH(hw);
+ /* Wait for EEPROM reload */
+ msec_delay(2);
+ break;
+ case em_82541:
+ case em_82541_rev_2:
+ case em_82547:
+ case em_82547_rev_2:
+ /* Wait for EEPROM reload */
+ msec_delay(20);
+ break;
+ default:
+ /* Wait for EEPROM reload (it happens automatically) */
+ msec_delay(5);
+ break;
+ }
+
+ /* Disable HW ARPs on ASF enabled adapters */
+ if(hw->mac_type >= em_82540) {
manc = E1000_READ_REG(hw, MANC);
manc &= ~(E1000_MANC_ARP_EN);
E1000_WRITE_REG(hw, MANC, manc);
@@ -361,6 +485,8 @@ em_reset_hw(struct em_hw *hw)
if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
em_pci_set_mwi(hw);
}
+
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -377,7 +503,7 @@ em_reset_hw(struct em_hw *hw)
int32_t
em_init_hw(struct em_hw *hw)
{
- uint32_t ctrl, status;
+ uint32_t ctrl;
uint32_t i;
int32_t ret_val;
uint16_t pcix_cmd_word;
@@ -388,31 +514,13 @@ em_init_hw(struct em_hw *hw)
DEBUGFUNC("em_init_hw");
/* Initialize Identification LED */
- ret_val = em_id_led_init(hw);
- if(ret_val < 0) {
+ if((ret_val = em_id_led_init(hw))) {
DEBUGOUT("Error Initializing Identification LED\n");
return ret_val;
}
- /* Set the Media Type and exit with error if it is not valid. */
- if(hw->mac_type != em_82543) {
- /* tbi_compatibility is only valid on 82543 */
- hw->tbi_compatibility_en = FALSE;
- }
-
- if(hw->mac_type >= em_82543) {
- status = E1000_READ_REG(hw, STATUS);
- if(status & E1000_STATUS_TBIMODE) {
- hw->media_type = em_media_type_fiber;
- /* tbi_compatibility not valid on fiber */
- hw->tbi_compatibility_en = FALSE;
- } else {
- hw->media_type = em_media_type_copper;
- }
- } else {
- /* This is an 82542 (fiber only) */
- hw->media_type = em_media_type_fiber;
- }
+ /* Set the media type and TBI compatibility */
+ em_set_media_type(hw);
/* Disabling VLAN filtering. */
DEBUGOUT("Initializing the IEEE VLAN\n");
@@ -457,21 +565,30 @@ em_init_hw(struct em_hw *hw)
E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
}
- /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
- if(hw->bus_type == em_bus_type_pcix) {
- em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
- em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
- cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
- PCIX_COMMAND_MMRBC_SHIFT;
- stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
- PCIX_STATUS_HI_MMRBC_SHIFT;
- if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
- stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
- if(cmd_mmrbc > stat_mmrbc) {
- pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
- pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
- em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
+ switch(hw->mac_type) {
+ case em_82545_rev_3:
+ case em_82546_rev_3:
+ break;
+ default:
+ /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
+ if(hw->bus_type == em_bus_type_pcix) {
+ em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
+ em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
+ &pcix_stat_hi_word);
+ cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
+ PCIX_COMMAND_MMRBC_SHIFT;
+ stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
+ PCIX_STATUS_HI_MMRBC_SHIFT;
+ if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
+ stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
+ if(cmd_mmrbc > stat_mmrbc) {
+ pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
+ pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
+ em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
+ &pcix_cmd_word);
+ }
}
+ break;
}
/* Call a subroutine to configure the link and setup flow control. */
@@ -495,6 +612,46 @@ em_init_hw(struct em_hw *hw)
}
/******************************************************************************
+ * Adjust SERDES output amplitude based on EEPROM setting.
+ *
+ * hw - Struct containing variables accessed by shared code.
+ *****************************************************************************/
+static int32_t
+em_adjust_serdes_amplitude(struct em_hw *hw)
+{
+ uint16_t eeprom_data;
+ int32_t ret_val;
+
+ DEBUGFUNC("em_adjust_serdes_amplitude");
+
+ if(hw->media_type != em_media_type_internal_serdes)
+ return E1000_SUCCESS;
+
+ switch(hw->mac_type) {
+ case em_82545_rev_3:
+ case em_82546_rev_3:
+ break;
+ default:
+ return E1000_SUCCESS;
+ }
+
+ if ((ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
+ &eeprom_data))) {
+ return ret_val;
+ }
+
+ if(eeprom_data != EEPROM_RESERVED_WORD) {
+ /* Adjust SERDES output amplitude only. */
+ eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
+ if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
+ eeprom_data)))
+ return ret_val;
+ }
+
+ return E1000_SUCCESS;
+}
+
+/******************************************************************************
* Configures flow control and link settings.
*
* hw - Struct containing variables accessed by shared code
@@ -565,9 +722,9 @@ em_setup_link(struct em_hw *hw)
}
/* Call the necessary subroutine to configure the link. */
- ret_val = (hw->media_type == em_media_type_fiber) ?
- em_setup_fiber_link(hw) :
- em_setup_copper_link(hw);
+ ret_val = (hw->media_type == em_media_type_copper) ?
+ em_setup_copper_link(hw) :
+ em_setup_fiber_serdes_link(hw);
/* Initialize the flow control address, type, and PAUSE timer
* registers to their default values. This is done even if flow
@@ -606,7 +763,7 @@ em_setup_link(struct em_hw *hw)
}
/******************************************************************************
- * Sets up link for a fiber based adapter
+ * Sets up link for a fiber based or serdes based adapter
*
* hw - Struct containing variables accessed by shared code
*
@@ -615,28 +772,37 @@ em_setup_link(struct em_hw *hw)
* and receiver are not enabled.
*****************************************************************************/
static int32_t
-em_setup_fiber_link(struct em_hw *hw)
+em_setup_fiber_serdes_link(struct em_hw *hw)
{
uint32_t ctrl;
uint32_t status;
uint32_t txcw = 0;
uint32_t i;
- uint32_t signal;
+ uint32_t signal = 0;
int32_t ret_val;
- DEBUGFUNC("em_setup_fiber_link");
+ DEBUGFUNC("em_setup_fiber_serdes_link");
- /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
+ /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
- * cleared when there is a signal
+ * cleared when there is a signal. This applies to fiber media only.
+ * If we're on serdes media, adjust the output amplitude to value set in
+ * the EEPROM.
*/
ctrl = E1000_READ_REG(hw, CTRL);
- if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1;
- else signal = 0;
+ if(hw->media_type == em_media_type_fiber)
+ signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
+
+ if((ret_val = em_adjust_serdes_amplitude(hw)))
+ return ret_val;
/* Take the link out of reset */
ctrl &= ~(E1000_CTRL_LRST);
+ /* Adjust VCO speed to improve BER performance */
+ if((ret_val = em_set_vco_speed(hw)))
+ return ret_val;
+
em_config_collision_dist(hw);
/* Check for a software override of the flow control settings, and setup
@@ -703,8 +869,10 @@ em_setup_fiber_link(struct em_hw *hw)
* indication in the Device Status Register. Time-out if a link isn't
* seen in 500 milliseconds seconds (Auto-negotiation should complete in
* less than 500 milliseconds even if the other end is doing it in SW).
+ * For internal serdes, we just assume a signal is present, then poll.
*/
- if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
+ if(hw->media_type == em_media_type_internal_serdes ||
+ (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
DEBUGOUT("Looking for Link\n");
for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
msec_delay(10);
@@ -712,15 +880,14 @@ em_setup_fiber_link(struct em_hw *hw)
if(status & E1000_STATUS_LU) break;
}
if(i == (LINK_UP_TIMEOUT / 10)) {
+ DEBUGOUT("Never got a valid link from auto-neg!!!\n");
+ hw->autoneg_failed = 1;
/* AutoNeg failed to achieve a link, so we'll call
- * em_check_for_link. This routine will force the link up if we
- * detect a signal. This will allow us to communicate with
+ * em_check_for_link. This routine will force the link up if
+ * we detect a signal. This will allow us to communicate with
* non-autonegotiating link partners.
*/
- DEBUGOUT("Never got a valid link from auto-neg!!!\n");
- hw->autoneg_failed = 1;
- ret_val = em_check_for_link(hw);
- if(ret_val < 0) {
+ if((ret_val = em_check_for_link(hw))) {
DEBUGOUT("Error while checking for link\n");
return ret_val;
}
@@ -732,7 +899,7 @@ em_setup_fiber_link(struct em_hw *hw)
} else {
DEBUGOUT("No Signal Detected\n");
}
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -767,233 +934,281 @@ em_setup_copper_link(struct em_hw *hw)
}
/* Make sure we have a valid PHY */
- ret_val = em_detect_gig_phy(hw);
- if(ret_val < 0) {
+ if((ret_val = em_detect_gig_phy(hw))) {
DEBUGOUT("Error, did not detect valid phy.\n");
return ret_val;
}
DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
- if (hw->phy_type == em_phy_igp) {
+ if(hw->mac_type <= em_82543 ||
+ hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
+ hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
+ hw->phy_reset_disable = FALSE;
- ret_val = em_phy_reset(hw);
- if(ret_val < 0) {
- DEBUGOUT("Error Resetting the PHY\n");
- return ret_val;
- }
+ if(!hw->phy_reset_disable) {
+ if (hw->phy_type == em_phy_igp) {
- /* Wait 10ms for MAC to configure PHY from eeprom settings */
- msec_delay(15);
+ if((ret_val = em_phy_reset(hw))) {
+ DEBUGOUT("Error Resetting the PHY\n");
+ return ret_val;
+ }
- if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0000) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ /* Wait 10ms for MAC to configure PHY from eeprom settings */
+ msec_delay(15);
- /* Configure activity LED after PHY reset */
- led_ctrl = E1000_READ_REG(hw, LEDCTL);
- led_ctrl &= IGP_ACTIVITY_LED_MASK;
- led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
- E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
+ /* Configure activity LED after PHY reset */
+ led_ctrl = E1000_READ_REG(hw, LEDCTL);
+ led_ctrl &= IGP_ACTIVITY_LED_MASK;
+ led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+ E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
- if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
- /* Disable SmartSpeed */
- if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
- /* Set auto Master/Slave resolution process */
- if(em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
+ /* disable lplu d3 during driver init */
+ if((ret_val = em_set_d3_lplu_state(hw, FALSE))) {
+ DEBUGOUT("Error Disabling LPLU D3\n");
+ return ret_val;
}
- phy_data &= ~CR_1000T_MS_ENABLE;
- if(em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
+
+ /* Configure mdi-mdix settings */
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
+ &phy_data)))
+ return ret_val;
+
+ if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
+ hw->dsp_config_state = em_dsp_config_disabled;
+ /* Force MDI for IGP B-0 PHY */
+ phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
+ IGP01E1000_PSCR_FORCE_MDI_MDIX);
+ hw->mdix = 1;
+
+ } else {
+ hw->dsp_config_state = em_dsp_config_enabled;
+ phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
+
+ switch (hw->mdix) {
+ case 1:
+ phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
+ break;
+ case 2:
+ phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
+ break;
+ case 0:
+ default:
+ phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
+ break;
+ }
}
- }
+ if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
+ phy_data)))
+ return ret_val;
- if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ /* set auto-master slave resolution settings */
+ if(hw->autoneg) {
+ em_ms_type phy_ms_setting = hw->master_slave;
+
+ if(hw->ffe_config_state == em_ffe_config_active)
+ hw->ffe_config_state = em_ffe_config_enabled;
+
+ if(hw->dsp_config_state == em_dsp_config_activated)
+ hw->dsp_config_state = em_dsp_config_enabled;
+
+ /* when autonegotiation advertisment is only 1000Mbps then we
+ * should disable SmartSpeed and enable Auto MasterSlave
+ * resolution as hardware default. */
+ if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
+ /* Disable SmartSpeed */
+ if((ret_val = em_read_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG,
+ &phy_data)))
+ return ret_val;
+ phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+ if((ret_val = em_write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG,
+ phy_data)))
+ return ret_val;
+ /* Set auto Master/Slave resolution process */
+ if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
+ &phy_data)))
+ return ret_val;
+ phy_data &= ~CR_1000T_MS_ENABLE;
+ if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
+ phy_data)))
+ return ret_val;
+ }
- /* Force MDI for IGP PHY */
- phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
- IGP01E1000_PSCR_FORCE_MDI_MDIX);
+ if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
+ &phy_data)))
+ return ret_val;
- hw->mdix = 1;
+ /* load defaults for future use */
+ hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
+ ((phy_data & CR_1000T_MS_VALUE) ?
+ em_ms_force_master :
+ em_ms_force_slave) :
+ em_ms_auto;
- if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ switch (phy_ms_setting) {
+ case em_ms_force_master:
+ phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
+ break;
+ case em_ms_force_slave:
+ phy_data |= CR_1000T_MS_ENABLE;
+ phy_data &= ~(CR_1000T_MS_VALUE);
+ break;
+ case em_ms_auto:
+ phy_data &= ~CR_1000T_MS_ENABLE;
+ default:
+ break;
+ }
+ if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
+ phy_data)))
+ return ret_val;
+ }
+ } else {
+ /* Enable CRS on TX. This must be set for half-duplex operation. */
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ &phy_data)))
+ return ret_val;
- } else {
- /* Enable CRS on TX. This must be set for half-duplex operation. */
- if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
+ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
- /* Options:
- * MDI/MDI-X = 0 (default)
- * 0 - Auto for all speeds
- * 1 - MDI mode
- * 2 - MDI-X mode
- * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
- */
- phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+ /* Options:
+ * MDI/MDI-X = 0 (default)
+ * 0 - Auto for all speeds
+ * 1 - MDI mode
+ * 2 - MDI-X mode
+ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
+ */
+ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
- switch (hw->mdix) {
- case 1:
- phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
- break;
- case 2:
- phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
- break;
- case 3:
- phy_data |= M88E1000_PSCR_AUTO_X_1000T;
- break;
- case 0:
- default:
- phy_data |= M88E1000_PSCR_AUTO_X_MODE;
- break;
- }
+ switch (hw->mdix) {
+ case 1:
+ phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
+ break;
+ case 2:
+ phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
+ break;
+ case 3:
+ phy_data |= M88E1000_PSCR_AUTO_X_1000T;
+ break;
+ case 0:
+ default:
+ phy_data |= M88E1000_PSCR_AUTO_X_MODE;
+ break;
+ }
- /* Options:
- * disable_polarity_correction = 0 (default)
- * Automatic Correction for Reversed Cable Polarity
- * 0 - Disabled
- * 1 - Enabled
- */
- phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
- if(hw->disable_polarity_correction == 1)
- phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
- if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ /* Options:
+ * disable_polarity_correction = 0 (default)
+ * Automatic Correction for Reversed Cable Polarity
+ * 0 - Disabled
+ * 1 - Enabled
+ */
+ phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
+ if(hw->disable_polarity_correction == 1)
+ phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
+ if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ phy_data)))
+ return ret_val;
- /* Force TX_CLK in the Extended PHY Specific Control Register
- * to 25MHz clock.
- */
- if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- phy_data |= M88E1000_EPSCR_TX_CLK_25;
+ /* Force TX_CLK in the Extended PHY Specific Control Register
+ * to 25MHz clock.
+ */
+ if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+ &phy_data)))
+ return ret_val;
- if (hw->phy_revision < M88E1011_I_REV_4) {
- /* Configure Master and Slave downshift values */
- phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
- M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
- phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
- M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
- if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
- phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
+ phy_data |= M88E1000_EPSCR_TX_CLK_25;
+
+ if (hw->phy_revision < M88E1011_I_REV_4) {
+ /* Configure Master and Slave downshift values */
+ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
+ M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
+ phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
+ M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
+ if((ret_val = em_write_phy_reg(hw,
+ M88E1000_EXT_PHY_SPEC_CTRL,
+ phy_data)))
+ return ret_val;
}
- }
- /* SW Reset the PHY so all changes take effect */
- ret_val = em_phy_reset(hw);
- if(ret_val < 0) {
- DEBUGOUT("Error Resetting the PHY\n");
- return ret_val;
+ /* SW Reset the PHY so all changes take effect */
+ if((ret_val = em_phy_reset(hw))) {
+ DEBUGOUT("Error Resetting the PHY\n");
+ return ret_val;
+ }
}
- }
-
- /* Options:
- * autoneg = 1 (default)
- * PHY will advertise value(s) parsed from
- * autoneg_advertised and fc
- * autoneg = 0
- * PHY will be set to 10H, 10F, 100H, or 100F
- * depending on value parsed from forced_speed_duplex.
- */
- /* Is autoneg enabled? This is enabled by default or by software override.
- * If so, call em_phy_setup_autoneg routine to parse the
- * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
- * user should have provided a speed/duplex override. If so, then call
- * em_phy_force_speed_duplex to parse and set this up.
- */
- if(hw->autoneg) {
- /* Perform some bounds checking on the hw->autoneg_advertised
- * parameter. If this variable is zero, then set it to the default.
+ /* Options:
+ * autoneg = 1 (default)
+ * PHY will advertise value(s) parsed from
+ * autoneg_advertised and fc
+ * autoneg = 0
+ * PHY will be set to 10H, 10F, 100H, or 100F
+ * depending on value parsed from forced_speed_duplex.
*/
- hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
- /* If autoneg_advertised is zero, we assume it was not defaulted
- * by the calling code so we set to advertise full capability.
+ /* Is autoneg enabled? This is enabled by default or by software
+ * override. If so, call em_phy_setup_autoneg routine to parse the
+ * autoneg_advertised and fc options. If autoneg is NOT enabled, then
+ * the user should have provided a speed/duplex override. If so, then
+ * call em_phy_force_speed_duplex to parse and set this up.
*/
- if(hw->autoneg_advertised == 0)
- hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+ if(hw->autoneg) {
+ /* Perform some bounds checking on the hw->autoneg_advertised
+ * parameter. If this variable is zero, then set it to the default.
+ */
+ hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
- DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
- ret_val = em_phy_setup_autoneg(hw);
- if(ret_val < 0) {
- DEBUGOUT("Error Setting up Auto-Negotiation\n");
- return ret_val;
- }
- DEBUGOUT("Restarting Auto-Neg\n");
+ /* If autoneg_advertised is zero, we assume it was not defaulted
+ * by the calling code so we set to advertise full capability.
+ */
+ if(hw->autoneg_advertised == 0)
+ hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- /* Restart auto-negotiation by setting the Auto Neg Enable bit and
- * the Auto Neg Restart bit in the PHY control register.
- */
- if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
- if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
+ if((ret_val = em_phy_setup_autoneg(hw))) {
+ DEBUGOUT("Error Setting up Auto-Negotiation\n");
+ return ret_val;
+ }
+ DEBUGOUT("Restarting Auto-Neg\n");
- /* Does the user want to wait for Auto-Neg to complete here, or
- * check at a later time (for example, callback routine).
- */
- if(hw->wait_autoneg_complete) {
- ret_val = em_wait_autoneg(hw);
- if(ret_val < 0) {
- DEBUGOUT("Error while waiting for autoneg to complete\n");
+ /* Restart auto-negotiation by setting the Auto Neg Enable bit and
+ * the Auto Neg Restart bit in the PHY control register.
+ */
+ if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data)))
+ return ret_val;
+
+ phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
+ if((ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data)))
+ return ret_val;
+
+ /* Does the user want to wait for Auto-Neg to complete here, or
+ * check at a later time (for example, callback routine).
+ */
+ if(hw->wait_autoneg_complete) {
+ if((ret_val = em_wait_autoneg(hw))) {
+ DEBUGOUT("Error while waiting for autoneg to complete\n");
+ return ret_val;
+ }
+ }
+ hw->get_link_status = TRUE;
+ } else {
+ DEBUGOUT("Forcing speed and duplex\n");
+ if((ret_val = em_phy_force_speed_duplex(hw))) {
+ DEBUGOUT("Error Forcing Speed and Duplex\n");
return ret_val;
}
}
- hw->get_link_status = TRUE;
- } else {
- DEBUGOUT("Forcing speed and duplex\n");
- ret_val = em_phy_force_speed_duplex(hw);
- if(ret_val < 0) {
- DEBUGOUT("Error Forcing Speed and Duplex\n");
- return ret_val;
- }
- }
+ } /* !hw->phy_reset_disable */
/* Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
for(i = 0; i < 10; i++) {
- if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ return ret_val;
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ return ret_val;
+
if(phy_data & MII_SR_LINK_STATUS) {
/* We have link, so we need to finish the config process:
* 1) Set up the MAC to the current PHY speed/duplex
@@ -1006,25 +1221,31 @@ em_setup_copper_link(struct em_hw *hw)
if(hw->mac_type >= em_82544) {
em_config_collision_dist(hw);
} else {
- ret_val = em_config_mac_to_phy(hw);
- if(ret_val < 0) {
+ if((ret_val = em_config_mac_to_phy(hw))) {
DEBUGOUT("Error configuring MAC to PHY settings\n");
return ret_val;
- }
+ }
}
- ret_val = em_config_fc_after_link_up(hw);
- if(ret_val < 0) {
+ if((ret_val = em_config_fc_after_link_up(hw))) {
DEBUGOUT("Error Configuring Flow Control\n");
return ret_val;
}
DEBUGOUT("Valid link established!!!\n");
- return 0;
+
+ if(hw->phy_type == em_phy_igp) {
+ if((ret_val = em_config_dsp_after_link_change(hw, TRUE))) {
+ DEBUGOUT("Error Configuring DSP after link up\n");
+ return ret_val;
+ }
+ }
+ DEBUGOUT("Valid link established!!!\n");
+ return E1000_SUCCESS;
}
usec_delay(10);
}
DEBUGOUT("Unable to establish link!!!\n");
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -1035,22 +1256,20 @@ em_setup_copper_link(struct em_hw *hw)
int32_t
em_phy_setup_autoneg(struct em_hw *hw)
{
+ int32_t ret_val;
uint16_t mii_autoneg_adv_reg;
uint16_t mii_1000t_ctrl_reg;
DEBUGFUNC("em_phy_setup_autoneg");
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
- if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
+ &mii_autoneg_adv_reg)))
+ return ret_val;
/* Read the MII 1000Base-T Control Register (Address 9). */
- if(em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
+ return ret_val;
/* Need to parse both autoneg_advertised and fc and set up
* the appropriate PHY registers. First we will parse for
@@ -1156,18 +1375,16 @@ em_phy_setup_autoneg(struct em_hw *hw)
return -E1000_ERR_CONFIG;
}
- if(em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV,
+ mii_autoneg_adv_reg)))
+ return ret_val;
DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
- if(em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
- return 0;
+ if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
+ return ret_val;
+
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -1203,10 +1420,8 @@ em_phy_force_speed_duplex(struct em_hw *hw)
ctrl &= ~E1000_CTRL_ASDE;
/* Read the MII Control Register. */
- if(em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg)))
+ return ret_val;
/* We need to disable autoneg in order to force link and duplex. */
@@ -1252,19 +1467,18 @@ em_phy_force_speed_duplex(struct em_hw *hw)
E1000_WRITE_REG(hw, CTRL, ctrl);
if (hw->phy_type == em_phy_m88) {
- if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ &phy_data)))
+ return ret_val;
/* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
* forced whenever speed are duplex are forced.
*/
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
- if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ phy_data)))
+ return ret_val;
+
DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
/* Need to reset the PHY or these changes will be ignored */
@@ -1273,25 +1487,22 @@ em_phy_force_speed_duplex(struct em_hw *hw)
/* Clear Auto-Crossover to force MDI manually. IGP requires MDI
* forced whenever speed or duplex are forced.
*/
- if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
+ &phy_data)))
+ return ret_val;
phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
- if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
+ phy_data)))
+ return ret_val;
}
/* Write back the modified PHY MII control register. */
- if(em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg)))
+ return ret_val;
+
usec_delay(1);
/* The wait_autoneg_complete flag may be a little misleading here.
@@ -1311,22 +1522,18 @@ em_phy_force_speed_duplex(struct em_hw *hw)
/* Read the MII Status Register and wait for Auto-Neg Complete bit
* to be set.
*/
- if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ return ret_val;
+
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ return ret_val;
+
if(mii_status_reg & MII_SR_LINK_STATUS) break;
msec_delay(100);
}
if(i == 0) { /* We didn't get link */
/* Reset the DSP and wait again for link. */
-
- ret_val = em_phy_reset_dsp(hw);
- if(ret_val < 0) {
+ if((ret_val = em_phy_reset_dsp(hw))) {
DEBUGOUT("Error Resetting PHY DSP\n");
return ret_val;
}
@@ -1338,14 +1545,11 @@ em_phy_force_speed_duplex(struct em_hw *hw)
/* Read the MII Status Register and wait for Auto-Neg Complete bit
* to be set.
*/
- if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ return ret_val;
+
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ return ret_val;
}
}
@@ -1354,30 +1558,29 @@ em_phy_force_speed_duplex(struct em_hw *hw)
* Extended PHY Specific Control Register to 25MHz clock. This value
* defaults back to a 2.5MHz clock when the PHY is reset.
*/
- if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+ &phy_data)))
+ return ret_val;
+
phy_data |= M88E1000_EPSCR_TX_CLK_25;
- if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+ phy_data)))
+ return ret_val;
/* In addition, because of the s/w reset above, we need to enable CRS on
* TX. This must be set for both full and half duplex operation.
*/
- if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ &phy_data)))
+ return ret_val;
+
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
- if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ phy_data)))
+ return ret_val;
+
}
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -1417,6 +1620,7 @@ static int32_t
em_config_mac_to_phy(struct em_hw *hw)
{
uint32_t ctrl;
+ int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_config_mac_to_phy");
@@ -1432,10 +1636,10 @@ em_config_mac_to_phy(struct em_hw *hw)
* registers depending on negotiated values.
*/
if (hw->phy_type == em_phy_igp) {
- if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
+ &phy_data)))
+ return ret_val;
+
if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
else ctrl &= ~E1000_CTRL_FD;
@@ -1451,10 +1655,10 @@ em_config_mac_to_phy(struct em_hw *hw)
IGP01E1000_PSSR_SPEED_100MBPS)
ctrl |= E1000_CTRL_SPD_100;
} else {
- if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data)))
+ return ret_val;
+
if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
else ctrl &= ~E1000_CTRL_FD;
@@ -1470,7 +1674,7 @@ em_config_mac_to_phy(struct em_hw *hw)
}
/* Write the configured values back to the Device Control Reg. */
E1000_WRITE_REG(hw, CTRL, ctrl);
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -1484,7 +1688,7 @@ em_config_mac_to_phy(struct em_hw *hw)
* by the PHY rather than the MAC. Software must also configure these
* bits when link is forced on a fiber connection.
*****************************************************************************/
-static int32_t
+int32_t
em_force_mac_fc(struct em_hw *hw)
{
uint32_t ctrl;
@@ -1537,7 +1741,7 @@ em_force_mac_fc(struct em_hw *hw)
ctrl &= (~E1000_CTRL_TFCE);
E1000_WRITE_REG(hw, CTRL, ctrl);
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -1568,9 +1772,9 @@ em_config_fc_after_link_up(struct em_hw *hw)
* configuration of the MAC to match the "fc" parameter.
*/
if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
+ ((hw->media_type == em_media_type_internal_serdes) && (hw->autoneg_failed)) ||
((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
- ret_val = em_force_mac_fc(hw);
- if(ret_val < 0) {
+ if((ret_val = em_force_mac_fc(hw))) {
DEBUGOUT("Error forcing flow control settings\n");
return ret_val;
}
@@ -1586,14 +1790,10 @@ em_config_fc_after_link_up(struct em_hw *hw)
* has completed. We read this twice because this reg has
* some "sticky" (latched) bits.
*/
- if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
- DEBUGOUT("PHY Read Error \n");
- return -E1000_ERR_PHY;
- }
- if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
- DEBUGOUT("PHY Read Error \n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ return ret_val;
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ return ret_val;
if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
/* The AutoNeg process has completed, so we now need to
@@ -1602,14 +1802,12 @@ em_config_fc_after_link_up(struct em_hw *hw)
* Register (Address 5) to determine how flow control was
* negotiated.
*/
- if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if(em_read_phy_reg(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
+ &mii_nway_adv_reg)))
+ return ret_val;
+ if((ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
+ &mii_nway_lp_ability_reg)))
+ return ret_val;
/* Two bits in the Auto Negotiation Advertisement Register
* (Address 4) and two bits in the Auto Negotiation Base
@@ -1711,8 +1909,9 @@ em_config_fc_after_link_up(struct em_hw *hw)
* be asked to delay transmission of packets than asking
* our link partner to pause transmission of frames.
*/
- else if(hw->original_fc == em_fc_none ||
- hw->original_fc == em_fc_tx_pause) {
+ else if((hw->original_fc == em_fc_none ||
+ hw->original_fc == em_fc_tx_pause) ||
+ hw->fc_strict_ieee) {
hw->fc = em_fc_none;
DEBUGOUT("Flow Control = NONE.\r\n");
} else {
@@ -1724,7 +1923,10 @@ em_config_fc_after_link_up(struct em_hw *hw)
* negotiated to HALF DUPLEX, flow control should not be
* enabled per IEEE 802.3 spec.
*/
- em_get_speed_and_duplex(hw, &speed, &duplex);
+ if((ret_val = em_get_speed_and_duplex(hw, &speed, &duplex))) {
+ DEBUGOUT("Error getting link speed and duplex\n");
+ return ret_val;
+ }
if(duplex == HALF_DUPLEX)
hw->fc = em_fc_none;
@@ -1732,16 +1934,15 @@ em_config_fc_after_link_up(struct em_hw *hw)
/* Now we call a subroutine to actually force the MAC
* controller to use the correct flow control settings.
*/
- ret_val = em_force_mac_fc(hw);
- if(ret_val < 0) {
+ if((ret_val = em_force_mac_fc(hw))) {
DEBUGOUT("Error forcing flow control settings\n");
return ret_val;
- }
+ }
} else {
DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
}
}
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -1758,19 +1959,19 @@ em_check_for_link(struct em_hw *hw)
uint32_t ctrl;
uint32_t status;
uint32_t rctl;
- uint32_t signal;
+ uint32_t signal = 0;
int32_t ret_val;
uint16_t phy_data;
uint16_t lp_capability;
DEBUGFUNC("em_check_for_link");
- /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
+ /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
- * cleared when there is a signal
+ * cleared when there is a signal. This applies to fiber media only.
*/
- if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1;
- else signal = 0;
+ if(hw->media_type == em_media_type_fiber)
+ signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
ctrl = E1000_READ_REG(hw, CTRL);
status = E1000_READ_REG(hw, STATUS);
@@ -1788,14 +1989,10 @@ em_check_for_link(struct em_hw *hw)
* of the PHY.
* Read the register twice since the link bit is sticky.
*/
- if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ return ret_val;
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ return ret_val;
if(phy_data & MII_SR_LINK_STATUS) {
hw->get_link_status = FALSE;
@@ -1805,6 +2002,7 @@ em_check_for_link(struct em_hw *hw)
} else {
/* No link detected */
+ em_config_dsp_after_link_change(hw, FALSE);
return 0;
}
@@ -1813,6 +2011,9 @@ em_check_for_link(struct em_hw *hw)
*/
if(!hw->autoneg) return -E1000_ERR_CONFIG;
+ /* optimize the dsp settings for the igp phy */
+ em_config_dsp_after_link_change(hw, TRUE);
+
/* We have a M88E1000 PHY and Auto-Neg is enabled. If we
* have Si on board that is 82544 or newer, Auto
* Speed Detection takes care of MAC speed/duplex
@@ -1824,8 +2025,7 @@ em_check_for_link(struct em_hw *hw)
if(hw->mac_type >= em_82544)
em_config_collision_dist(hw);
else {
- ret_val = em_config_mac_to_phy(hw);
- if(ret_val < 0) {
+ if((ret_val = em_config_mac_to_phy(hw))) {
DEBUGOUT("Error configuring MAC to PHY settings\n");
return ret_val;
}
@@ -1835,8 +2035,7 @@ em_check_for_link(struct em_hw *hw)
* need to restore the desired flow control settings because we may
* have had to re-autoneg with a different link partner.
*/
- ret_val = em_config_fc_after_link_up(hw);
- if(ret_val < 0) {
+ if((ret_val = em_config_fc_after_link_up(hw))) {
DEBUGOUT("Error configuring flow control\n");
return ret_val;
}
@@ -1851,10 +2050,9 @@ em_check_for_link(struct em_hw *hw)
* partner is TBI-based, and we turn on TBI Compatibility.
*/
if(hw->tbi_compatibility_en) {
- if(em_read_phy_reg(hw, PHY_LP_ABILITY, &lp_capability) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
+ &lp_capability)))
+ return ret_val;
if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
NWAY_LPAR_10T_FD_CAPS |
NWAY_LPAR_100TX_HD_CAPS |
@@ -1892,9 +2090,10 @@ em_check_for_link(struct em_hw *hw)
* auto-negotiation time to complete, in case the cable was just plugged
* in. The autoneg_failed flag does this.
*/
- else if((hw->media_type == em_media_type_fiber) &&
+ else if((((hw->media_type == em_media_type_fiber) &&
+ ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
+ (hw->media_type == em_media_type_internal_serdes)) &&
(!(status & E1000_STATUS_LU)) &&
- ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
(!(rxcw & E1000_RXCW_C))) {
if(hw->autoneg_failed == 0) {
hw->autoneg_failed = 1;
@@ -1911,8 +2110,7 @@ em_check_for_link(struct em_hw *hw)
E1000_WRITE_REG(hw, CTRL, ctrl);
/* Configure Flow Control after forcing link up. */
- ret_val = em_config_fc_after_link_up(hw);
- if(ret_val < 0) {
+ if((ret_val = em_config_fc_after_link_up(hw))) {
DEBUGOUT("Error configuring flow control\n");
return ret_val;
}
@@ -1922,14 +2120,15 @@ em_check_for_link(struct em_hw *hw)
* Device Control register in an attempt to auto-negotiate with our link
* partner.
*/
- else if((hw->media_type == em_media_type_fiber) &&
+ else if(((hw->media_type == em_media_type_fiber) ||
+ (hw->media_type == em_media_type_internal_serdes)) &&
(ctrl & E1000_CTRL_SLU) &&
(rxcw & E1000_RXCW_C)) {
DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
E1000_WRITE_REG(hw, TXCW, hw->txcw);
E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
}
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -1939,12 +2138,14 @@ em_check_for_link(struct em_hw *hw)
* speed - Speed of the connection
* duplex - Duplex setting of the connection
*****************************************************************************/
-void
+int32_t
em_get_speed_and_duplex(struct em_hw *hw,
uint16_t *speed,
uint16_t *duplex)
{
uint32_t status;
+ int32_t ret_val;
+ uint16_t phy_data;
DEBUGFUNC("em_get_speed_and_duplex");
@@ -1973,6 +2174,27 @@ em_get_speed_and_duplex(struct em_hw *hw,
*speed = SPEED_1000;
*duplex = FULL_DUPLEX;
}
+
+ /* IGP01 PHY may advertise full duplex operation after speed downgrade even
+ * if it is operating at half duplex. Here we set the duplex settings to
+ * match the duplex in the link partner's capabilities.
+ */
+ if(hw->phy_type == em_phy_igp && hw->speed_downgraded) {
+ if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data)))
+ return ret_val;
+
+ if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
+ *duplex = HALF_DUPLEX;
+ else {
+ if((ret_val == em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data)))
+ return ret_val;
+ if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
+ (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
+ *duplex = HALF_DUPLEX;
+ }
+ }
+
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -1983,6 +2205,7 @@ em_get_speed_and_duplex(struct em_hw *hw,
int32_t
em_wait_autoneg(struct em_hw *hw)
{
+ int32_t ret_val;
uint16_t i;
uint16_t phy_data;
@@ -1994,20 +2217,16 @@ em_wait_autoneg(struct em_hw *hw)
/* Read the MII Status Register and wait for Auto-Neg
* Complete bit to be set.
*/
- if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ return ret_val;
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ return ret_val;
if(phy_data & MII_SR_AUTONEG_COMPLETE) {
- return 0;
+ return E1000_SUCCESS;
}
msec_delay(100);
}
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -2021,11 +2240,11 @@ em_raise_mdi_clk(struct em_hw *hw,
uint32_t *ctrl)
{
/* Raise the clock input to the Management Data Clock (by setting the MDC
- * bit), and then delay 2 microseconds.
+ * bit), and then delay 10 microseconds.
*/
E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
E1000_WRITE_FLUSH(hw);
- usec_delay(2);
+ usec_delay(10);
}
/******************************************************************************
@@ -2039,11 +2258,11 @@ em_lower_mdi_clk(struct em_hw *hw,
uint32_t *ctrl)
{
/* Lower the clock input to the Management Data Clock (by clearing the MDC
- * bit), and then delay 2 microseconds.
+ * bit), and then delay 10 microseconds.
*/
E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
E1000_WRITE_FLUSH(hw);
- usec_delay(2);
+ usec_delay(10);
}
/******************************************************************************
@@ -2087,7 +2306,7 @@ em_shift_out_mdi_bits(struct em_hw *hw,
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
- usec_delay(2);
+ usec_delay(10);
em_raise_mdi_clk(hw, &ctrl);
em_lower_mdi_clk(hw, &ctrl);
@@ -2149,8 +2368,8 @@ em_shift_in_mdi_bits(struct em_hw *hw)
}
/*****************************************************************************
-* Reads the value from a PHY register
-*
+* Reads the value from a PHY register, if the value is on a specific non zero
+* page, sets the page first.
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to read
******************************************************************************/
@@ -2159,11 +2378,33 @@ em_read_phy_reg(struct em_hw *hw,
uint32_t reg_addr,
uint16_t *phy_data)
{
+ uint32_t ret_val;
+
+ DEBUGFUNC("em_read_phy_reg");
+
+ if(hw->phy_type == em_phy_igp &&
+ (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+ if((ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+ (uint16_t)reg_addr)))
+ return ret_val;
+ }
+
+ ret_val = em_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
+ phy_data);
+
+ return ret_val;
+}
+
+int32_t
+em_read_phy_reg_ex(struct em_hw *hw,
+ uint32_t reg_addr,
+ uint16_t *phy_data)
+{
uint32_t i;
uint32_t mdic = 0;
const uint32_t phy_addr = 1;
- DEBUGFUNC("em_read_phy_reg");
+ DEBUGFUNC("em_read_phy_reg_ex");
if(reg_addr > MAX_PHY_REG_ADDRESS) {
DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
@@ -2183,7 +2424,7 @@ em_read_phy_reg(struct em_hw *hw,
/* Poll the ready bit to see if the MDI read completed */
for(i = 0; i < 64; i++) {
- usec_delay(10);
+ usec_delay(50);
mdic = E1000_READ_REG(hw, MDIC);
if(mdic & E1000_MDIC_READY) break;
}
@@ -2225,7 +2466,7 @@ em_read_phy_reg(struct em_hw *hw,
*/
*phy_data = em_shift_in_mdi_bits(hw);
}
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -2240,11 +2481,33 @@ em_write_phy_reg(struct em_hw *hw,
uint32_t reg_addr,
uint16_t phy_data)
{
+ uint32_t ret_val;
+
+ DEBUGFUNC("em_write_phy_reg");
+
+ if(hw->phy_type == em_phy_igp &&
+ (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+ if((ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+ (uint16_t)reg_addr)))
+ return ret_val;
+ }
+
+ ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
+ phy_data);
+
+ return ret_val;
+}
+
+int32_t
+em_write_phy_reg_ex(struct em_hw *hw,
+ uint32_t reg_addr,
+ uint16_t phy_data)
+{
uint32_t i;
uint32_t mdic = 0;
const uint32_t phy_addr = 1;
- DEBUGFUNC("em_write_phy_reg");
+ DEBUGFUNC("em_write_phy_reg_ex");
if(reg_addr > MAX_PHY_REG_ADDRESS) {
DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
@@ -2265,7 +2528,7 @@ em_write_phy_reg(struct em_hw *hw,
/* Poll the ready bit to see if the MDI read completed */
for(i = 0; i < 64; i++) {
- usec_delay(10);
+ usec_delay(50);
mdic = E1000_READ_REG(hw, MDIC);
if(mdic & E1000_MDIC_READY) break;
}
@@ -2295,7 +2558,7 @@ em_write_phy_reg(struct em_hw *hw,
em_shift_out_mdi_bits(hw, mdic, 32);
}
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -2340,11 +2603,6 @@ em_phy_hw_reset(struct em_hw *hw)
usec_delay(150);
if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
- if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0000) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return;
- }
-
/* Configure activity LED after PHY reset */
led_ctrl = E1000_READ_REG(hw, LEDCTL);
led_ctrl &= IGP_ACTIVITY_LED_MASK;
@@ -2363,24 +2621,26 @@ em_phy_hw_reset(struct em_hw *hw)
int32_t
em_phy_reset(struct em_hw *hw)
{
+ int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_phy_reset");
- if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- phy_data |= MII_CR_RESET;
- if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
- DEBUGOUT("PHY Write Error\n");
- return -E1000_ERR_PHY;
- }
- usec_delay(1);
- if (hw->phy_type == em_phy_igp) {
+ if(hw->mac_type != em_82541_rev_2) {
+ if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data)))
+ return ret_val;
+
+ phy_data |= MII_CR_RESET;
+ if((ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data)))
+ return ret_val;
+
+ usec_delay(1);
+ } else em_phy_hw_reset(hw);
+
+ if(hw->phy_type == em_phy_igp)
em_phy_init_script(hw);
- }
- return 0;
+
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -2391,23 +2651,21 @@ em_phy_reset(struct em_hw *hw)
int32_t
em_detect_gig_phy(struct em_hw *hw)
{
+ int32_t phy_init_status, ret_val;
uint16_t phy_id_high, phy_id_low;
boolean_t match = FALSE;
- int32_t phy_init_status;
DEBUGFUNC("em_detect_gig_phy");
/* Read the PHY ID Registers to identify which PHY is onboard. */
- if(em_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
+ return ret_val;
+
hw->phy_id = (uint32_t) (phy_id_high << 16);
usec_delay(20);
- if(em_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
+ return ret_val;
+
hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
@@ -2420,11 +2678,15 @@ em_detect_gig_phy(struct em_hw *hw)
break;
case em_82540:
case em_82545:
+ case em_82545_rev_3:
case em_82546:
+ case em_82546_rev_3:
if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
break;
case em_82541:
+ case em_82541_rev_2:
case em_82547:
+ case em_82547_rev_2:
if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
break;
default:
@@ -2435,7 +2697,7 @@ em_detect_gig_phy(struct em_hw *hw)
if ((match) && (phy_init_status == E1000_SUCCESS)) {
DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
- return 0;
+ return E1000_SUCCESS;
}
DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
return -E1000_ERR_PHY;
@@ -2449,17 +2711,16 @@ em_detect_gig_phy(struct em_hw *hw)
static int32_t
em_phy_reset_dsp(struct em_hw *hw)
{
- int32_t ret_val = -E1000_ERR_PHY;
+ int32_t ret_val;
DEBUGFUNC("em_phy_reset_dsp");
do {
- if(em_write_phy_reg(hw, 29, 0x001d) < 0) break;
- if(em_write_phy_reg(hw, 30, 0x00c1) < 0) break;
- if(em_write_phy_reg(hw, 30, 0x0000) < 0) break;
- ret_val = 0;
+ if((ret_val = em_write_phy_reg(hw, 29, 0x001d))) break;
+ if((ret_val = em_write_phy_reg(hw, 30, 0x00c1))) break;
+ if((ret_val = em_write_phy_reg(hw, 30, 0x0000))) break;
+ ret_val = E1000_SUCCESS;
} while(0);
- if(ret_val < 0) DEBUGOUT("PHY Write Error\n");
return ret_val;
}
@@ -2470,8 +2731,10 @@ em_phy_reset_dsp(struct em_hw *hw)
* phy_info - PHY information structure
******************************************************************************/
int32_t
-em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
+em_phy_igp_get_info(struct em_hw *hw,
+ struct em_phy_info *phy_info)
{
+ int32_t ret_val;
uint16_t phy_data, polarity, min_length, max_length, average;
DEBUGFUNC("em_phy_igp_get_info");
@@ -2487,13 +2750,14 @@ em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
phy_info->polarity_correction = em_polarity_reversal_enabled;
/* Check polarity status */
- if(em_check_polarity(hw, &polarity) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_check_polarity(hw, &polarity)))
+ return ret_val;
phy_info->cable_polarity = polarity;
- if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
+ &phy_data)))
+ return ret_val;
phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
IGP01E1000_PSSR_MDIX_SHIFT;
@@ -2501,8 +2765,8 @@ em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
IGP01E1000_PSSR_SPEED_1000MBPS) {
/* Local/Remote Receiver Information are only valid at 1000 Mbps */
- if(em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
+ return ret_val;
phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
SR_1000T_LOCAL_RX_STATUS_SHIFT;
@@ -2510,8 +2774,8 @@ em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
SR_1000T_REMOTE_RX_STATUS_SHIFT;
/* Get cable length */
- if(em_get_cable_length(hw, &min_length, &max_length) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_get_cable_length(hw, &min_length, &max_length)))
+ return ret_val;
/* transalte to old method */
average = (max_length + min_length) / 2;
@@ -2538,8 +2802,10 @@ em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
* phy_info - PHY information structure
******************************************************************************/
int32_t
-em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
+em_phy_m88_get_info(struct em_hw *hw,
+ struct em_phy_info *phy_info)
{
+ int32_t ret_val;
uint16_t phy_data, polarity;
DEBUGFUNC("em_phy_m88_get_info");
@@ -2548,8 +2814,8 @@ em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
* and it stored in the hw->speed_downgraded parameter. */
phy_info->downshift = hw->speed_downgraded;
- if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data)))
+ return ret_val;
phy_info->extended_10bt_distance =
(phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
@@ -2559,13 +2825,13 @@ em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
/* Check polarity status */
- if(em_check_polarity(hw, &polarity) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_check_polarity(hw, &polarity)))
+ return ret_val;
phy_info->cable_polarity = polarity;
- if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data)))
+ return ret_val;
phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
M88E1000_PSSR_MDIX_SHIFT;
@@ -2577,8 +2843,8 @@ em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
M88E1000_PSSR_CABLE_LENGTH_SHIFT);
- if(em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
+ return ret_val;
phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
SR_1000T_LOCAL_RX_STATUS_SHIFT;
@@ -2600,6 +2866,7 @@ int32_t
em_phy_get_info(struct em_hw *hw,
struct em_phy_info *phy_info)
{
+ int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_phy_get_info");
@@ -2618,20 +2885,18 @@ em_phy_get_info(struct em_hw *hw,
return -E1000_ERR_CONFIG;
}
- if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ return ret_val;
+
+ if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ return ret_val;
+
if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
DEBUGOUT("PHY info is only valid if link is up\n");
return -E1000_ERR_CONFIG;
}
- if (hw->phy_type == em_phy_igp)
+ if(hw->phy_type == em_phy_igp)
return em_phy_igp_get_info(hw, phy_info);
else
return em_phy_m88_get_info(hw, phy_info);
@@ -2647,7 +2912,7 @@ em_validate_mdi_setting(struct em_hw *hw)
hw->mdix = 1;
return -E1000_ERR_CONFIG;
}
- return 0;
+ return E1000_SUCCESS;
}
@@ -2679,7 +2944,9 @@ em_init_eeprom_params(struct em_hw *hw)
break;
case em_82540:
case em_82545:
+ case em_82545_rev_3:
case em_82546:
+ case em_82546_rev_3:
eeprom->type = em_eeprom_microwire;
eeprom->opcode_bits = 3;
eeprom->delay_usec = 50;
@@ -2692,8 +2959,9 @@ em_init_eeprom_params(struct em_hw *hw)
}
break;
case em_82541:
+ case em_82541_rev_2:
case em_82547:
- default:
+ case em_82547_rev_2:
if (eecd & E1000_EECD_TYPE) {
eeprom->type = em_eeprom_spi;
eeprom->opcode_bits = 8;
@@ -2718,6 +2986,18 @@ em_init_eeprom_params(struct em_hw *hw)
}
}
break;
+ default:
+ eeprom->type = em_eeprom_spi;
+ eeprom->opcode_bits = 8;
+ eeprom->delay_usec = 1;
+ if (eecd & E1000_EECD_ADDR_BITS) {
+ eeprom->page_size = 32;
+ eeprom->address_bits = 16;
+ } else {
+ eeprom->page_size = 8;
+ eeprom->address_bits = 8;
+ }
+ break;
}
if (eeprom->type == em_eeprom_spi) {
@@ -2726,28 +3006,28 @@ em_init_eeprom_params(struct em_hw *hw)
eeprom_size &= EEPROM_SIZE_MASK;
switch (eeprom_size) {
- case EEPROM_SIZE_16KB:
- eeprom->word_size = 8192;
- break;
- case EEPROM_SIZE_8KB:
- eeprom->word_size = 4096;
- break;
- case EEPROM_SIZE_4KB:
- eeprom->word_size = 2048;
- break;
- case EEPROM_SIZE_2KB:
- eeprom->word_size = 1024;
- break;
- case EEPROM_SIZE_1KB:
- eeprom->word_size = 512;
- break;
- case EEPROM_SIZE_512B:
- eeprom->word_size = 256;
- break;
- case EEPROM_SIZE_128B:
- default:
- eeprom->word_size = 64;
- break;
+ case EEPROM_SIZE_16KB:
+ eeprom->word_size = 8192;
+ break;
+ case EEPROM_SIZE_8KB:
+ eeprom->word_size = 4096;
+ break;
+ case EEPROM_SIZE_4KB:
+ eeprom->word_size = 2048;
+ break;
+ case EEPROM_SIZE_2KB:
+ eeprom->word_size = 1024;
+ break;
+ case EEPROM_SIZE_1KB:
+ eeprom->word_size = 512;
+ break;
+ case EEPROM_SIZE_512B:
+ eeprom->word_size = 256;
+ break;
+ case EEPROM_SIZE_128B:
+ default:
+ eeprom->word_size = 64;
+ break;
}
}
}
@@ -2852,7 +3132,8 @@ em_shift_out_ee_bits(struct em_hw *hw,
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static uint16_t
-em_shift_in_ee_bits(struct em_hw *hw, uint16_t count)
+em_shift_in_ee_bits(struct em_hw *hw,
+ uint16_t count)
{
uint32_t eecd;
uint32_t i;
@@ -3112,13 +3393,17 @@ em_read_eeprom(struct em_hw *hw,
}
/* Prepare the EEPROM for reading */
- if (em_acquire_eeprom(hw) != E1000_SUCCESS)
+ if(em_acquire_eeprom(hw) != E1000_SUCCESS)
return -E1000_ERR_EEPROM;
if(eeprom->type == em_eeprom_spi) {
+ uint16_t word_in;
uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
- if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
+ if(em_spi_eeprom_ready(hw)) {
+ em_release_eeprom(hw);
+ return -E1000_ERR_EEPROM;
+ }
em_standby_eeprom(hw);
@@ -3129,30 +3414,35 @@ em_read_eeprom(struct em_hw *hw,
/* Send the READ command (opcode + addr) */
em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
- }
- else if(eeprom->type == em_eeprom_microwire) {
- /* Send the READ command (opcode + addr) */
- em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
- eeprom->opcode_bits);
- em_shift_out_ee_bits(hw, offset, eeprom->address_bits);
- }
- /* Read the data. The address of the eeprom internally increments with
- * each word (microwire) or byte (spi) being read, saving on the overhead
- * of eeprom setup and tear-down. The address counter will roll over if
- * reading beyond the size of the eeprom, thus allowing the entire memory
- * to be read starting from any offset. */
- for (i = 0; i < words; i++) {
- uint16_t word_in = em_shift_in_ee_bits(hw, 16);
- if (eeprom->type == em_eeprom_spi)
- word_in = (word_in >> 8) | (word_in << 8);
- data[i] = word_in;
+ /* Read the data. The address of the eeprom internally increments with
+ * each byte (spi) being read, saving on the overhead of eeprom setup
+ * and tear-down. The address counter will roll over if reading beyond
+ * the size of the eeprom, thus allowing the entire memory to be read
+ * starting from any offset. */
+ for (i = 0; i < words; i++) {
+ word_in = em_shift_in_ee_bits(hw, 16);
+ data[i] = (word_in >> 8) | (word_in << 8);
+ }
+ } else if(eeprom->type == em_eeprom_microwire) {
+ for (i = 0; i < words; i++) {
+ /* Send the READ command (opcode + addr) */
+ em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
+ eeprom->opcode_bits);
+ em_shift_out_ee_bits(hw, (uint16_t)(offset + i),
+ eeprom->address_bits);
+
+ /* Read the data. For microwire, each word requires the overhead
+ * of eeprom setup and tear-down. */
+ data[i] = em_shift_in_ee_bits(hw, 16);
+ em_standby_eeprom(hw);
+ }
}
/* End this read operation */
em_release_eeprom(hw);
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -3180,9 +3470,9 @@ em_validate_eeprom_checksum(struct em_hw *hw)
checksum += eeprom_data;
}
- if(checksum == (uint16_t) EEPROM_SUM) {
- return 0;
- } else {
+ if(checksum == (uint16_t) EEPROM_SUM)
+ return E1000_SUCCESS;
+ else {
DEBUGOUT("EEPROM Checksum Invalid\n");
return -E1000_ERR_EEPROM;
}
@@ -3216,7 +3506,7 @@ em_update_eeprom_checksum(struct em_hw *hw)
DEBUGOUT("EEPROM Write Error\n");
return -E1000_ERR_EEPROM;
}
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -3414,7 +3704,7 @@ em_write_eeprom_microwire(struct em_hw *hw,
em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -3448,7 +3738,7 @@ em_read_part_num(struct em_hw *hw,
/* Save word 1 in lower half of part_num */
*part_num |= eeprom_data;
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -3474,7 +3764,7 @@ em_read_mac_addr(struct em_hw * hw)
hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
}
- if((hw->mac_type == em_82546) &&
+ if(((hw->mac_type == em_82546) || (hw->mac_type == em_82546_rev_3)) &&
(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
if(hw->perm_mac_addr[5] & 0x01)
hw->perm_mac_addr[5] &= ~(0x01);
@@ -3483,7 +3773,7 @@ em_read_mac_addr(struct em_hw * hw)
}
for(i = 0; i < NODE_ADDRESS_SIZE; i++)
hw->mac_addr[i] = hw->perm_mac_addr[i];
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -3759,7 +4049,7 @@ em_id_led_init(struct em_hw * hw)
if(hw->mac_type < em_82540) {
/* Nothing to do */
- return 0;
+ return E1000_SUCCESS;
}
ledctl = E1000_READ_REG(hw, LEDCTL);
@@ -3810,7 +4100,7 @@ em_id_led_init(struct em_hw * hw)
break;
}
}
- return 0;
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -3822,49 +4112,48 @@ int32_t
em_setup_led(struct em_hw *hw)
{
uint32_t ledctl;
+ int32_t ret_val = E1000_SUCCESS;
DEBUGFUNC("em_setup_led");
- switch(hw->device_id) {
- case E1000_DEV_ID_82542:
- case E1000_DEV_ID_82543GC_FIBER:
- case E1000_DEV_ID_82543GC_COPPER:
- case E1000_DEV_ID_82544EI_COPPER:
- case E1000_DEV_ID_82544EI_FIBER:
- case E1000_DEV_ID_82544GC_COPPER:
- case E1000_DEV_ID_82544GC_LOM:
+ switch(hw->mac_type) {
+ case em_82542_rev2_0:
+ case em_82542_rev2_1:
+ case em_82543:
+ case em_82544:
/* No setup necessary */
break;
- case E1000_DEV_ID_82545EM_FIBER:
- case E1000_DEV_ID_82546EB_FIBER:
- ledctl = E1000_READ_REG(hw, LEDCTL);
- /* Save current LEDCTL settings */
- hw->ledctl_default = ledctl;
- /* Turn off LED0 */
- ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
- E1000_LEDCTL_LED0_BLINK |
- E1000_LEDCTL_LED0_MODE_MASK);
- ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT);
- E1000_WRITE_REG(hw, LEDCTL, ledctl);
- break;
- case E1000_DEV_ID_82540EP:
- case E1000_DEV_ID_82540EP_LOM:
- case E1000_DEV_ID_82540EP_LP:
- case E1000_DEV_ID_82540EM:
- case E1000_DEV_ID_82540EM_LOM:
- case E1000_DEV_ID_82545EM_COPPER:
- case E1000_DEV_ID_82546EB_COPPER:
- case E1000_DEV_ID_82546EB_QUAD_COPPER:
- case E1000_DEV_ID_82541EI:
- case E1000_DEV_ID_82541EP:
- case E1000_DEV_ID_82547EI:
- E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
- break;
+ case em_82541:
+ case em_82547:
+ case em_82541_rev_2:
+ case em_82547_rev_2:
+ /* Turn off PHY Smart Power Down (if enabled) */
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ &hw->phy_spd_default)))
+ return ret_val;
+ if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ (uint16_t)(hw->phy_spd_default &
+ ~IGP01E1000_GMII_SPD))))
+ return ret_val;
+ /* Fall Through */
default:
- DEBUGOUT("Invalid device ID\n");
- return -E1000_ERR_CONFIG;
+ if(hw->media_type == em_media_type_fiber) {
+ ledctl = E1000_READ_REG(hw, LEDCTL);
+ /* Save current LEDCTL settings */
+ hw->ledctl_default = ledctl;
+ /* Turn off LED0 */
+ ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
+ E1000_LEDCTL_LED0_BLINK |
+ E1000_LEDCTL_LED0_MODE_MASK);
+ ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
+ E1000_LEDCTL_LED0_MODE_SHIFT);
+ E1000_WRITE_REG(hw, LEDCTL, ledctl);
+ } else if(hw->media_type == em_media_type_copper)
+ E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
+ break;
}
- return 0;
+
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -3875,39 +4164,33 @@ em_setup_led(struct em_hw *hw)
int32_t
em_cleanup_led(struct em_hw *hw)
{
+ int32_t ret_val = E1000_SUCCESS;
+
DEBUGFUNC("em_cleanup_led");
- switch(hw->device_id) {
- case E1000_DEV_ID_82542:
- case E1000_DEV_ID_82543GC_FIBER:
- case E1000_DEV_ID_82543GC_COPPER:
- case E1000_DEV_ID_82544EI_COPPER:
- case E1000_DEV_ID_82544EI_FIBER:
- case E1000_DEV_ID_82544GC_COPPER:
- case E1000_DEV_ID_82544GC_LOM:
+ switch(hw->mac_type) {
+ case em_82542_rev2_0:
+ case em_82542_rev2_1:
+ case em_82543:
+ case em_82544:
/* No cleanup necessary */
break;
- case E1000_DEV_ID_82540EP:
- case E1000_DEV_ID_82540EP_LOM:
- case E1000_DEV_ID_82540EP_LP:
- case E1000_DEV_ID_82540EM:
- case E1000_DEV_ID_82540EM_LOM:
- case E1000_DEV_ID_82545EM_COPPER:
- case E1000_DEV_ID_82545EM_FIBER:
- case E1000_DEV_ID_82546EB_COPPER:
- case E1000_DEV_ID_82546EB_FIBER:
- case E1000_DEV_ID_82546EB_QUAD_COPPER:
- case E1000_DEV_ID_82541EI:
- case E1000_DEV_ID_82541EP:
- case E1000_DEV_ID_82547EI:
+ case em_82541:
+ case em_82547:
+ case em_82541_rev_2:
+ case em_82547_rev_2:
+ /* Turn on PHY Smart Power Down (if previously enabled) */
+ if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ hw->phy_spd_default)))
+ return ret_val;
+ /* Fall Through */
+ default:
/* Restore LEDCTL settings */
E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
break;
- default:
- DEBUGOUT("Invalid device ID\n");
- return -E1000_ERR_CONFIG;
}
- return 0;
+
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -3918,50 +4201,44 @@ em_cleanup_led(struct em_hw *hw)
int32_t
em_led_on(struct em_hw *hw)
{
- uint32_t ctrl;
+ uint32_t ctrl = E1000_READ_REG(hw, CTRL);
DEBUGFUNC("em_led_on");
- switch(hw->device_id) {
- case E1000_DEV_ID_82542:
- case E1000_DEV_ID_82543GC_FIBER:
- case E1000_DEV_ID_82543GC_COPPER:
- case E1000_DEV_ID_82544EI_FIBER:
- ctrl = E1000_READ_REG(hw, CTRL);
+ switch(hw->mac_type) {
+ case em_82542_rev2_0:
+ case em_82542_rev2_1:
+ case em_82543:
/* Set SW Defineable Pin 0 to turn on the LED */
ctrl |= E1000_CTRL_SWDPIN0;
ctrl |= E1000_CTRL_SWDPIO0;
- E1000_WRITE_REG(hw, CTRL, ctrl);
break;
- case E1000_DEV_ID_82544EI_COPPER:
- case E1000_DEV_ID_82544GC_COPPER:
- case E1000_DEV_ID_82544GC_LOM:
- case E1000_DEV_ID_82545EM_FIBER:
- case E1000_DEV_ID_82546EB_FIBER:
- ctrl = E1000_READ_REG(hw, CTRL);
- /* Clear SW Defineable Pin 0 to turn on the LED */
- ctrl &= ~E1000_CTRL_SWDPIN0;
- ctrl |= E1000_CTRL_SWDPIO0;
- E1000_WRITE_REG(hw, CTRL, ctrl);
- break;
- case E1000_DEV_ID_82540EP:
- case E1000_DEV_ID_82540EP_LOM:
- case E1000_DEV_ID_82540EP_LP:
- case E1000_DEV_ID_82540EM:
- case E1000_DEV_ID_82540EM_LOM:
- case E1000_DEV_ID_82545EM_COPPER:
- case E1000_DEV_ID_82546EB_COPPER:
- case E1000_DEV_ID_82546EB_QUAD_COPPER:
- case E1000_DEV_ID_82541EI:
- case E1000_DEV_ID_82541EP:
- case E1000_DEV_ID_82547EI:
- E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
+ case em_82544:
+ if(hw->media_type == em_media_type_fiber) {
+ /* Set SW Defineable Pin 0 to turn on the LED */
+ ctrl |= E1000_CTRL_SWDPIN0;
+ ctrl |= E1000_CTRL_SWDPIO0;
+ } else {
+ /* Clear SW Defineable Pin 0 to turn on the LED */
+ ctrl &= ~E1000_CTRL_SWDPIN0;
+ ctrl |= E1000_CTRL_SWDPIO0;
+ }
break;
default:
- DEBUGOUT("Invalid device ID\n");
- return -E1000_ERR_CONFIG;
+ if(hw->media_type == em_media_type_fiber) {
+ /* Clear SW Defineable Pin 0 to turn on the LED */
+ ctrl &= ~E1000_CTRL_SWDPIN0;
+ ctrl |= E1000_CTRL_SWDPIO0;
+ } else if(hw->media_type == em_media_type_copper) {
+ E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
+ return E1000_SUCCESS;
+ }
+ break;
}
- return 0;
+
+ E1000_WRITE_REG(hw, CTRL, ctrl);
+
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -3972,50 +4249,44 @@ em_led_on(struct em_hw *hw)
int32_t
em_led_off(struct em_hw *hw)
{
- uint32_t ctrl;
+ uint32_t ctrl = E1000_READ_REG(hw, CTRL);
DEBUGFUNC("em_led_off");
- switch(hw->device_id) {
- case E1000_DEV_ID_82542:
- case E1000_DEV_ID_82543GC_FIBER:
- case E1000_DEV_ID_82543GC_COPPER:
- case E1000_DEV_ID_82544EI_FIBER:
- ctrl = E1000_READ_REG(hw, CTRL);
+ switch(hw->mac_type) {
+ case em_82542_rev2_0:
+ case em_82542_rev2_1:
+ case em_82543:
/* Clear SW Defineable Pin 0 to turn off the LED */
ctrl &= ~E1000_CTRL_SWDPIN0;
ctrl |= E1000_CTRL_SWDPIO0;
- E1000_WRITE_REG(hw, CTRL, ctrl);
break;
- case E1000_DEV_ID_82544EI_COPPER:
- case E1000_DEV_ID_82544GC_COPPER:
- case E1000_DEV_ID_82544GC_LOM:
- case E1000_DEV_ID_82545EM_FIBER:
- case E1000_DEV_ID_82546EB_FIBER:
- ctrl = E1000_READ_REG(hw, CTRL);
- /* Set SW Defineable Pin 0 to turn off the LED */
- ctrl |= E1000_CTRL_SWDPIN0;
- ctrl |= E1000_CTRL_SWDPIO0;
- E1000_WRITE_REG(hw, CTRL, ctrl);
- break;
- case E1000_DEV_ID_82540EP:
- case E1000_DEV_ID_82540EP_LOM:
- case E1000_DEV_ID_82540EP_LP:
- case E1000_DEV_ID_82540EM:
- case E1000_DEV_ID_82540EM_LOM:
- case E1000_DEV_ID_82545EM_COPPER:
- case E1000_DEV_ID_82546EB_COPPER:
- case E1000_DEV_ID_82546EB_QUAD_COPPER:
- case E1000_DEV_ID_82541EI:
- case E1000_DEV_ID_82541EP:
- case E1000_DEV_ID_82547EI:
- E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
+ case em_82544:
+ if(hw->media_type == em_media_type_fiber) {
+ /* Clear SW Defineable Pin 0 to turn off the LED */
+ ctrl &= ~E1000_CTRL_SWDPIN0;
+ ctrl |= E1000_CTRL_SWDPIO0;
+ } else {
+ /* Set SW Defineable Pin 0 to turn off the LED */
+ ctrl |= E1000_CTRL_SWDPIN0;
+ ctrl |= E1000_CTRL_SWDPIO0;
+ }
break;
default:
- DEBUGOUT("Invalid device ID\n");
- return -E1000_ERR_CONFIG;
+ if(hw->media_type == em_media_type_fiber) {
+ /* Set SW Defineable Pin 0 to turn off the LED */
+ ctrl |= E1000_CTRL_SWDPIN0;
+ ctrl |= E1000_CTRL_SWDPIO0;
+ } else if(hw->media_type == em_media_type_copper) {
+ E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
+ return E1000_SUCCESS;
+ }
+ break;
}
- return 0;
+
+ E1000_WRITE_REG(hw, CTRL, ctrl);
+
+ return E1000_SUCCESS;
}
/******************************************************************************
@@ -4138,8 +4409,7 @@ em_update_adaptive(struct em_hw *hw)
DEBUGFUNC("em_update_adaptive");
if(hw->adaptive_ifs) {
- if((hw->collision_delta * hw->ifs_ratio) >
- hw->tx_packet_delta) {
+ if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
if(hw->tx_packet_delta > MIN_NUM_XMITS) {
hw->in_ifs_mode = TRUE;
if(hw->current_ifs_val < hw->ifs_max_val) {
@@ -4151,8 +4421,7 @@ em_update_adaptive(struct em_hw *hw)
}
}
} else {
- if((hw->in_ifs_mode == TRUE) &&
- (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
+ if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
hw->current_ifs_val = 0;
hw->in_ifs_mode = FALSE;
E1000_WRITE_REG(hw, AIT, 0);
@@ -4335,7 +4604,8 @@ em_write_reg_io(struct em_hw *hw,
* min_length - The estimated minimum length
* max_length - The estimated maximum length
*
- * returns: E1000_SUCCESS / -E1000_ERR_XXX
+ * returns: - E1000_ERR_XXX
+ * E1000_SUCCESS
*
* This function always returns a ranged length (minimum & maximum).
* So for M88 phy's, this function interprets the one value returned from the
@@ -4343,9 +4613,11 @@ em_write_reg_io(struct em_hw *hw,
* For IGP phy's, the function calculates the range by the AGC registers.
*****************************************************************************/
int32_t
-em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
+em_get_cable_length(struct em_hw *hw,
+ uint16_t *min_length,
uint16_t *max_length)
{
+ int32_t ret_val;
uint16_t agc_value = 0;
uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
uint16_t i, phy_data;
@@ -4356,8 +4628,9 @@ em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
/* Use old method for Phy older than IGP */
if(hw->phy_type == em_phy_m88) {
- if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data)))
+ return ret_val;
/* Convert the enum value to ranged values */
switch((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
@@ -4387,19 +4660,16 @@ em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
break;
}
} else if(hw->phy_type == em_phy_igp) { /* For IGP PHY */
- uint16_t agc_reg_array[IGP01E1000_PHY_AGC_NUM] = {IGP01E1000_PHY_AGC_A,
+ uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
+ {IGP01E1000_PHY_AGC_A,
IGP01E1000_PHY_AGC_B,
IGP01E1000_PHY_AGC_C,
IGP01E1000_PHY_AGC_D};
/* Read the AGC registers for all channels */
- for(i = 0; i < IGP01E1000_PHY_AGC_NUM; i++) {
- if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
- agc_reg_array[i]) != E1000_SUCCESS)
- return -E1000_ERR_PHY;
- if(em_read_phy_reg(hw, agc_reg_array[i] &
- IGP01E1000_PHY_PAGE_SELECT, &phy_data) !=
- E1000_SUCCESS)
- return -E1000_ERR_PHY;
+ for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+
+ if((ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data)))
+ return ret_val;
cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
@@ -4415,20 +4685,15 @@ em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
min_agc = cur_agc;
}
- /* Return to page 0 */
- if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0) !=
- E1000_SUCCESS)
- return -E1000_ERR_PHY;
-
/* Remove the minimal AGC result for length < 50m */
- if(agc_value < IGP01E1000_PHY_AGC_NUM * em_igp_cable_length_50) {
+ if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) {
agc_value -= min_agc;
/* Get the average length of the remaining 3 channels */
- agc_value /= (IGP01E1000_PHY_AGC_NUM - 1);
+ agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
} else {
/* Get the average length of all the 4 channels. */
- agc_value /= IGP01E1000_PHY_AGC_NUM;
+ agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
}
/* Set the range of the calculated length. */
@@ -4450,7 +4715,8 @@ em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
* polarity - output parameter : 0 - Polarity is not reversed
* 1 - Polarity is reversed.
*
- * returns: E1000_SUCCESS / -E1000_ERR_XXX
+ * returns: - E1000_ERR_XXX
+ * E1000_SUCCESS
*
* For phy's older then IGP, this function simply reads the polarity bit in the
* Phy Status register. For IGP phy's, this bit is valid only if link speed is
@@ -4459,22 +4725,26 @@ em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
* IGP01E1000_PHY_PCS_INIT_REG.
*****************************************************************************/
int32_t
-em_check_polarity(struct em_hw *hw, uint16_t *polarity)
+em_check_polarity(struct em_hw *hw,
+ uint16_t *polarity)
{
+ int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_check_polarity");
if(hw->phy_type == em_phy_m88) {
/* return the Polarity bit in the Status register. */
- if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data)))
+ return ret_val;
*polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
M88E1000_PSSR_REV_POLARITY_SHIFT;
} else if(hw->phy_type == em_phy_igp) {
/* Read the Status register to check the speed */
- if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0)
- return -E1000_ERR_PHY;
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
+ &phy_data)))
+ return ret_val;
/* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
* find the polarity status */
@@ -4482,18 +4752,9 @@ em_check_polarity(struct em_hw *hw, uint16_t *polarity)
IGP01E1000_PSSR_SPEED_1000MBPS) {
/* Read the GIG initialization PCS register (0x00B4) */
- if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
- IGP01E1000_PHY_PCS_INIT_REG) < 0)
- return -E1000_ERR_PHY;
-
- if(em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG &
- IGP01E1000_PHY_PAGE_SELECT, &phy_data) < 0)
- return -E1000_ERR_PHY;
-
- /* Return to page 0 */
- if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0) !=
- E1000_SUCCESS)
- return -E1000_ERR_PHY;
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
+ &phy_data)))
+ return ret_val;
/* Check the polarity bits */
*polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
@@ -4513,7 +4774,8 @@ em_check_polarity(struct em_hw *hw, uint16_t *polarity)
* downshift - output parameter : 0 - No Downshift ocured.
* 1 - Downshift ocured.
*
- * returns: E1000_SUCCESS / -E1000_ERR_XXX
+ * returns: - E1000_ERR_XXX
+ * E1000_SUCCESS
*
* For phy's older then IGP, this function reads the Downshift bit in the Phy
* Specific Status register. For IGP phy's, it reads the Downgrade bit in the
@@ -4523,25 +4785,287 @@ em_check_polarity(struct em_hw *hw, uint16_t *polarity)
int32_t
em_check_downshift(struct em_hw *hw)
{
+ int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC("em_check_downshift");
if(hw->phy_type == em_phy_igp) {
- if(em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
+ &phy_data)))
+ return ret_val;
+
hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
}
else if(hw->phy_type == em_phy_m88) {
- if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data)))
+ return ret_val;
+
hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
- M88E1000_PSSR_DOWNSHIFT_SHIFT;
+ M88E1000_PSSR_DOWNSHIFT_SHIFT;
+ }
+ return E1000_SUCCESS;
+}
+
+/*****************************************************************************
+ *
+ * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
+ * gigabit link is achieved to improve link quality.
+ *
+ * hw: Struct containing variables accessed by shared code
+ *
+ * returns: - E1000_ERR_PHY if fail to read/write the PHY
+ * E1000_SUCCESS at any other case.
+ *
+ ****************************************************************************/
+
+int32_t
+em_config_dsp_after_link_change(struct em_hw *hw,
+ boolean_t link_up)
+{
+ int32_t ret_val;
+ uint16_t phy_data, speed, duplex, i;
+ uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
+ {IGP01E1000_PHY_AGC_PARAM_A,
+ IGP01E1000_PHY_AGC_PARAM_B,
+ IGP01E1000_PHY_AGC_PARAM_C,
+ IGP01E1000_PHY_AGC_PARAM_D};
+ uint16_t min_length, max_length;
+
+ DEBUGFUNC("em_config_dsp_after_link_change");
+
+ if(hw->phy_type != em_phy_igp)
+ return E1000_SUCCESS;
+
+ if(link_up) {
+ if((ret_val = em_get_speed_and_duplex(hw, &speed, &duplex))) {
+ DEBUGOUT("Error getting link speed and duplex\n");
+ return ret_val;
+ }
+
+ if(speed == SPEED_1000) {
+
+ em_get_cable_length(hw, &min_length, &max_length);
+
+ if((hw->dsp_config_state == em_dsp_config_enabled) &&
+ min_length >= em_igp_cable_length_50) {
+
+ for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+ if((ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
+ &phy_data)))
+ return ret_val;
+
+ phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
+
+ if((ret_val = em_write_phy_reg(hw, dsp_reg_array[i],
+ phy_data)))
+ return ret_val;
+ }
+ hw->dsp_config_state = em_dsp_config_activated;
+ }
+
+ if((hw->ffe_config_state == em_ffe_config_enabled) &&
+ (min_length < em_igp_cable_length_50)) {
+
+ uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
+ uint32_t idle_errs = 0;
+
+ /* clear previous idle error counts */
+ if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
+ &phy_data)))
+ return ret_val;
+
+ for(i = 0; i < ffe_idle_err_timeout; i++) {
+ usec_delay(1000);
+ if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
+ &phy_data)))
+ return ret_val;
+
+ idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
+ if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
+ hw->ffe_config_state = em_ffe_config_active;
+
+ if((ret_val = em_write_phy_reg(hw,
+ IGP01E1000_PHY_DSP_FFE,
+ IGP01E1000_PHY_DSP_FFE_CM_CP)))
+ return ret_val;
+ break;
+ }
+
+ if(idle_errs)
+ ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
+ }
+ }
+ }
+ } else {
+ if(hw->dsp_config_state == em_dsp_config_activated) {
+ if((ret_val = em_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_FORCE_GIGA)))
+ return ret_val;
+ for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+ if((ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
+ &phy_data)))
+ return ret_val;
+
+ phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
+ phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
+
+ if((ret_val = em_write_phy_reg(hw,dsp_reg_array[i],
+ phy_data)))
+ return ret_val;
+ }
+
+ if((ret_val = em_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_RESTART_AUTONEG)))
+ return ret_val;
+
+ hw->dsp_config_state = em_dsp_config_enabled;
+ }
+
+ if(hw->ffe_config_state == em_ffe_config_active) {
+ if((ret_val = em_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_FORCE_GIGA)))
+ return ret_val;
+ if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
+ IGP01E1000_PHY_DSP_FFE_DEFAULT)))
+ return ret_val;
+
+ if((ret_val = em_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_RESTART_AUTONEG)))
+ return ret_val;
+ hw->ffe_config_state = em_ffe_config_enabled;
+ }
+ }
+ return E1000_SUCCESS;
+}
+
+/*****************************************************************************
+ *
+ * This function sets the lplu state according to the active flag. When
+ * activating lplu this function also disables smart speed and vise versa.
+ * lplu will not be activated unless the device autonegotiation advertisment
+ * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
+ * hw: Struct containing variables accessed by shared code
+ * active - true to enable lplu false to disable lplu.
+ *
+ * returns: - E1000_ERR_PHY if fail to read/write the PHY
+ * E1000_SUCCESS at any other case.
+ *
+ ****************************************************************************/
+
+int32_t
+em_set_d3_lplu_state(struct em_hw *hw,
+ boolean_t active)
+{
+ int32_t ret_val;
+ uint16_t phy_data;
+ DEBUGFUNC("em_set_d3_lplu_state");
+
+ if(!((hw->mac_type == em_82541_rev_2) ||
+ (hw->mac_type == em_82547_rev_2)))
+ return E1000_SUCCESS;
+
+ /* During driver activity LPLU should not be used or it will attain link
+ * from the lowest speeds starting from 10Mbps. The capability is used for
+ * Dx transitions and states */
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data)))
+ return ret_val;
+
+ if(!active) {
+ phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
+ if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
+ return ret_val;
+
+ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
+ * Dx states where the power conservation is most important. During
+ * driver activity we should enable SmartSpeed, so performance is
+ * maintained. */
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+ &phy_data)))
+ return ret_val;
+
+ phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
+ if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+ phy_data)))
+ return ret_val;
+
+ } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
+ (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
+ (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
+
+ phy_data |= IGP01E1000_GMII_FLEX_SPD;
+ if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
+ return ret_val;
+
+ /* When LPLU is enabled we should disable SmartSpeed */
+ if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+ &phy_data)))
+ return ret_val;
+
+ phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+ if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+ phy_data)))
+ return ret_val;
+
+ }
+ return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * Change VCO speed register to improve Bit Error Rate performance of SERDES.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static int32_t
+em_set_vco_speed(struct em_hw *hw)
+{
+ int32_t ret_val;
+ uint16_t default_page = 0;
+ uint16_t phy_data;
+
+ DEBUGFUNC("em_set_vco_speed");
+
+ switch(hw->mac_type) {
+ case em_82545_rev_3:
+ case em_82546_rev_3:
+ break;
+ default:
+ return E1000_SUCCESS;
}
+
+ /* Set PHY register 30, page 5, bit 8 to 0 */
+
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
+ &default_page)))
+ return ret_val;
+
+ if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005)))
+ return ret_val;
+
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
+ return ret_val;
+
+ phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
+ if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
+ return ret_val;
+
+ /* Set PHY register 30, page 4, bit 11 to 1 */
+
+ if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004)))
+ return ret_val;
+
+ if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
+ return ret_val;
+
+ phy_data |= M88E1000_PHY_VCO_REG_BIT11;
+ if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
+ return ret_val;
+
+ if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
+ default_page)))
+ return ret_val;
+
return E1000_SUCCESS;
}
diff --git a/sys/dev/pci/if_em_hw.h b/sys/dev/pci/if_em_hw.h
index 49337e765a5..50ded77426b 100644
--- a/sys/dev/pci/if_em_hw.h
+++ b/sys/dev/pci/if_em_hw.h
@@ -31,8 +31,8 @@
*******************************************************************************/
-/*$FreeBSD: if_em_hw.h,v 1.10 2003/06/05 17:51:38 pdeuskar Exp $*/
-/* $OpenBSD: if_em_hw.h,v 1.3 2003/06/13 19:21:21 henric Exp $ */
+/*$FreeBSD: if_em_hw.h,v 1.12 2003/11/14 18:02:25 pdeuskar Exp $*/
+/* $OpenBSD: if_em_hw.h,v 1.4 2003/12/09 23:37:04 henning Exp $ */
/* if_em_hw.h
* Structures, enums, and macros for the MAC
*/
@@ -42,6 +42,7 @@
#include <dev/pci/if_em_osdep.h>
+
/* Forward declarations of structures used by the shared code */
struct em_hw;
struct em_hw_stats;
@@ -56,9 +57,13 @@ typedef enum {
em_82544,
em_82540,
em_82545,
+ em_82545_rev_3,
em_82546,
+ em_82546_rev_3,
em_82541,
+ em_82541_rev_2,
em_82547,
+ em_82547_rev_2,
em_num_macs
} em_mac_type;
@@ -73,6 +78,7 @@ typedef enum {
typedef enum {
em_media_type_copper = 0,
em_media_type_fiber = 1,
+ em_media_type_internal_serdes = 2,
em_num_media_types
} em_media_type;
@@ -96,7 +102,8 @@ typedef enum {
typedef enum {
em_bus_type_unknown = 0,
em_bus_type_pci,
- em_bus_type_pcix
+ em_bus_type_pcix,
+ em_bus_type_reserved
} em_bus_type;
/* PCI bus speeds */
@@ -114,7 +121,8 @@ typedef enum {
typedef enum {
em_bus_width_unknown = 0,
em_bus_width_32,
- em_bus_width_64
+ em_bus_width_64,
+ em_bus_width_reserved
} em_bus_width;
/* PHY status info structure and supporting enums */
@@ -192,6 +200,26 @@ typedef enum {
em_phy_undefined = 0xFF
} em_phy_type;
+typedef enum {
+ em_ms_hw_default = 0,
+ em_ms_force_master,
+ em_ms_force_slave,
+ em_ms_auto
+} em_ms_type;
+
+typedef enum {
+ em_ffe_config_enabled = 0,
+ em_ffe_config_active,
+ em_ffe_config_blocked
+} em_ffe_config;
+
+typedef enum {
+ em_dsp_config_disabled = 0,
+ em_dsp_config_enabled,
+ em_dsp_config_activated,
+ em_dsp_config_undefined = 0xFF
+} em_dsp_config;
+
struct em_phy_info {
em_cable_length cable_length;
em_10bt_ext_dist_enable extended_10bt_distance;
@@ -230,9 +258,10 @@ struct em_eeprom_info {
/* Function prototypes */
/* Initialization */
-void em_reset_hw(struct em_hw *hw);
+int32_t em_reset_hw(struct em_hw *hw);
int32_t em_init_hw(struct em_hw *hw);
int32_t em_set_mac_type(struct em_hw *hw);
+void em_set_media_type(struct em_hw *hw);
/* Link Configuration */
int32_t em_setup_link(struct em_hw *hw);
@@ -240,8 +269,9 @@ int32_t em_phy_setup_autoneg(struct em_hw *hw);
void em_config_collision_dist(struct em_hw *hw);
int32_t em_config_fc_after_link_up(struct em_hw *hw);
int32_t em_check_for_link(struct em_hw *hw);
-void em_get_speed_and_duplex(struct em_hw *hw, uint16_t * speed, uint16_t * duplex);
+int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t * speed, uint16_t * duplex);
int32_t em_wait_autoneg(struct em_hw *hw);
+int32_t em_force_mac_fc(struct em_hw *hw);
/* PHY */
int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
@@ -298,6 +328,8 @@ uint32_t em_io_read(struct em_hw *hw, uint32_t port);
uint32_t em_read_reg_io(struct em_hw *hw, uint32_t offset);
void em_io_write(struct em_hw *hw, uint32_t port, uint32_t value);
void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
+int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up);
+int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
#define E1000_READ_REG_IO(a, reg) \
em_read_reg_io((a), E1000_##reg)
@@ -319,13 +351,22 @@ void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
#define E1000_DEV_ID_82540EP_LP 0x101E
#define E1000_DEV_ID_82545EM_COPPER 0x100F
#define E1000_DEV_ID_82545EM_FIBER 0x1011
+#define E1000_DEV_ID_82545GM_COPPER 0x1026
+#define E1000_DEV_ID_82545GM_FIBER 0x1027
+#define E1000_DEV_ID_82545GM_SERDES 0x1028
#define E1000_DEV_ID_82546EB_COPPER 0x1010
#define E1000_DEV_ID_82546EB_FIBER 0x1012
#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
#define E1000_DEV_ID_82541EI 0x1013
-#define E1000_DEV_ID_82541EP 0x1018
+#define E1000_DEV_ID_82541EI_MOBILE 0x1018
+#define E1000_DEV_ID_82541ER 0x1078
+#define E1000_DEV_ID_82547GI 0x1075
+#define E1000_DEV_ID_82541GI 0x1076
+#define E1000_DEV_ID_82541GI_MOBILE 0x1077
+#define E1000_DEV_ID_82546GB_COPPER 0x1079
+#define E1000_DEV_ID_82546GB_FIBER 0x107A
+#define E1000_DEV_ID_82546GB_SERDES 0x107B
#define E1000_DEV_ID_82547EI 0x1019
-#define NUM_DEV_IDS 20
#define NODE_ADDRESS_SIZE 6
#define ETH_LENGTH_OF_ADDRESS 6
@@ -391,7 +432,7 @@ void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
E1000_IMS_RXSEQ | \
E1000_IMS_LSC)
-/* The number of high/low register pairs in the RAR. The RAR (Receive Address
+/* Number of high/low register pairs in the RAR. The RAR (Receive Address
* Registers) holds the directed and multicast addresses that we monitor. We
* reserve one of these spots for our directed address, allowing us room for
* E1000_RAR_ENTRIES - 1 multicast addresses.
@@ -545,7 +586,7 @@ struct em_rar {
volatile uint32_t high; /* receive address high */
};
-/* The number of entries in the Multicast Table Array (MTA). */
+/* Number of entries in the Multicast Table Array (MTA). */
#define E1000_NUM_MTA_REGISTERS 128
/* IPv4 Address Table Entry */
@@ -605,6 +646,7 @@ struct em_ffvt_entry {
* A - register array
*/
#define E1000_CTRL 0x00000 /* Device Control - RW */
+#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
#define E1000_STATUS 0x00008 /* Device Status - RO */
#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
#define E1000_EERD 0x00014 /* EEPROM Read - RW */
@@ -940,6 +982,9 @@ struct em_hw {
em_bus_width bus_width;
em_bus_type bus_type;
struct em_eeprom_info eeprom;
+ em_ms_type master_slave;
+ em_ms_type original_master_slave;
+ em_ffe_config ffe_config_state;
uint32_t io_base;
uint32_t phy_id;
uint32_t phy_revision;
@@ -956,6 +1001,7 @@ struct em_hw {
uint32_t ledctl_default;
uint32_t ledctl_mode1;
uint32_t ledctl_mode2;
+ uint16_t phy_spd_default;
uint16_t autoneg_advertised;
uint16_t pci_cmd_word;
uint16_t fc_high_water;
@@ -980,10 +1026,13 @@ struct em_hw {
uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
boolean_t disable_polarity_correction;
boolean_t speed_downgraded;
+ em_dsp_config dsp_config_state;
boolean_t get_link_status;
boolean_t tbi_compatibility_en;
boolean_t tbi_compatibility_on;
+ boolean_t phy_reset_disable;
boolean_t fc_send_xon;
+ boolean_t fc_strict_ieee;
boolean_t report_tx_early;
boolean_t adaptive_ifs;
boolean_t ifs_params_forced;
@@ -1065,7 +1114,7 @@ struct em_hw {
#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
- * (0-small, 1-large) */
+ * (0-small, 1-large) */
#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
#ifndef E1000_EEPROM_GRANT_ATTEMPTS
#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
@@ -1127,22 +1176,22 @@ struct em_hw {
#define E1000_MDIC_ERROR 0x40000000
/* LED Control */
-#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
-#define E1000_LEDCTL_LED0_MODE_SHIFT 0
-#define E1000_LEDCTL_LED0_IVRT 0x00000040
-#define E1000_LEDCTL_LED0_BLINK 0x00000080
-#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
-#define E1000_LEDCTL_LED1_MODE_SHIFT 8
-#define E1000_LEDCTL_LED1_IVRT 0x00004000
-#define E1000_LEDCTL_LED1_BLINK 0x00008000
-#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
-#define E1000_LEDCTL_LED2_MODE_SHIFT 16
-#define E1000_LEDCTL_LED2_IVRT 0x00400000
-#define E1000_LEDCTL_LED2_BLINK 0x00800000
-#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
-#define E1000_LEDCTL_LED3_MODE_SHIFT 24
-#define E1000_LEDCTL_LED3_IVRT 0x40000000
-#define E1000_LEDCTL_LED3_BLINK 0x80000000
+#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
+#define E1000_LEDCTL_LED0_MODE_SHIFT 0
+#define E1000_LEDCTL_LED0_IVRT 0x00000040
+#define E1000_LEDCTL_LED0_BLINK 0x00000080
+#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
+#define E1000_LEDCTL_LED1_MODE_SHIFT 8
+#define E1000_LEDCTL_LED1_IVRT 0x00004000
+#define E1000_LEDCTL_LED1_BLINK 0x00008000
+#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
+#define E1000_LEDCTL_LED2_MODE_SHIFT 16
+#define E1000_LEDCTL_LED2_IVRT 0x00400000
+#define E1000_LEDCTL_LED2_BLINK 0x00800000
+#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
+#define E1000_LEDCTL_LED3_MODE_SHIFT 24
+#define E1000_LEDCTL_LED3_IVRT 0x40000000
+#define E1000_LEDCTL_LED3_BLINK 0x80000000
#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
@@ -1165,109 +1214,109 @@ struct em_hw {
#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
/* Interrupt Cause Read */
-#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
-#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
-#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
-#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
-#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
-#define E1000_ICR_RXO 0x00000040 /* rx overrun */
-#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
-#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
-#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
-#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
-#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
-#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
-#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
-#define E1000_ICR_TXD_LOW 0x00008000
-#define E1000_ICR_SRPD 0x00010000
+#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
+#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
+#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
+#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
+#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
+#define E1000_ICR_RXO 0x00000040 /* rx overrun */
+#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
+#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
+#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
+#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
+#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
+#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
+#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
+#define E1000_ICR_TXD_LOW 0x00008000
+#define E1000_ICR_SRPD 0x00010000
/* Interrupt Cause Set */
-#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
-#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
-#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
-#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
-#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
-#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
-#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
-#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
-#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
-#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
-#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
-#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
-#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
-#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_ICS_SRPD E1000_ICR_SRPD
+#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
+#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
+#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
+#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
+#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
+#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
+#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
+#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
+#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
+#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
+#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
+#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
+#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
+#define E1000_ICS_SRPD E1000_ICR_SRPD
/* Interrupt Mask Set */
-#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
-#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
-#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
-#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
-#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
-#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
-#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
-#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
-#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
-#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
-#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
-#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
-#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
-#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_IMS_SRPD E1000_ICR_SRPD
+#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
+#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
+#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
+#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
+#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
+#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
+#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
+#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
+#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
+#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
+#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
+#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
+#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
+#define E1000_IMS_SRPD E1000_ICR_SRPD
/* Interrupt Mask Clear */
-#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
-#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
-#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
-#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
-#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
-#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
-#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
-#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
-#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
-#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
-#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
-#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
-#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
-#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_IMC_SRPD E1000_ICR_SRPD
+#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
+#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
+#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
+#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
+#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
+#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
+#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
+#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
+#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
+#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
+#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
+#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
+#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
+#define E1000_IMC_SRPD E1000_ICR_SRPD
/* Receive Control */
-#define E1000_RCTL_RST 0x00000001 /* Software reset */
-#define E1000_RCTL_EN 0x00000002 /* enable */
-#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
-#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
-#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
-#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
-#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
-#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
-#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
-#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
-#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
-#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
-#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
-#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
-#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
-#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
-#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
-#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
+#define E1000_RCTL_RST 0x00000001 /* Software reset */
+#define E1000_RCTL_EN 0x00000002 /* enable */
+#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
+#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
+#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
+#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
+#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
+#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
+#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
+#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
+#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
+#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
+#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
+#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
+#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
+#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
+#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
+#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
-#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
-#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
-#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
-#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
+#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
+#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
+#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
+#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
-#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
-#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
-#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
-#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
-#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
-#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
-#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
-#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
-#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
+#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
+#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
+#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
+#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
+#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
+#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
+#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
+#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
+#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
/* Receive Descriptor */
#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
@@ -1432,15 +1481,17 @@ struct em_hw {
#define EEPROM_SIZE_128B 0x0000
#define EEPROM_SIZE_MASK 0x1C00
-
/* EEPROM Word Offsets */
-#define EEPROM_COMPAT 0x0003
-#define EEPROM_ID_LED_SETTINGS 0x0004
-#define EEPROM_INIT_CONTROL1_REG 0x000A
-#define EEPROM_INIT_CONTROL2_REG 0x000F
-#define EEPROM_CFG 0x0012
-#define EEPROM_FLASH_VERSION 0x0032
-#define EEPROM_CHECKSUM_REG 0x003F
+#define EEPROM_COMPAT 0x0003
+#define EEPROM_ID_LED_SETTINGS 0x0004
+#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
+#define EEPROM_INIT_CONTROL1_REG 0x000A
+#define EEPROM_INIT_CONTROL2_REG 0x000F
+#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
+#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
+#define EEPROM_CFG 0x0012
+#define EEPROM_FLASH_VERSION 0x0032
+#define EEPROM_CHECKSUM_REG 0x003F
/* Word definitions for ID LED Settings */
#define ID_LED_RESERVED_0000 0x0000
@@ -1464,6 +1515,9 @@ struct em_hw {
#define IGP_LED3_MODE 0x07000000
+/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
+#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
+
/* Mask bits for fields in Word 0x0a of the EEPROM */
#define EEPROM_WORD0A_ILOS 0x0010
#define EEPROM_WORD0A_SWDPIO 0x01E0
@@ -1485,6 +1539,8 @@ struct em_hw {
#define EEPROM_NODE_ADDRESS_BYTE_0 0
#define EEPROM_PBA_BYTE_1 8
+#define EEPROM_RESERVED_WORD 0xFFFF
+
/* EEPROM Map Sizes (Byte Counts) */
#define PBA_SIZE 4
@@ -1496,7 +1552,7 @@ struct em_hw {
#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
#define E1000_COLD_SHIFT 12
-/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
+/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
#define REQ_TX_DESCRIPTOR_MULTIPLE 8
#define REQ_RX_DESCRIPTOR_MULTIPLE 8
@@ -1563,35 +1619,30 @@ struct em_hw {
#define PCIX_STATUS_HI_MMRBC_2K 0x2
-/* The number of bits that we need to shift right to move the "pause"
- * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
- * in the TXCW register
+/* Number of bits required to shift right the "pause" bits from the
+ * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
*/
#define PAUSE_SHIFT 5
-/* The number of bits that we need to shift left to move the "SWDPIO"
- * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
- * in the CTRL register
+/* Number of bits required to shift left the "SWDPIO" bits from the
+ * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
*/
#define SWDPIO_SHIFT 17
-/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
- * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
- * Extended CTRL register.
- * in the CTRL register
+/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
+ * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
*/
#define SWDPIO__EXT_SHIFT 4
-/* The number of bits that we need to shift left to move the "ILOS"
- * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
- * in the CTRL register
+/* Number of bits required to shift left the "ILOS" bit from the EEPROM
+ * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
*/
#define ILOS_SHIFT 3
#define RECEIVE_BUFFER_ALIGN_SIZE (256)
-/* The number of milliseconds we wait for auto-negotiation to complete */
+/* Number of milliseconds we wait for auto-negotiation to complete */
#define LINK_UP_TIMEOUT 500
#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
@@ -1674,6 +1725,16 @@ struct em_hw {
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
+#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
+#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
+#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
+#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
+#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
+
+#define IGP01E1000_IEEE_REGS_PAGE 0x0000
+#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
+#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
+
/* IGP01E1000 Specific Registers */
#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
@@ -1689,16 +1750,35 @@ struct em_hw {
#define IGP01E1000_PHY_AGC_C 0x1472
#define IGP01E1000_PHY_AGC_D 0x1872
-/* Number of AGC registers */
-#define IGP01E1000_PHY_AGC_NUM 4
+/* IGP01E1000 DSP Reset Register */
+#define IGP01E1000_PHY_DSP_RESET 0x1F33
+#define IGP01E1000_PHY_DSP_SET 0x1F71
+#define IGP01E1000_PHY_DSP_FFE 0x1F35
+
+#define IGP01E1000_PHY_CHANNEL_NUM 4
+#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
+#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
+#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
+#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
+
+#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
+#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
+#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
+#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
+#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
+#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
+
+#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
/* IGP01E1000 PCS Initialization register - stores the polarity status when
* speed = 1000 Mbps. */
#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
+#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
+#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
-
+#define MAX_PHY_MULTI_PAGE_REG 0xF /*Registers that are equal on all pages*/
/* PHY Control Register */
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
@@ -1812,8 +1892,11 @@ struct em_hw {
#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
-#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
-#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
+#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
+#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
+#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
+#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
+#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
/* Extended Status Register */
#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
@@ -1905,7 +1988,6 @@ struct em_hw {
#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
-
/* IGP01E1000 Specific Port Config Register - R/W */
#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
#define IGP01E1000_PSCFR_PRE_EN 0x0020
@@ -1956,6 +2038,11 @@ struct em_hw {
#define IGP01E1000_MSE_CHANNEL_B 0x0F00
#define IGP01E1000_MSE_CHANNEL_A 0xF000
+/* IGP01E1000 DSP reset macros */
+#define DSP_RESET_ENABLE 0x0
+#define DSP_RESET_DISABLE 0x2
+#define E1000_MAX_DSP_RESETS 10
+
/* IGP01E1000 AGC Registers */
#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
@@ -1966,18 +2053,6 @@ struct em_hw {
/* The precision of the length is +/- 10 meters */
#define IGP01E1000_AGC_RANGE 10
-/* IGP cable length table */
-static const
-uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
- { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
- 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
- 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
- 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
- 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
- 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
- 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
- 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
-
/* IGP01E1000 PCS Initialization register */
/* bits 3:6 in the PCS registers stores the channels polarity */
#define IGP01E1000_PHY_POLARITY_MASK 0x0078
@@ -1987,6 +2062,23 @@ uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
* on Link-Up */
#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
+/* IGP01E1000 Analog Register */
+#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
+#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
+#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
+#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
+
+#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
+#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
+#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
+#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
+#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
+
+#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
+#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
+#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
+#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
+
/* Bit definitions for valid PHY IDs. */
#define M88E1000_E_PHY_ID 0x01410C50
#define M88E1000_I_PHY_ID 0x01410C30
@@ -2020,5 +2112,7 @@ uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
#define ADVERTISE_1000_HALF 0x0010
#define ADVERTISE_1000_FULL 0x0020
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
+#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
+#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
#endif /* _EM_HW_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 19:45:08 +0000