remove typedef's.

3 files changed, 495 insertions, 503 deletions

diff --git a/sys/dev/microcode/bnx/bnxfw.h b/sys/dev/microcode/bnx/bnxfw.h
index e0f9e462045..233fb548ce8 100644
--- a/sys/dev/microcode/bnx/bnxfw.h
+++ b/sys/dev/microcode/bnx/bnxfw.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bnxfw.h,v 1.1 2006/06/26 05:37:05 brad Exp $	*/
+/*	$OpenBSD: bnxfw.h,v 1.2 2006/08/10 04:01:52 brad Exp $	*/
 
 /*-
  * Copyright (c) 2006 Broadcom Corporation
@@ -43,18 +43,18 @@
 static int bnx_COM_b06FwReleaseMajor = 0x1;
 static int bnx_COM_b06FwReleaseMinor = 0x0;
 static int bnx_COM_b06FwReleaseFix = 0x0;
-static u32 bnx_COM_b06FwStartAddr = 0x080008b4;
-static u32 bnx_COM_b06FwTextAddr = 0x08000000;
+static u_int32_t bnx_COM_b06FwStartAddr = 0x080008b4;
+static u_int32_t bnx_COM_b06FwTextAddr = 0x08000000;
 static int bnx_COM_b06FwTextLen = 0x57bc;
-static u32 bnx_COM_b06FwDataAddr = 0x08005840;
+static u_int32_t bnx_COM_b06FwDataAddr = 0x08005840;
 static int bnx_COM_b06FwDataLen = 0x0;
-static u32 bnx_COM_b06FwRodataAddr = 0x080057c0;
+static u_int32_t bnx_COM_b06FwRodataAddr = 0x080057c0;
 static int bnx_COM_b06FwRodataLen = 0x58;
-static u32 bnx_COM_b06FwBssAddr = 0x08005860;
+static u_int32_t bnx_COM_b06FwBssAddr = 0x08005860;
 static int bnx_COM_b06FwBssLen = 0x88;
-static u32 bnx_COM_b06FwSbssAddr = 0x08005840;
+static u_int32_t bnx_COM_b06FwSbssAddr = 0x08005840;
 static int bnx_COM_b06FwSbssLen = 0x1c;
-static u32 bnx_COM_b06FwText[(0x57bc/4) + 1] = {
+static u_int32_t bnx_COM_b06FwText[(0x57bc/4) + 1] = {
 	0x0a00022d, 0x00000000, 0x00000000, 0x0000000d, 0x636f6d20, 0x322e352e,
 	0x38000000, 0x02050802, 0x00000000, 0x00000003, 0x00000014, 0x00000032,
 	0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -992,30 +992,30 @@ static u32 bnx_COM_b06FwText[(0x57bc/4) + 1] = {
 	0xaf45003c, 0xaf420030, 0x00000000, 0x00000000, 0x8f420000, 0x30420020,
 	0x1040fffd, 0x3c020020, 0xaf420030, 0x03e00008, 0x00000000, 0x00000000};
 
-static u32 bnx_COM_b06FwData[(0x0/4) + 1] = { 0x0 };
-static u32 bnx_COM_b06FwRodata[(0x58/4) + 1] = {
+static u_int32_t bnx_COM_b06FwData[(0x0/4) + 1] = { 0x0 };
+static u_int32_t bnx_COM_b06FwRodata[(0x58/4) + 1] = {
 	0x08002428, 0x0800245c, 0x0800245c, 0x0800245c, 0x0800245c, 0x0800245c,
 	0x08002380, 0x0800245c, 0x080023e4, 0x0800245c, 0x0800231c, 0x0800245c,
 	0x0800245c, 0x0800245c, 0x08002328, 0x00000000, 0x08003240, 0x08003270,
 	0x080032a0, 0x080032d0, 0x08003300, 0x00000000, 0x00000000 };
-static u32 bnx_COM_b06FwBss[(0x88/4) + 1] = { 0x0 };
-static u32 bnx_COM_b06FwSbss[(0x1c/4) + 1] = { 0x0 };
+static u_int32_t bnx_COM_b06FwBss[(0x88/4) + 1] = { 0x0 };
+static u_int32_t bnx_COM_b06FwSbss[(0x1c/4) + 1] = { 0x0 };
 
 static int bnx_RXP_b06FwReleaseMajor = 0x1;
 static int bnx_RXP_b06FwReleaseMinor = 0x0;
 static int bnx_RXP_b06FwReleaseFix = 0x0;
-static u32 bnx_RXP_b06FwStartAddr = 0x08003184;
-static u32 bnx_RXP_b06FwTextAddr = 0x08000000;
+static u_int32_t bnx_RXP_b06FwStartAddr = 0x08003184;
+static u_int32_t bnx_RXP_b06FwTextAddr = 0x08000000;
 static int bnx_RXP_b06FwTextLen = 0x588c;
-static u32 bnx_RXP_b06FwDataAddr = 0x080058e0;
+static u_int32_t bnx_RXP_b06FwDataAddr = 0x080058e0;
 static int bnx_RXP_b06FwDataLen = 0x0;
-static u32 bnx_RXP_b06FwRodataAddr = 0x08005890;
+static u_int32_t bnx_RXP_b06FwRodataAddr = 0x08005890;
 static int bnx_RXP_b06FwRodataLen = 0x28;
-static u32 bnx_RXP_b06FwBssAddr = 0x08005900;
+static u_int32_t bnx_RXP_b06FwBssAddr = 0x08005900;
 static int bnx_RXP_b06FwBssLen = 0x13a4;
-static u32 bnx_RXP_b06FwSbssAddr = 0x080058e0;
+static u_int32_t bnx_RXP_b06FwSbssAddr = 0x080058e0;
 static int bnx_RXP_b06FwSbssLen = 0x1c;
-static u32 bnx_RXP_b06FwText[(0x588c/4) + 1] = {
+static u_int32_t bnx_RXP_b06FwText[(0x588c/4) + 1] = {
 	0x0a000c61, 0x00000000, 0x00000000, 0x0000000d, 0x72787020, 0x322e362e,
 	0x31000000, 0x02060103, 0x00000000, 0x0000000d, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -1962,14 +1962,14 @@ static u32 bnx_RXP_b06FwText[(0x588c/4) + 1] = {
 	0xac860000, 0x00000000, 0x00000000, 0x24840004, 0x00a01021, 0x1440fffa,
 	0x24a5ffff, 0x03e00008, 0x00000000, 0x00000000 }; 
 
-static u32 bnx_RXP_b06FwData[(0x0/4) + 1] = { 0x0 };
-static u32 bnx_RXP_b06FwRodata[(0x28/4) + 1] = {
+static u_int32_t bnx_RXP_b06FwData[(0x0/4) + 1] = { 0x0 };
+static u_int32_t bnx_RXP_b06FwRodata[(0x28/4) + 1] = {
 	0x0800468c, 0x0800458c, 0x08004630, 0x08004648, 0x08004660, 0x08004680,
 	0x0800468c, 0x0800468c, 0x08004594, 0x00000000, 0x00000000 };
-static u32 bnx_RXP_b06FwBss[(0x13a4/4) + 1] = { 0x0 };
-static u32 bnx_RXP_b06FwSbss[(0x1c/4) + 1] = { 0x0 };
+static u_int32_t bnx_RXP_b06FwBss[(0x13a4/4) + 1] = { 0x0 };
+static u_int32_t bnx_RXP_b06FwSbss[(0x1c/4) + 1] = { 0x0 };
 
-static u32 bnx_rv2p_proc1[] = {
+static u_int32_t bnx_rv2p_proc1[] = {
     0x00000008, 0xac000001, 0x0000000c, 0x2f800001, 0x00000010, 0x203f0146, 
     0x00000010, 0x213f0003, 0x00000010, 0x20bf002b, 0x00000018, 0x8000fffd, 
     0x00000010, 0xb1b8b017, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000, 
@@ -2097,7 +2097,7 @@ static u32 bnx_rv2p_proc1[] = {
     0x00000000, 0x83871800, 0x00000018, 0x00020000
 };
 
-static u32 bnx_rv2p_proc2[] = {
+static u_int32_t bnx_rv2p_proc2[] = {
     0x00000000, 0x2a000000, 
     0x00000010, 0xb1d40000, 0x00000008, 0x02540003, 0x00000018, 0x00040000, 
     0x00000018, 0x8000000b, 0x00000018, 0x8000000b, 0x00000018, 0x8000000f, 
@@ -2344,18 +2344,18 @@ static u32 bnx_rv2p_proc2[] = {
 static int bnx_TPAT_b06FwReleaseMajor = 0x1;
 static int bnx_TPAT_b06FwReleaseMinor = 0x0;
 static int bnx_TPAT_b06FwReleaseFix = 0x0;
-static u32 bnx_TPAT_b06FwStartAddr = 0x08000860;
-static u32 bnx_TPAT_b06FwTextAddr = 0x08000800;
+static u_int32_t bnx_TPAT_b06FwStartAddr = 0x08000860;
+static u_int32_t bnx_TPAT_b06FwTextAddr = 0x08000800;
 static int bnx_TPAT_b06FwTextLen = 0x122c;
-static u32 bnx_TPAT_b06FwDataAddr = 0x08001a60;
+static u_int32_t bnx_TPAT_b06FwDataAddr = 0x08001a60;
 static int bnx_TPAT_b06FwDataLen = 0x0;
-static u32 bnx_TPAT_b06FwRodataAddr = 0x00000000;
+static u_int32_t bnx_TPAT_b06FwRodataAddr = 0x00000000;
 static int bnx_TPAT_b06FwRodataLen = 0x0;
-static u32 bnx_TPAT_b06FwBssAddr = 0x08001aa0;
+static u_int32_t bnx_TPAT_b06FwBssAddr = 0x08001aa0;
 static int bnx_TPAT_b06FwBssLen = 0x250;
-static u32 bnx_TPAT_b06FwSbssAddr = 0x08001a60;
+static u_int32_t bnx_TPAT_b06FwSbssAddr = 0x08001a60;
 static int bnx_TPAT_b06FwSbssLen = 0x34;
-static u32 bnx_TPAT_b06FwText[(0x122c/4) + 1] = {
+static u_int32_t bnx_TPAT_b06FwText[(0x122c/4) + 1] = {
 	0x0a000218, 0x00000000, 0x00000000, 0x0000000d, 0x74706174, 0x20322e36,
 	0x2e320000, 0x02060201, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -2551,26 +2551,26 @@ static u32 bnx_TPAT_b06FwText[(0x122c/4) + 1] = {
 	0x00000000, 0x00000000, 0x24840004, 0x00a01021, 0x1440fffa, 0x24a5ffff,
 	0x03e00008, 0x00000000, 0x0000000d, 0x03e00008, 0x00000000, 0x00000000};
 
-static u32 bnx_TPAT_b06FwData[(0x0/4) + 1] = { 0x0 };
-static u32 bnx_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 };
-static u32 bnx_TPAT_b06FwBss[(0x250/4) + 1] = { 0x0 };
-static u32 bnx_TPAT_b06FwSbss[(0x34/4) + 1] = { 0x0 };
+static u_int32_t bnx_TPAT_b06FwData[(0x0/4) + 1] = { 0x0 };
+static u_int32_t bnx_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 };
+static u_int32_t bnx_TPAT_b06FwBss[(0x250/4) + 1] = { 0x0 };
+static u_int32_t bnx_TPAT_b06FwSbss[(0x34/4) + 1] = { 0x0 };
 
 static int bnx_TXP_b06FwReleaseMajor = 0x1;
 static int bnx_TXP_b06FwReleaseMinor = 0x0;
 static int bnx_TXP_b06FwReleaseFix = 0x0;
-static u32 bnx_TXP_b06FwStartAddr = 0x080034b0;
-static u32 bnx_TXP_b06FwTextAddr = 0x08000000;
+static u_int32_t bnx_TXP_b06FwStartAddr = 0x080034b0;
+static u_int32_t bnx_TXP_b06FwTextAddr = 0x08000000;
 static int bnx_TXP_b06FwTextLen = 0x5748;
-static u32 bnx_TXP_b06FwDataAddr = 0x08005760;
+static u_int32_t bnx_TXP_b06FwDataAddr = 0x08005760;
 static int bnx_TXP_b06FwDataLen = 0x0;
-static u32 bnx_TXP_b06FwRodataAddr = 0x00000000;
+static u_int32_t bnx_TXP_b06FwRodataAddr = 0x00000000;
 static int bnx_TXP_b06FwRodataLen = 0x0;
-static u32 bnx_TXP_b06FwBssAddr = 0x080057a0;
+static u_int32_t bnx_TXP_b06FwBssAddr = 0x080057a0;
 static int bnx_TXP_b06FwBssLen = 0x1c4;
-static u32 bnx_TXP_b06FwSbssAddr = 0x08005760;
+static u_int32_t bnx_TXP_b06FwSbssAddr = 0x08005760;
 static int bnx_TXP_b06FwSbssLen = 0x38;
-static u32 bnx_TXP_b06FwText[(0x5748/4) + 1] = {
+static u_int32_t bnx_TXP_b06FwText[(0x5748/4) + 1] = {
 	0x0a000d2c, 0x00000000, 0x00000000, 0x0000000d, 0x74787020, 0x322e352e,
 	0x38000000, 0x02050800, 0x0000000a, 0x000003e8, 0x0000ea60, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -3504,7 +3504,7 @@ static u32 bnx_TXP_b06FwText[(0x5748/4) + 1] = {
 	0x00671821, 0xad250070, 0x24420001, 0xacc20074, 0x03e00008, 0xac68000c,
 	0x00000000 };
 
-static u32 bnx_TXP_b06FwData[(0x0/4) + 1] = { 0x0 };
-static u32 bnx_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 };
-static u32 bnx_TXP_b06FwBss[(0x1c4/4) + 1] = { 0x0 };
-static u32 bnx_TXP_b06FwSbss[(0x38/4) + 1] = { 0x0 };
+static u_int32_t bnx_TXP_b06FwData[(0x0/4) + 1] = { 0x0 };
+static u_int32_t bnx_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 };
+static u_int32_t bnx_TXP_b06FwBss[(0x1c4/4) + 1] = { 0x0 };
+static u_int32_t bnx_TXP_b06FwSbss[(0x38/4) + 1] = { 0x0 };
diff --git a/sys/dev/pci/if_bnx.c b/sys/dev/pci/if_bnx.c
index 89368eb2aa4..d21a4ba9605 100644
--- a/sys/dev/pci/if_bnx.c
+++ b/sys/dev/pci/if_bnx.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_bnx.c,v 1.4 2006/08/09 15:49:49 marco Exp $	*/
+/*	$OpenBSD: if_bnx.c,v 1.5 2006/08/10 04:01:52 brad Exp $	*/
 
 /*-
  * Copyright (c) 2006 Broadcom Corporation
@@ -63,7 +63,7 @@ char bnx_driver_version[] = "v0.9.6";
 /* BNX Debug Options                                                        */
 /****************************************************************************/
 #ifdef BNX_DEBUG
-	u32 bnx_debug = BNX_WARN;
+	u_int32_t bnx_debug = BNX_WARN;
 
 	/*          0 = Never              */
 	/*          1 = 1 in 2,147,483,648 */
@@ -225,9 +225,9 @@ void bnx_breakpoint		(struct bnx_softc *);
 /****************************************************************************/
 /* BNX Register/Memory Access Routines                                      */
 /****************************************************************************/
-u32 bnx_reg_rd_ind		(struct bnx_softc *, u32);
-void bnx_reg_wr_ind		(struct bnx_softc *, u32, u32);
-void bnx_ctx_wr			(struct bnx_softc *, u32, u32, u32);
+u_int32_t bnx_reg_rd_ind		(struct bnx_softc *, u_int32_t);
+void bnx_reg_wr_ind		(struct bnx_softc *, u_int32_t, u_int32_t);
+void bnx_ctx_wr			(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t);
 int bnx_miibus_read_reg		(struct device *, int, int);
 void bnx_miibus_write_reg	(struct device *, int, int, int);
 void bnx_miibus_statchg		(struct device *);
@@ -239,16 +239,16 @@ int bnx_acquire_nvram_lock	(struct bnx_softc *);
 int bnx_release_nvram_lock	(struct bnx_softc *);
 void bnx_enable_nvram_access	(struct bnx_softc *);
 void bnx_disable_nvram_access	(struct bnx_softc *);
-int bnx_nvram_read_dword	(struct bnx_softc *, u32, u8 *, u32);
+int bnx_nvram_read_dword	(struct bnx_softc *, u_int32_t, u_int8_t *, u_int32_t);
 int bnx_init_nvram		(struct bnx_softc *);
-int bnx_nvram_read		(struct bnx_softc *, u32, u8 *, int);
+int bnx_nvram_read		(struct bnx_softc *, u_int32_t, u_int8_t *, int);
 int bnx_nvram_test		(struct bnx_softc *);
 #ifdef BNX_NVRAM_WRITE_SUPPORT
 int bnx_enable_nvram_write	(struct bnx_softc *);
 void bnx_disable_nvram_write	(struct bnx_softc *);
-int bnx_nvram_erase_page	(struct bnx_softc *, u32);
-int bnx_nvram_write_dword	(struct bnx_softc *, u32, u8 *, u32);
-int bnx_nvram_write		(struct bnx_softc *, u32, u8 *, int);
+int bnx_nvram_erase_page	(struct bnx_softc *, u_int32_t);
+int bnx_nvram_write_dword	(struct bnx_softc *, u_int32_t, u_int8_t *, u_int32_t);
+int bnx_nvram_write		(struct bnx_softc *, u_int32_t, u_int8_t *, int);
 #endif
 
 /****************************************************************************/
@@ -262,23 +262,23 @@ void bnx_dma_map_tx_desc	(void *, bus_dmamap_t);
 /****************************************************************************/
 /* BNX Firmware Synchronization and Load                                    */
 /****************************************************************************/
-int bnx_fw_sync			(struct bnx_softc *, u32);
-void bnx_load_rv2p_fw		(struct bnx_softc *, u32 *, u32, u32);
+int bnx_fw_sync			(struct bnx_softc *, u_int32_t);
+void bnx_load_rv2p_fw		(struct bnx_softc *, u_int32_t *, u_int32_t, u_int32_t);
 void bnx_load_cpu_fw		(struct bnx_softc *, struct cpu_reg *, struct fw_info *);
 void bnx_init_cpus		(struct bnx_softc *);
 
 void bnx_stop			(struct bnx_softc *);
-int bnx_reset			(struct bnx_softc *, u32);
+int bnx_reset			(struct bnx_softc *, u_int32_t);
 int bnx_chipinit 		(struct bnx_softc *);
 int bnx_blockinit 		(struct bnx_softc *);
-int bnx_get_buf			(struct bnx_softc *, struct mbuf *, u16 *, u16 *, u32 *);
+int bnx_get_buf			(struct bnx_softc *, struct mbuf *, u_int16_t *, u_int16_t *, u_int32_t *);
 
 int bnx_init_tx_chain		(struct bnx_softc *);
 int bnx_init_rx_chain		(struct bnx_softc *);
 void bnx_free_rx_chain		(struct bnx_softc *);
 void bnx_free_tx_chain		(struct bnx_softc *);
 
-int bnx_tx_encap		(struct bnx_softc *, struct mbuf *, u16 *, u16 *, u32 *);
+int bnx_tx_encap		(struct bnx_softc *, struct mbuf *, u_int16_t *, u_int16_t *, u_int32_t *);
 void bnx_start			(struct ifnet *);
 int bnx_ioctl			(struct ifnet *, u_long, caddr_t);
 void bnx_watchdog		(struct ifnet *);
@@ -346,7 +346,7 @@ bnx_attach(struct device *parent, struct device *self, void *aux)
 	pci_intr_handle_t ih;
 	const char *intrstr = NULL;
 	struct ifnet *ifp;
-	u32 val;
+	u_int32_t val;
 	pcireg_t memtype;
 	bus_size_t size;
 
@@ -437,7 +437,7 @@ bnx_attach(struct device *parent, struct device *self, void *aux)
 	/* Get PCI bus information (speed and type). */
 	val = REG_RD(sc, BNX_PCICFG_MISC_STATUS);
 	if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) {
-		u32 clkreg;
+		u_int32_t clkreg;
 
 		sc->bnx_flags |= BNX_PCIX_FLAG;
 
@@ -713,15 +713,15 @@ bnx_shutdown(void *xsc)
 /* Returns:                                                                 */
 /*   The value of the register.                                             */
 /****************************************************************************/
-u32
-bnx_reg_rd_ind(struct bnx_softc *sc, u32 offset)
+u_int32_t
+bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset)
 {
 	struct pci_attach_args *pa = &(sc->bnx_pa);
 
 	pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, offset);
 #ifdef BNX_DEBUG
 	{
-		u32 val;
+		u_int32_t val;
 		val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW);
 		DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
 			__FUNCTION__, offset, val);
@@ -743,7 +743,7 @@ bnx_reg_rd_ind(struct bnx_softc *sc, u32 offset)
 /*   Nothing.                                                               */
 /****************************************************************************/
 void
-bnx_reg_wr_ind(struct bnx_softc *sc, u32 offset, u32 val)
+bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val)
 {
 	struct pci_attach_args  *pa = &(sc->bnx_pa);
 
@@ -764,7 +764,7 @@ bnx_reg_wr_ind(struct bnx_softc *sc, u32 offset, u32 val)
 /*   Nothing.                                                               */
 /****************************************************************************/
 void
-bnx_ctx_wr(struct bnx_softc *sc, u32 cid_addr, u32 offset, u32 val)
+bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t offset, u_int32_t val)
 {
 
 	DBPRINT(sc, BNX_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
@@ -787,7 +787,7 @@ int
 bnx_miibus_read_reg(struct device *dev, int phy, int reg)
 {
 	struct bnx_softc *sc = (struct bnx_softc *)dev;
-	u32 val;
+	u_int32_t val;
 	int i;
 
 	/* Make sure we are accessing the correct PHY address. */
@@ -834,7 +834,7 @@ bnx_miibus_read_reg(struct device *dev, int phy, int reg)
 	}
 
 	DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
-		__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff);
+		__FUNCTION__, phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
 
 	if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) {
 		val = REG_RD(sc, BNX_EMAC_MDIO_MODE);
@@ -862,7 +862,7 @@ void
 bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val)
 {
 	struct bnx_softc *sc = (struct bnx_softc *)dev;
-	u32 val1;
+	u_int32_t val1;
 	int i;
 
 	/* Make sure we are accessing the correct PHY address. */
@@ -872,7 +872,7 @@ bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val)
 	}
 
 	DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
-		__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff);
+		__FUNCTION__, phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
 
 	if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) {
 		val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
@@ -964,7 +964,7 @@ bnx_miibus_statchg(struct device *dev)
 int
 bnx_acquire_nvram_lock(struct bnx_softc *sc)
 {
-	u32 val;
+	u_int32_t val;
 	int j;
 
 	DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n");
@@ -1001,7 +1001,7 @@ int
 bnx_release_nvram_lock(struct bnx_softc *sc)
 {
 	int j;
-	u32 val;
+	u_int32_t val;
 
 	DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n");
 
@@ -1038,7 +1038,7 @@ bnx_release_nvram_lock(struct bnx_softc *sc)
 int
 bnx_enable_nvram_write(struct bnx_softc *sc)
 {
-	u32 val;
+	u_int32_t val;
 
 	DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n");
 
@@ -1079,7 +1079,7 @@ bnx_enable_nvram_write(struct bnx_softc *sc)
 void
 bnx_disable_nvram_write(struct bnx_softc *sc)
 {
-	u32 val;
+	u_int32_t val;
 
 	DBPRINT(sc, BNX_VERBOSE,  "Disabling NVRAM write.\n");
 
@@ -1100,7 +1100,7 @@ bnx_disable_nvram_write(struct bnx_softc *sc)
 void
 bnx_enable_nvram_access(struct bnx_softc *sc)
 {
-	u32 val;
+	u_int32_t val;
 
 	DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n");
 
@@ -1121,7 +1121,7 @@ bnx_enable_nvram_access(struct bnx_softc *sc)
 void
 bnx_disable_nvram_access(struct bnx_softc *sc)
 {
-	u32 val;
+	u_int32_t val;
 
 	DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n");
 
@@ -1144,9 +1144,9 @@ bnx_disable_nvram_access(struct bnx_softc *sc)
 /*   0 on success, positive value on failure.                               */
 /****************************************************************************/
 int
-bnx_nvram_erase_page(struct bnx_softc *sc, u32 offset)
+bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset)
 {
-	u32 cmd;
+	u_int32_t cmd;
 	int j;
 
 	/* Buffered flash doesn't require an erase. */
@@ -1169,7 +1169,7 @@ bnx_nvram_erase_page(struct bnx_softc *sc, u32 offset)
 
 	/* Wait for completion. */
 	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
-		u32 val;
+		u_int32_t val;
 
 		DELAY(5);
 
@@ -1197,10 +1197,10 @@ bnx_nvram_erase_page(struct bnx_softc *sc, u32 offset)
 /*   0 on success and the 32 bit value read, positive value on failure.     */
 /****************************************************************************/
 int
-bnx_nvram_read_dword(struct bnx_softc *sc, u32 offset, u8 *ret_val,
-							u32 cmd_flags)
+bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_val,
+							u_int32_t cmd_flags)
 {
-	u32 cmd;
+	u_int32_t cmd;
 	int i, rc = 0;
 
 	/* Build the command word. */
@@ -1223,7 +1223,7 @@ bnx_nvram_read_dword(struct bnx_softc *sc, u32 offset, u8 *ret_val,
 
 	/* Wait for completion. */
 	for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
-		u32 val;
+		u_int32_t val;
 
 		DELAY(5);
 
@@ -1259,10 +1259,10 @@ bnx_nvram_read_dword(struct bnx_softc *sc, u32 offset, u8 *ret_val,
 /*   0 on success, positive value on failure.                               */
 /****************************************************************************/
 int
-bnx_nvram_write_dword(struct bnx_softc *sc, u32 offset, u8 *val,
-	u32 cmd_flags)
+bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val,
+	u_int32_t cmd_flags)
 {
-	u32 cmd, val32;
+	u_int32_t cmd, val32;
 	int j;
 
 	/* Build the command word. */
@@ -1315,7 +1315,7 @@ bnx_nvram_write_dword(struct bnx_softc *sc, u32 offset, u8 *val,
 int
 bnx_init_nvram(struct bnx_softc *sc)
 {
-	u32 val;
+	u_int32_t val;
 	int j, entry_count, rc;
 	struct flash_spec *flash;
 
@@ -1351,7 +1351,7 @@ bnx_init_nvram(struct bnx_softc *sc)
 		}
 	} else {
 		/* Flash interface not yet reconfigured. */
-		u32 mask;
+		u_int32_t mask;
 
 		DBPRINT(sc,BNX_INFO_LOAD, 
 			"bnx_init_nvram(): Flash was NOT reconfigured.\n");
@@ -1421,11 +1421,11 @@ bnx_init_nvram(struct bnx_softc *sc)
 /*   0 on success and the data read, positive value on failure.             */
 /****************************************************************************/
 int
-bnx_nvram_read(struct bnx_softc *sc, u32 offset, u8 *ret_buf,
+bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf,
 	int buf_size)
 {
 	int rc = 0;
-	u32 cmd_flags, offset32, len32, extra;
+	u_int32_t cmd_flags, offset32, len32, extra;
 
 	if (buf_size == 0)
 		return 0;
@@ -1444,8 +1444,8 @@ bnx_nvram_read(struct bnx_softc *sc, u32 offset, u8 *ret_buf,
 	cmd_flags = 0;
 
 	if (offset32 & 3) {
-		u8 buf[4];
-		u32 pre_len;
+		u_int8_t buf[4];
+		u_int32_t pre_len;
 
 		offset32 &= ~3;
 		pre_len = 4 - (offset & 3);
@@ -1476,7 +1476,7 @@ bnx_nvram_read(struct bnx_softc *sc, u32 offset, u8 *ret_buf,
 	}
 
 	if (len32 == 4) {
-		u8 buf[4];
+		u_int8_t buf[4];
 
 		if (cmd_flags)
 			cmd_flags = BNX_NVM_COMMAND_LAST;
@@ -1489,7 +1489,7 @@ bnx_nvram_read(struct bnx_softc *sc, u32 offset, u8 *ret_buf,
 		memcpy(ret_buf, buf, 4 - extra);
 	}
 	else if (len32 > 0) {
-		u8 buf[4];
+		u_int8_t buf[4];
 
 		/* Read the first word. */
 		if (cmd_flags)
@@ -1541,11 +1541,11 @@ bnx_nvram_read(struct bnx_softc *sc, u32 offset, u8 *ret_buf,
 /*   0 on success, positive value on failure.                               */
 /****************************************************************************/
 int
-bnx_nvram_write(struct bnx_softc *sc, u32 offset, u8 *data_buf,
+bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf,
 	int buf_size)
 {
-	u32 written, offset32, len32;
-	u8 *buf, start[4], end[4];
+	u_int32_t written, offset32, len32;
+	u_int8_t *buf, start[4], end[4];
 	int rc = 0;
 	int align_start, align_end;
 
@@ -1587,10 +1587,10 @@ bnx_nvram_write(struct bnx_softc *sc, u32 offset, u8 *data_buf,
 
 	written = 0;
 	while ((written < len32) && (rc == 0)) {
-		u32 page_start, page_end, data_start, data_end;
-		u32 addr, cmd_flags;
+		u_int32_t page_start, page_end, data_start, data_end;
+		u_int32_t addr, cmd_flags;
 		int i;
-		u8 flash_buffer[264];
+		u_int8_t flash_buffer[264];
 
 	    /* Find the page_start addr */
 		page_start = offset32 + written;
@@ -1728,10 +1728,10 @@ nvram_write_end:
 int
 bnx_nvram_test(struct bnx_softc *sc)
 {
-	u32 buf[BNX_NVRAM_SIZE / 4];
-	u8 *data = (u8 *) buf;
+	u_int32_t buf[BNX_NVRAM_SIZE / 4];
+	u_int8_t *data = (u_int8_t *) buf;
 	int rc = 0;
-	u32 magic, csum;
+	u_int32_t magic, csum;
 
 	/*
 	 * Check that the device NVRAM is valid by reading
@@ -1883,10 +1883,10 @@ bnx_dma_map_tx_desc(void *arg, bus_dmamap_t map)
 	struct bnx_softc *sc;
 	struct tx_bd *txbd = NULL;
 	int i = 0, nseg;
-	u16 prod, chain_prod;
-	u32	prod_bseq;
+	u_int16_t prod, chain_prod;
+	u_int32_t	prod_bseq;
 #ifdef BNX_DEBUG
-	u16 debug_prod;
+	u_int16_t debug_prod;
 #endif
 
 	map_arg = arg;
@@ -2021,7 +2021,7 @@ bnx_dma_alloc(struct bnx_softc *sc)
 
 	/* DRC - Fix for 64 bit addresses. */
 	DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n",
-		(u32) sc->status_block_paddr);
+		(u_int32_t) sc->status_block_paddr);
 
 	/*
 	 * Allocate DMA memory for the statistics block, map the memory into
@@ -2061,7 +2061,7 @@ bnx_dma_alloc(struct bnx_softc *sc)
 
 	/* DRC - Fix for 64 bit address. */
 	DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 
-		(u32) sc->stats_block_paddr);
+		(u_int32_t) sc->stats_block_paddr);
 
 	/*
 	 * Allocate DMA memory for the TX buffer descriptor chain,
@@ -2104,7 +2104,7 @@ bnx_dma_alloc(struct bnx_softc *sc)
 
 		/* DRC - Fix for 64 bit systems. */
 		DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 
-			i, (u32) sc->tx_bd_chain_paddr[i]);
+			i, (u_int32_t) sc->tx_bd_chain_paddr[i]);
 	}
 
 	/*
@@ -2162,7 +2162,7 @@ bnx_dma_alloc(struct bnx_softc *sc)
 
 		/* DRC - Fix for 64 bit systems. */
 		DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 
-			i, (u32) sc->rx_bd_chain_paddr[i]);
+			i, (u_int32_t) sc->rx_bd_chain_paddr[i]);
 	}
 
 	/*
@@ -2218,10 +2218,10 @@ bnx_release_resources(struct bnx_softc *sc)
 /*   0 for success, positive value for failure.                             */
 /****************************************************************************/
 int
-bnx_fw_sync(struct bnx_softc *sc, u32 msg_data)
+bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data)
 {
 	int i, rc = 0;
-	u32 val;
+	u_int32_t val;
 
 	/* Don't waste any time if we've timed out before. */
 	if (sc->bnx_fw_timed_out) {
@@ -2275,11 +2275,11 @@ bnx_fw_sync_exit:
 /*   Nothing.                                                               */
 /****************************************************************************/
 void
-bnx_load_rv2p_fw(struct bnx_softc *sc, u32 *rv2p_code, 
-	u32 rv2p_code_len, u32 rv2p_proc)
+bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 
+	u_int32_t rv2p_code_len, u_int32_t rv2p_proc)
 {
 	int i;
-	u32 val;
+	u_int32_t val;
 
 	for (i = 0; i < rv2p_code_len; i += 8) {
 		REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code);
@@ -2319,8 +2319,8 @@ void
 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg,
 	struct fw_info *fw)
 {
-	u32 offset;
-	u32 val;
+	u_int32_t offset;
+	u_int32_t val;
 
 	/* Halt the CPU. */
 	val = REG_RD_IND(sc, cpu_reg->mode);
@@ -2608,11 +2608,11 @@ bnx_init_cpus(struct bnx_softc *sc)
 void
 bnx_init_context(struct bnx_softc *sc)
 {
-	u32 vcid;
+	u_int32_t vcid;
 
 	vcid = 96;
 	while (vcid) {
-		u32 vcid_addr, pcid_addr, offset;
+		u_int32_t vcid_addr, pcid_addr, offset;
 
 		vcid--;
 
@@ -2641,7 +2641,7 @@ bnx_init_context(struct bnx_softc *sc)
 void
 bnx_get_mac_addr(struct bnx_softc *sc)
 {
-	u32 mac_lo = 0, mac_hi = 0;
+	u_int32_t mac_lo = 0, mac_hi = 0;
 
 	/*
 	 * The NetXtreme II bootcode populates various NIC
@@ -2681,8 +2681,8 @@ bnx_get_mac_addr(struct bnx_softc *sc)
 void
 bnx_set_mac_addr(struct bnx_softc *sc)
 {
-	u32 val;
-	u8 *mac_addr = sc->eaddr;
+	u_int32_t val;
+	u_int8_t *mac_addr = sc->eaddr;
 
 	DBPRINT(sc, BNX_INFO, "Setting Ethernet address = %6D\n", sc->eaddr, ":");
 
@@ -2763,9 +2763,9 @@ bnx_stop(struct bnx_softc *sc)
 }
 
 int
-bnx_reset(struct bnx_softc *sc, u32 reset_code)
+bnx_reset(struct bnx_softc *sc, u_int32_t reset_code)
 {
-	u32 val;
+	u_int32_t val;
 	int i, rc = 0;
 
 	DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
@@ -2847,7 +2847,7 @@ int
 bnx_chipinit(struct bnx_softc *sc)
 {
 	struct pci_attach_args *pa = &(sc->bnx_pa);
-	u32 val;
+	u_int32_t val;
 	int rc = 0;
 
 	DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
@@ -2885,7 +2885,7 @@ bnx_chipinit(struct bnx_softc *sc)
 
 	/* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */
 	if (sc->bnx_flags & BNX_PCIX_FLAG) {
-		u16 val;
+		u_int16_t val;
 
 		val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD);
 		pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, val & ~0x2);
@@ -2943,7 +2943,7 @@ bnx_chipinit_exit:
 int
 bnx_blockinit(struct bnx_softc *sc)
 {
-	u32 reg, val;
+	u_int32_t reg, val;
 	int rc = 0;
 
 	DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
@@ -3057,15 +3057,15 @@ bnx_blockinit_exit:
 /*   0 for success, positive value for failure.                             */
 /****************************************************************************/
 int
-bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u16 *prod, u16 *chain_prod, 
-	u32 *prod_bseq)
+bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u_int16_t *prod, u_int16_t *chain_prod, 
+	u_int32_t *prod_bseq)
 {
 	bus_dmamap_t		map;
 	struct mbuf *m_new = NULL;
 	struct rx_bd		*rxbd;
 	int i, rc = 0;
 #ifdef BNX_DEBUG
-	u16 debug_chain_prod = *chain_prod;
+	u_int16_t debug_chain_prod = *chain_prod;
 #endif
 
 	DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 
@@ -3074,7 +3074,7 @@ bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u16 *prod, u16 *chain_prod,
 	/* Make sure the inputs are valid. */
 	DBRUNIF((*chain_prod > MAX_RX_BD),
 		printf("%s: RX producer out of range: 0x%04X > 0x%04X\n",
-		*chain_prod, (u16) MAX_RX_BD));
+		*chain_prod, (u_int16_t) MAX_RX_BD));
 
 	DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
 		"prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq);
@@ -3144,7 +3144,7 @@ bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u16 *prod, u16 *chain_prod,
 	/* Watch for overflow. */
 	DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
 		printf("%s: Too many free rx_bd (0x%04X > 0x%04X)!\n", 
-			sc->free_rx_bd, (u16) USABLE_RX_BD));
+			sc->free_rx_bd, (u_int16_t) USABLE_RX_BD));
 
 	DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 
 		sc->rx_low_watermark = sc->free_rx_bd);
@@ -3201,7 +3201,7 @@ int
 bnx_init_tx_chain(struct bnx_softc *sc)
 {
 	struct tx_bd *txbd;
-	u32 val;
+	u_int32_t val;
 	int i, rc = 0;
 
 	DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
@@ -3313,8 +3313,8 @@ bnx_init_rx_chain(struct bnx_softc *sc)
 {
 	struct rx_bd *rxbd;
 	int i, rc = 0;
-	u16 prod, chain_prod;
-	u32 prod_bseq, val;
+	u_int16_t prod, chain_prod;
+	u_int32_t prod_bseq, val;
 
 	DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
 
@@ -3496,7 +3496,7 @@ bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 void
 bnx_phy_intr(struct bnx_softc *sc)
 {
-	u32 new_link_state, old_link_state;
+	u_int32_t new_link_state, old_link_state;
 
 	new_link_state = sc->status_block->status_attn_bits &
 		STATUS_ATTN_BITS_LINK_STATE;
@@ -3540,8 +3540,8 @@ bnx_rx_intr(struct bnx_softc *sc)
 {
 	struct status_block *sblk = sc->status_block;
 	struct ifnet *ifp = &sc->arpcom.ac_if;
-	u16 hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
-	u32 sw_prod_bseq;
+	u_int16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
+	u_int32_t sw_prod_bseq;
 	struct l2_fhdr *l2fhdr;
 	int i;
 
@@ -3584,7 +3584,7 @@ bnx_rx_intr(struct bnx_softc *sc)
 		struct mbuf *m;
 		struct rx_bd *rxbd;
 		unsigned int len;
-		u32 status;
+		u_int32_t status;
 
 		/* Convert the producer/consumer indices to an actual rx_bd index. */
 		sw_chain_cons = RX_CHAIN_IDX(sw_cons);
@@ -3810,7 +3810,7 @@ bnx_tx_intr(struct bnx_softc *sc)
 {
 	struct status_block *sblk = sc->status_block;
 	struct ifnet *ifp = &sc->arpcom.ac_if;
-	u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
+	u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
 
 	DBRUNIF(1, sc->tx_interrupts++);
 
@@ -3938,7 +3938,7 @@ bnx_disable_intr(struct bnx_softc *sc)
 void
 bnx_enable_intr(struct bnx_softc *sc)
 {
-	u32 val;
+	u_int32_t val;
 
 	REG_WR(sc, BNX_PCICFG_INT_ACK_CMD,
 	       BNX_PCICFG_INT_ACK_CMD_INDEX_VALID |
@@ -3962,7 +3962,7 @@ bnx_init(void *xsc)
 {
 	struct bnx_softc *sc = (struct bnx_softc *)xsc;
 	struct ifnet *ifp = &sc->arpcom.ac_if;
-	u32 ether_mtu;
+	u_int32_t ether_mtu;
 	int s;
 
 	DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
@@ -4056,10 +4056,10 @@ bnx_init_locked_exit:
 /*   0 for success, positive value for failure.                             */
 /****************************************************************************/
 int
-bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m_head, u16 *prod,
-	u16 *chain_prod, u32 *prod_bseq)
+bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m_head, u_int16_t *prod,
+	u_int16_t *chain_prod, u_int32_t *prod_bseq)
 {
-	u32 vlan_tag_flags = 0;
+	u_int32_t vlan_tag_flags = 0;
 #ifdef BNX_VLAN
 	struct m_tag *mtag;
 #endif
@@ -4157,8 +4157,8 @@ bnx_start(struct ifnet *ifp)
 	struct bnx_softc *sc = ifp->if_softc;
 	struct mbuf *m_head = NULL;
 	int count = 0;
-	u16 tx_prod, tx_chain_prod;
-	u32	tx_prod_bseq;
+	u_int16_t tx_prod, tx_chain_prod;
+	u_int32_t	tx_prod_bseq;
 
 	/* If there's no link or the transmit queue is empty then just exit. */
 	if (!sc->bnx_link || IFQ_IS_EMPTY(&ifp->if_snd)) {
@@ -4369,7 +4369,7 @@ bnx_intr(void *xsc)
 {
 	struct bnx_softc *sc;
 	struct ifnet *ifp;
-	u32 status_attn_bits;
+	u_int32_t status_attn_bits;
 
 	sc = xsc;
 	ifp = &sc->arpcom.ac_if;
@@ -4478,8 +4478,8 @@ bnx_set_rx_mode(struct bnx_softc *sc)
 	struct ifnet *ifp = &ac->ac_if;
 	struct ether_multi *enm;
 	struct ether_multistep step;
-	u32 hashes[4] = { 0, 0, 0, 0 };
-	u32 rx_mode, sort_mode;
+	u_int32_t hashes[4] = { 0, 0, 0, 0 };
+	u_int32_t rx_mode, sort_mode;
 	int h, i;
 
 	/* Initialize receive mode default settings. */
@@ -4595,44 +4595,44 @@ bnx_stats_update(struct bnx_softc *sc)
 	 * hardware statistics.
 	 */
 	sc->stat_IfHCInOctets = 
-		((u64) stats->stat_IfHCInOctets_hi << 32) + 
-		 (u64) stats->stat_IfHCInOctets_lo;
+		((u_int64_t) stats->stat_IfHCInOctets_hi << 32) + 
+		 (u_int64_t) stats->stat_IfHCInOctets_lo;
 
 	sc->stat_IfHCInBadOctets =
-		((u64) stats->stat_IfHCInBadOctets_hi << 32) + 
-		 (u64) stats->stat_IfHCInBadOctets_lo;
+		((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 
+		 (u_int64_t) stats->stat_IfHCInBadOctets_lo;
 
 	sc->stat_IfHCOutOctets =
-		((u64) stats->stat_IfHCOutOctets_hi << 32) +
-		 (u64) stats->stat_IfHCOutOctets_lo;
+		((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) +
+		 (u_int64_t) stats->stat_IfHCOutOctets_lo;
 
 	sc->stat_IfHCOutBadOctets =
-		((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
-		 (u64) stats->stat_IfHCOutBadOctets_lo;
+		((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) +
+		 (u_int64_t) stats->stat_IfHCOutBadOctets_lo;
 
 	sc->stat_IfHCInUcastPkts =
-		((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
-		 (u64) stats->stat_IfHCInUcastPkts_lo;
+		((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) +
+		 (u_int64_t) stats->stat_IfHCInUcastPkts_lo;
 
 	sc->stat_IfHCInMulticastPkts =
-		((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
-		 (u64) stats->stat_IfHCInMulticastPkts_lo;
+		((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) +
+		 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo;
 
 	sc->stat_IfHCInBroadcastPkts =
-		((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
-		 (u64) stats->stat_IfHCInBroadcastPkts_lo;
+		((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) +
+		 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo;
 
 	sc->stat_IfHCOutUcastPkts =
-		((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
-		 (u64) stats->stat_IfHCOutUcastPkts_lo;
+		((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) +
+		 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo;
 
 	sc->stat_IfHCOutMulticastPkts =
-		((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
-		 (u64) stats->stat_IfHCOutMulticastPkts_lo;
+		((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) +
+		 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo;
 
 	sc->stat_IfHCOutBroadcastPkts =
-		((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
-		 (u64) stats->stat_IfHCOutBroadcastPkts_lo;
+		((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
+		 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo;
 
 	sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
 		stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
@@ -4775,13 +4775,13 @@ bnx_tick(void *xsc)
 	struct bnx_softc *sc = xsc;
 	struct ifnet *ifp = &sc->arpcom.ac_if;
 	struct mii_data *mii = NULL;
-	u32 msg;
+	u_int32_t msg;
 
 	/* Tell the firmware that the driver is still running. */
 #ifdef BNX_DEBUG
-	msg = (u32) BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE;
+	msg = (u_int32_t) BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE;
 #else
-	msg = (u32) ++sc->bnx_fw_drv_pulse_wr_seq;
+	msg = (u_int32_t) ++sc->bnx_fw_drv_pulse_wr_seq;
 #endif
 	REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg);
 
@@ -4827,7 +4827,7 @@ bnx_tick_locked_exit:
 void
 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m)
 {
-	u32 val_hi, val_lo;
+	u_int32_t val_hi, val_lo;
 	struct mbuf *mp = m;
 
 	if (m == NULL) {
@@ -4982,12 +4982,12 @@ bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count)
 		"----------------------------\n");
 
 	BNX_PRINTF(sc, "page size      = 0x%08X, tx chain pages        = 0x%08X\n",
-		(u32) BCM_PAGE_SIZE, (u32) TX_PAGES);
+		(u_int32_t) BCM_PAGE_SIZE, (u_int32_t) TX_PAGES);
 
 	BNX_PRINTF(sc, "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
-		(u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
+		(u_int32_t) TOTAL_TX_BD_PER_PAGE, (u_int32_t) USABLE_TX_BD_PER_PAGE);
 
-	BNX_PRINTF(sc, "total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD);
+	BNX_PRINTF(sc, "total tx_bd    = 0x%08X\n", (u_int32_t) TOTAL_TX_BD);
 
 	BNX_PRINTF(sc, ""
 		"-----------------------------"
@@ -5025,12 +5025,12 @@ bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count)
 	BNX_PRINTF(sc, "----- RX_BD Chain -----\n");
 
 	BNX_PRINTF(sc, "page size      = 0x%08X, rx chain pages        = 0x%08X\n",
-		(u32) BCM_PAGE_SIZE, (u32) RX_PAGES);
+		(u_int32_t) BCM_PAGE_SIZE, (u_int32_t) RX_PAGES);
 
 	BNX_PRINTF(sc, "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
-		(u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
+		(u_int32_t) TOTAL_RX_BD_PER_PAGE, (u_int32_t) USABLE_RX_BD_PER_PAGE);
 
-	BNX_PRINTF(sc, "total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD);
+	BNX_PRINTF(sc, "total rx_bd    = 0x%08X\n", (u_int32_t) TOTAL_RX_BD);
 
 	BNX_PRINTF(sc,
 		"----------------------------"
@@ -5363,7 +5363,7 @@ bnx_dump_stats_block(struct bnx_softc *sc)
 void
 bnx_dump_driver_state(struct bnx_softc *sc)
 {
-	u32 val_hi, val_lo;
+	u_int32_t val_hi, val_lo;
 
 	BNX_PRINTF(sc,
 		"-----------------------------"
@@ -5446,7 +5446,7 @@ bnx_dump_driver_state(struct bnx_softc *sc)
 		sc->free_rx_bd);
 
 	BNX_PRINTF(sc, "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n",
-		sc->rx_low_watermark, (u32) USABLE_RX_BD);
+		sc->rx_low_watermark, (u_int32_t) USABLE_RX_BD);
 
 	BNX_PRINTF(sc, "         0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n",
 		sc->tx_mbuf_alloc);
@@ -5458,7 +5458,7 @@ bnx_dump_driver_state(struct bnx_softc *sc)
 		sc->used_tx_bd);
 
 	BNX_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
-		sc->tx_hi_watermark, (u32) USABLE_TX_BD);
+		sc->tx_hi_watermark, (u_int32_t) USABLE_TX_BD);
 
 	BNX_PRINTF(sc, "         0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n",
 		sc->mbuf_alloc_failed);
@@ -5472,7 +5472,7 @@ bnx_dump_driver_state(struct bnx_softc *sc)
 void
 bnx_dump_hw_state(struct bnx_softc *sc)
 {
-	u32 val1;
+	u_int32_t val1;
 	int i;
 
 	BNX_PRINTF(sc,
diff --git a/sys/dev/pci/if_bnxreg.h b/sys/dev/pci/if_bnxreg.h
index d42e2f0985a..d0b532aea73 100644
--- a/sys/dev/pci/if_bnxreg.h
+++ b/sys/dev/pci/if_bnxreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_bnxreg.h,v 1.5 2006/08/10 01:03:00 brad Exp $	*/
+/*	$OpenBSD: if_bnxreg.h,v 1.6 2006/08/10 04:01:52 brad Exp $	*/
 
 /*-
  * Copyright (c) 2006 Broadcom Corporation
@@ -77,14 +77,6 @@
 #include <dev/mii/brgphyreg.h>
 
 /****************************************************************************/
-/* Conversion to OpenBSD type definitions.                                  */
-/****************************************************************************/
-#define u64 uint64_t
-#define u32	uint32_t
-#define u16	uint16_t
-#define u8	uint8_t
-
-/****************************************************************************/
 /* Debugging macros and definitions.                                        */
 /****************************************************************************/
 #define BNX_CP_LOAD 			0x00000001
@@ -326,17 +318,17 @@ struct bnx_type {
 #define FLASH_BACKUP_STRAP_MASK			(0xf << 26)
 
 struct flash_spec {
-	u32 strapping;
-	u32 config1;
-	u32 config2;
-	u32 config3;
-	u32 write1;
-	u32 buffered;
-	u32 page_bits;
-	u32 page_size;
-	u32 addr_mask;
-	u32 total_size;
-	u8  *name;
+	u_int32_t strapping;
+	u_int32_t config1;
+	u_int32_t config2;
+	u_int32_t config3;
+	u_int32_t write1;
+	u_int32_t buffered;
+	u_int32_t page_bits;
+	u_int32_t page_size;
+	u_int32_t addr_mask;
+	u_int32_t total_size;
+	u_int8_t  *name;
 };
 
 
@@ -680,11 +672,11 @@ struct flash_spec {
 #define BNX_STATS(x)			(u_long) stats->stat_ ## x ## _lo
 
 #ifdef __LP64__
-#define BNX_ADDR_LO(y)			((u64)(y) & 0xffffffff)
-#define BNX_ADDR_HI(y)			((u64)(y) >> 32)
+#define BNX_ADDR_LO(y)			((u_int64_t)(y) & 0xffffffff)
+#define BNX_ADDR_HI(y)			((u_int64_t)(y) >> 32)
 #else
-#define BNX_ADDR_LO(y)			((u32)(y))
-#define BNX_ADDR_HI(y)			((u32)0)
+#define BNX_ADDR_LO(y)			((u_int32_t)(y))
+#define BNX_ADDR_HI(y)			((u_int32_t)0)
 #endif
 
 /*
@@ -703,10 +695,10 @@ struct flash_spec {
  *  tx_bd definition
  */
 struct tx_bd {
-	u32 tx_bd_haddr_hi;
-	u32 tx_bd_haddr_lo;
-	u32 tx_bd_mss_nbytes;
-	u32 tx_bd_vlan_tag_flags;
+	u_int32_t tx_bd_haddr_hi;
+	u_int32_t tx_bd_haddr_lo;
+	u_int32_t tx_bd_mss_nbytes;
+	u_int32_t tx_bd_vlan_tag_flags;
 		#define TX_BD_FLAGS_CONN_FAULT		(1<<0)
 		#define TX_BD_FLAGS_TCP_UDP_CKSUM	(1<<1)
 		#define TX_BD_FLAGS_IP_CKSUM		(1<<2)
@@ -727,10 +719,10 @@ struct tx_bd {
  *  rx_bd definition
  */
 struct rx_bd {
-	u32 rx_bd_haddr_hi;
-	u32 rx_bd_haddr_lo;
-	u32 rx_bd_len;
-	u32 rx_bd_flags;
+	u_int32_t rx_bd_haddr_hi;
+	u_int32_t rx_bd_haddr_lo;
+	u_int32_t rx_bd_len;
+	u_int32_t rx_bd_flags;
 		#define RX_BD_FLAGS_NOPUSH		(1<<0)
 		#define RX_BD_FLAGS_DUMMY		(1<<1)
 		#define RX_BD_FLAGS_END			(1<<2)
@@ -743,7 +735,7 @@ struct rx_bd {
  *  status_block definition
  */
 struct status_block {
-	u32 status_attn_bits;
+	u_int32_t status_attn_bits;
 		#define STATUS_ATTN_BITS_LINK_STATE		(1L<<0)
 		#define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT	(1L<<1)
 		#define STATUS_ATTN_BITS_TX_BD_READ_ABORT	(1L<<2)
@@ -774,57 +766,57 @@ struct status_block {
 		#define STATUS_ATTN_BITS_GRC_ABORT		(1L<<27)
 		#define STATUS_ATTN_BITS_PARITY_ERROR		(1L<<31)
 
-	u32 status_attn_bits_ack;
+	u_int32_t status_attn_bits_ack;
 #if BYTE_ORDER == BIG_ENDIAN
-	u16 status_tx_quick_consumer_index0;
-	u16 status_tx_quick_consumer_index1;
-	u16 status_tx_quick_consumer_index2;
-	u16 status_tx_quick_consumer_index3;
-	u16 status_rx_quick_consumer_index0;
-	u16 status_rx_quick_consumer_index1;
-	u16 status_rx_quick_consumer_index2;
-	u16 status_rx_quick_consumer_index3;
-	u16 status_rx_quick_consumer_index4;
-	u16 status_rx_quick_consumer_index5;
-	u16 status_rx_quick_consumer_index6;
-	u16 status_rx_quick_consumer_index7;
-	u16 status_rx_quick_consumer_index8;
-	u16 status_rx_quick_consumer_index9;
-	u16 status_rx_quick_consumer_index10;
-	u16 status_rx_quick_consumer_index11;
-	u16 status_rx_quick_consumer_index12;
-	u16 status_rx_quick_consumer_index13;
-	u16 status_rx_quick_consumer_index14;
-	u16 status_rx_quick_consumer_index15;
-	u16 status_completion_producer_index;
-	u16 status_cmd_consumer_index;
-	u16 status_idx;
-	u16 status_unused;
+	u_int16_t status_tx_quick_consumer_index0;
+	u_int16_t status_tx_quick_consumer_index1;
+	u_int16_t status_tx_quick_consumer_index2;
+	u_int16_t status_tx_quick_consumer_index3;
+	u_int16_t status_rx_quick_consumer_index0;
+	u_int16_t status_rx_quick_consumer_index1;
+	u_int16_t status_rx_quick_consumer_index2;
+	u_int16_t status_rx_quick_consumer_index3;
+	u_int16_t status_rx_quick_consumer_index4;
+	u_int16_t status_rx_quick_consumer_index5;
+	u_int16_t status_rx_quick_consumer_index6;
+	u_int16_t status_rx_quick_consumer_index7;
+	u_int16_t status_rx_quick_consumer_index8;
+	u_int16_t status_rx_quick_consumer_index9;
+	u_int16_t status_rx_quick_consumer_index10;
+	u_int16_t status_rx_quick_consumer_index11;
+	u_int16_t status_rx_quick_consumer_index12;
+	u_int16_t status_rx_quick_consumer_index13;
+	u_int16_t status_rx_quick_consumer_index14;
+	u_int16_t status_rx_quick_consumer_index15;
+	u_int16_t status_completion_producer_index;
+	u_int16_t status_cmd_consumer_index;
+	u_int16_t status_idx;
+	u_int16_t status_unused;
 #elif BYTE_ORDER == LITTLE_ENDIAN
-	u16 status_tx_quick_consumer_index1;
-	u16 status_tx_quick_consumer_index0;
-	u16 status_tx_quick_consumer_index3;
-	u16 status_tx_quick_consumer_index2;
-	u16 status_rx_quick_consumer_index1;
-	u16 status_rx_quick_consumer_index0;
-	u16 status_rx_quick_consumer_index3;
-	u16 status_rx_quick_consumer_index2;
-	u16 status_rx_quick_consumer_index5;
-	u16 status_rx_quick_consumer_index4;
-	u16 status_rx_quick_consumer_index7;
-	u16 status_rx_quick_consumer_index6;
-	u16 status_rx_quick_consumer_index9;
-	u16 status_rx_quick_consumer_index8;
-	u16 status_rx_quick_consumer_index11;
-	u16 status_rx_quick_consumer_index10;
-	u16 status_rx_quick_consumer_index13;
-	u16 status_rx_quick_consumer_index12;
-	u16 status_rx_quick_consumer_index15;
-	u16 status_rx_quick_consumer_index14;
-	u16 status_cmd_consumer_index;
-	u16 status_completion_producer_index;
-	u16 status_unused;
-	u16 status_idx;
+	u_int16_t status_tx_quick_consumer_index1;
+	u_int16_t status_tx_quick_consumer_index0;
+	u_int16_t status_tx_quick_consumer_index3;
+	u_int16_t status_tx_quick_consumer_index2;
+	u_int16_t status_rx_quick_consumer_index1;
+	u_int16_t status_rx_quick_consumer_index0;
+	u_int16_t status_rx_quick_consumer_index3;
+	u_int16_t status_rx_quick_consumer_index2;
+	u_int16_t status_rx_quick_consumer_index5;
+	u_int16_t status_rx_quick_consumer_index4;
+	u_int16_t status_rx_quick_consumer_index7;
+	u_int16_t status_rx_quick_consumer_index6;
+	u_int16_t status_rx_quick_consumer_index9;
+	u_int16_t status_rx_quick_consumer_index8;
+	u_int16_t status_rx_quick_consumer_index11;
+	u_int16_t status_rx_quick_consumer_index10;
+	u_int16_t status_rx_quick_consumer_index13;
+	u_int16_t status_rx_quick_consumer_index12;
+	u_int16_t status_rx_quick_consumer_index15;
+	u_int16_t status_rx_quick_consumer_index14;
+	u_int16_t status_cmd_consumer_index;
+	u_int16_t status_completion_producer_index;
+	u_int16_t status_unused;
+	u_int16_t status_idx;
 #endif
 };
 
@@ -833,86 +825,86 @@ struct status_block {
  *  statistics_block definition
  */
 struct statistics_block {
-	u32 stat_IfHCInOctets_hi;
-	u32 stat_IfHCInOctets_lo;
-	u32 stat_IfHCInBadOctets_hi;
-	u32 stat_IfHCInBadOctets_lo;
-	u32 stat_IfHCOutOctets_hi;
-	u32 stat_IfHCOutOctets_lo;
-	u32 stat_IfHCOutBadOctets_hi;
-	u32 stat_IfHCOutBadOctets_lo;
-	u32 stat_IfHCInUcastPkts_hi;
-	u32 stat_IfHCInUcastPkts_lo;
-	u32 stat_IfHCInMulticastPkts_hi;
-	u32 stat_IfHCInMulticastPkts_lo;
-	u32 stat_IfHCInBroadcastPkts_hi;
-	u32 stat_IfHCInBroadcastPkts_lo;
-	u32 stat_IfHCOutUcastPkts_hi;
-	u32 stat_IfHCOutUcastPkts_lo;
-	u32 stat_IfHCOutMulticastPkts_hi;
-	u32 stat_IfHCOutMulticastPkts_lo;
-	u32 stat_IfHCOutBroadcastPkts_hi;
-	u32 stat_IfHCOutBroadcastPkts_lo;
-	u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
-	u32 stat_Dot3StatsCarrierSenseErrors;
-	u32 stat_Dot3StatsFCSErrors;
-	u32 stat_Dot3StatsAlignmentErrors;
-	u32 stat_Dot3StatsSingleCollisionFrames;
-	u32 stat_Dot3StatsMultipleCollisionFrames;
-	u32 stat_Dot3StatsDeferredTransmissions;
-	u32 stat_Dot3StatsExcessiveCollisions;
-	u32 stat_Dot3StatsLateCollisions;
-	u32 stat_EtherStatsCollisions;
-	u32 stat_EtherStatsFragments;
-	u32 stat_EtherStatsJabbers;
-	u32 stat_EtherStatsUndersizePkts;
-	u32 stat_EtherStatsOverrsizePkts;
-	u32 stat_EtherStatsPktsRx64Octets;
-	u32 stat_EtherStatsPktsRx65Octetsto127Octets;
-	u32 stat_EtherStatsPktsRx128Octetsto255Octets;
-	u32 stat_EtherStatsPktsRx256Octetsto511Octets;
-	u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
-	u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
-	u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
-	u32 stat_EtherStatsPktsTx64Octets;
-	u32 stat_EtherStatsPktsTx65Octetsto127Octets;
-	u32 stat_EtherStatsPktsTx128Octetsto255Octets;
-	u32 stat_EtherStatsPktsTx256Octetsto511Octets;
-	u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
-	u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
-	u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
-	u32 stat_XonPauseFramesReceived;
-	u32 stat_XoffPauseFramesReceived;
-	u32 stat_OutXonSent;
-	u32 stat_OutXoffSent;
-	u32 stat_FlowControlDone;
-	u32 stat_MacControlFramesReceived;
-	u32 stat_XoffStateEntered;
-	u32 stat_IfInFramesL2FilterDiscards;
-	u32 stat_IfInRuleCheckerDiscards;
-	u32 stat_IfInFTQDiscards;
-	u32 stat_IfInMBUFDiscards;
-	u32 stat_IfInRuleCheckerP4Hit;
-	u32 stat_CatchupInRuleCheckerDiscards;
-	u32 stat_CatchupInFTQDiscards;
-	u32 stat_CatchupInMBUFDiscards;
-	u32 stat_CatchupInRuleCheckerP4Hit;
-	u32 stat_GenStat00;
-	u32 stat_GenStat01;
-	u32 stat_GenStat02;
-	u32 stat_GenStat03;
-	u32 stat_GenStat04;
-	u32 stat_GenStat05;
-	u32 stat_GenStat06;
-	u32 stat_GenStat07;
-	u32 stat_GenStat08;
-	u32 stat_GenStat09;
-	u32 stat_GenStat10;
-	u32 stat_GenStat11;
-	u32 stat_GenStat12;
-	u32 stat_GenStat13;
-	u32 stat_GenStat14;
-	u32 stat_GenStat15;
+	u_int32_t stat_IfHCInOctets_hi;
+	u_int32_t stat_IfHCInOctets_lo;
+	u_int32_t stat_IfHCInBadOctets_hi;
+	u_int32_t stat_IfHCInBadOctets_lo;
+	u_int32_t stat_IfHCOutOctets_hi;
+	u_int32_t stat_IfHCOutOctets_lo;
+	u_int32_t stat_IfHCOutBadOctets_hi;
+	u_int32_t stat_IfHCOutBadOctets_lo;
+	u_int32_t stat_IfHCInUcastPkts_hi;
+	u_int32_t stat_IfHCInUcastPkts_lo;
+	u_int32_t stat_IfHCInMulticastPkts_hi;
+	u_int32_t stat_IfHCInMulticastPkts_lo;
+	u_int32_t stat_IfHCInBroadcastPkts_hi;
+	u_int32_t stat_IfHCInBroadcastPkts_lo;
+	u_int32_t stat_IfHCOutUcastPkts_hi;
+	u_int32_t stat_IfHCOutUcastPkts_lo;
+	u_int32_t stat_IfHCOutMulticastPkts_hi;
+	u_int32_t stat_IfHCOutMulticastPkts_lo;
+	u_int32_t stat_IfHCOutBroadcastPkts_hi;
+	u_int32_t stat_IfHCOutBroadcastPkts_lo;
+	u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
+	u_int32_t stat_Dot3StatsCarrierSenseErrors;
+	u_int32_t stat_Dot3StatsFCSErrors;
+	u_int32_t stat_Dot3StatsAlignmentErrors;
+	u_int32_t stat_Dot3StatsSingleCollisionFrames;
+	u_int32_t stat_Dot3StatsMultipleCollisionFrames;
+	u_int32_t stat_Dot3StatsDeferredTransmissions;
+	u_int32_t stat_Dot3StatsExcessiveCollisions;
+	u_int32_t stat_Dot3StatsLateCollisions;
+	u_int32_t stat_EtherStatsCollisions;
+	u_int32_t stat_EtherStatsFragments;
+	u_int32_t stat_EtherStatsJabbers;
+	u_int32_t stat_EtherStatsUndersizePkts;
+	u_int32_t stat_EtherStatsOverrsizePkts;
+	u_int32_t stat_EtherStatsPktsRx64Octets;
+	u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets;
+	u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets;
+	u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets;
+	u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
+	u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
+	u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
+	u_int32_t stat_EtherStatsPktsTx64Octets;
+	u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets;
+	u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets;
+	u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets;
+	u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
+	u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
+	u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
+	u_int32_t stat_XonPauseFramesReceived;
+	u_int32_t stat_XoffPauseFramesReceived;
+	u_int32_t stat_OutXonSent;
+	u_int32_t stat_OutXoffSent;
+	u_int32_t stat_FlowControlDone;
+	u_int32_t stat_MacControlFramesReceived;
+	u_int32_t stat_XoffStateEntered;
+	u_int32_t stat_IfInFramesL2FilterDiscards;
+	u_int32_t stat_IfInRuleCheckerDiscards;
+	u_int32_t stat_IfInFTQDiscards;
+	u_int32_t stat_IfInMBUFDiscards;
+	u_int32_t stat_IfInRuleCheckerP4Hit;
+	u_int32_t stat_CatchupInRuleCheckerDiscards;
+	u_int32_t stat_CatchupInFTQDiscards;
+	u_int32_t stat_CatchupInMBUFDiscards;
+	u_int32_t stat_CatchupInRuleCheckerP4Hit;
+	u_int32_t stat_GenStat00;
+	u_int32_t stat_GenStat01;
+	u_int32_t stat_GenStat02;
+	u_int32_t stat_GenStat03;
+	u_int32_t stat_GenStat04;
+	u_int32_t stat_GenStat05;
+	u_int32_t stat_GenStat06;
+	u_int32_t stat_GenStat07;
+	u_int32_t stat_GenStat08;
+	u_int32_t stat_GenStat09;
+	u_int32_t stat_GenStat10;
+	u_int32_t stat_GenStat11;
+	u_int32_t stat_GenStat12;
+	u_int32_t stat_GenStat13;
+	u_int32_t stat_GenStat14;
+	u_int32_t stat_GenStat15;
 };
 
 
@@ -920,7 +912,7 @@ struct statistics_block {
  *  l2_fhdr definition
  */
 struct l2_fhdr {
-	u32 l2_fhdr_status;
+	u_int32_t l2_fhdr_status;
 		#define L2_FHDR_STATUS_RULE_CLASS	(0x7<<0)
 		#define L2_FHDR_STATUS_RULE_P2		(1<<3)
 		#define L2_FHDR_STATUS_RULE_P3		(1<<4)
@@ -940,17 +932,17 @@ struct l2_fhdr {
 		#define L2_FHDR_ERRORS_TCP_XSUM		(1<<28)
 		#define L2_FHDR_ERRORS_UDP_XSUM		(1<<31)
 
-	u32 l2_fhdr_hash;
+	u_int32_t l2_fhdr_hash;
 #if BYTE_ORDER == BIG_ENDIAN
-	u16 l2_fhdr_pkt_len;
-	u16 l2_fhdr_vlan_tag;
-	u16 l2_fhdr_ip_xsum;
-	u16 l2_fhdr_tcp_udp_xsum;
+	u_int16_t l2_fhdr_pkt_len;
+	u_int16_t l2_fhdr_vlan_tag;
+	u_int16_t l2_fhdr_ip_xsum;
+	u_int16_t l2_fhdr_tcp_udp_xsum;
 #elif BYTE_ORDER == LITTLE_ENDIAN
-	u16 l2_fhdr_vlan_tag;
-	u16 l2_fhdr_pkt_len;
-	u16 l2_fhdr_tcp_udp_xsum;
-	u16 l2_fhdr_ip_xsum;
+	u_int16_t l2_fhdr_vlan_tag;
+	u_int16_t l2_fhdr_pkt_len;
+	u_int16_t l2_fhdr_tcp_udp_xsum;
+	u_int16_t l2_fhdr_ip_xsum;
 #endif
 };
 
@@ -4501,60 +4493,60 @@ struct l2_fhdr {
 /****************************************************************************/
 
 struct cpu_reg {
-	u32 mode;
-	u32 mode_value_halt;
-	u32 mode_value_sstep;
+	u_int32_t mode;
+	u_int32_t mode_value_halt;
+	u_int32_t mode_value_sstep;
 
-	u32 state;
-	u32 state_value_clear;
+	u_int32_t state;
+	u_int32_t state_value_clear;
 
-	u32 gpr0;
-	u32 evmask;
-	u32 pc;
-	u32 inst;
-	u32 bp;
+	u_int32_t gpr0;
+	u_int32_t evmask;
+	u_int32_t pc;
+	u_int32_t inst;
+	u_int32_t bp;
 
-	u32 spad_base;
+	u_int32_t spad_base;
 
-	u32 mips_view_base;
+	u_int32_t mips_view_base;
 };
 
 struct fw_info {
-	u32 ver_major;
-	u32 ver_minor;
-	u32 ver_fix;
+	u_int32_t ver_major;
+	u_int32_t ver_minor;
+	u_int32_t ver_fix;
 
-	u32 start_addr;
+	u_int32_t start_addr;
 
 	/* Text section. */
-	u32 text_addr;
-	u32 text_len;
-	u32 text_index;
-	u32 *text;
+	u_int32_t text_addr;
+	u_int32_t text_len;
+	u_int32_t text_index;
+	u_int32_t *text;
 
 	/* Data section. */
-	u32 data_addr;
-	u32 data_len;
-	u32 data_index;
-	u32 *data;
+	u_int32_t data_addr;
+	u_int32_t data_len;
+	u_int32_t data_index;
+	u_int32_t *data;
 
 	/* SBSS section. */
-	u32 sbss_addr;
-	u32 sbss_len;
-	u32 sbss_index;
-	u32 *sbss;
+	u_int32_t sbss_addr;
+	u_int32_t sbss_len;
+	u_int32_t sbss_index;
+	u_int32_t *sbss;
 
 	/* BSS section. */
-	u32 bss_addr;
-	u32 bss_len;
-	u32 bss_index;
-	u32 *bss;
+	u_int32_t bss_addr;
+	u_int32_t bss_len;
+	u_int32_t bss_index;
+	u_int32_t *bss;
 
 	/* Read-only section. */
-	u32 rodata_addr;
-	u32 rodata_len;
-	u32 rodata_index;
-	u32 *rodata;
+	u_int32_t rodata_addr;
+	u_int32_t rodata_len;
+	u_int32_t rodata_index;
+	u_int32_t *rodata;
 };
 
 #define RV2P_PROC1                              0
@@ -4608,11 +4600,11 @@ struct fw_info {
 struct bnx_dmamap_arg {
 	struct bnx_softc	*sc;				/* Pointer back to device context */
 	bus_addr_t			busaddr;		/* Physical address of mapped memory */
-	u32					tx_flags;		/* Flags for frame transmit */
-	u16					prod;
-	u16					chain_prod;
+	u_int32_t					tx_flags;		/* Flags for frame transmit */
+	u_int16_t					prod;
+	u_int16_t					chain_prod;
 	int					maxsegs;		/* Max segments supported for this mapped memory */
-	u32					prod_bseq;
+	u_int32_t					prod_bseq;
 	struct tx_bd		*tx_chain[TX_PAGES];
 };
 
@@ -4633,10 +4625,10 @@ struct bnx_softc
 	void				*bnx_shutdownhook;
 
 	/* ASIC Chip ID. */
-	u32					bnx_chipid;
+	u_int32_t					bnx_chipid;
 
 	/* General controller flags. */
-	u32					bnx_flags;
+	u_int32_t					bnx_flags;
 #define BNX_PCIX_FLAG			0x01
 #define BNX_PCI_32BIT_FLAG 		0x02
 #define BNX_ONE_TDMA_FLAG		0x04		/* Deprecated */
@@ -4646,7 +4638,7 @@ struct bnx_softc
 #define BNX_MFW_ENABLE_FLAG		0x40
 
 	/* PHY specific flags. */
-	u32					bnx_phy_flags;
+	u_int32_t					bnx_phy_flags;
 #define BNX_PHY_SERDES_FLAG					1
 #define BNX_PHY_CRC_FIX_FLAG				2
 #define BNX_PHY_PARALLEL_DETECT_FLAG		4
@@ -4658,27 +4650,27 @@ struct bnx_softc
 	int					bnx_if_flags;
 
 	bus_addr_t				max_bus_addr;
-	u16					bus_speed_mhz;		/* PCI bus speed */
+	u_int16_t					bus_speed_mhz;		/* PCI bus speed */
 	struct flash_spec	*bnx_flash_info;	/* Flash NVRAM settings */
-	u32					bnx_flash_size;		/* Flash NVRAM size */
-	u32					bnx_shmem_base;		/* Shared Memory base address */
+	u_int32_t					bnx_flash_size;		/* Flash NVRAM size */
+	u_int32_t					bnx_shmem_base;		/* Shared Memory base address */
 	char *				bnx_name;			/* Name string */
 
 	/* Tracks the version of bootcode firmware. */
-	u32					bnx_fw_ver;
+	u_int32_t					bnx_fw_ver;
 
 	/* Tracks the state of the firmware.  0 = Running while any     */
 	/* other value indicates that the firmware is not responding.   */
-	u16					bnx_fw_timed_out;
+	u_int16_t					bnx_fw_timed_out;
 
 	/* An incrementing sequence used to coordinate messages passed   */
 	/* from the driver to the firmware.                              */
-	u16					bnx_fw_wr_seq;
+	u_int16_t					bnx_fw_wr_seq;
 
 	/* An incrementing sequence used to let the firmware know that   */
 	/* the driver is still operating.  Without the pulse, management */
 	/* firmware such as IPMI or UMP will operate in OS absent state. */
-	u16					bnx_fw_drv_pulse_wr_seq;
+	u_int16_t					bnx_fw_drv_pulse_wr_seq;
 
 	/* Ethernet MAC address. */
 	u_char				eaddr[6];
@@ -4686,21 +4678,21 @@ struct bnx_softc
 	/* These setting are used by the host coalescing (HC) block to   */
 	/* to control how often the status block, statistics block and   */
 	/* interrupts are generated.                                     */
-	u16					bnx_tx_quick_cons_trip_int;
-	u16					bnx_tx_quick_cons_trip;
-	u16					bnx_rx_quick_cons_trip_int;
-	u16					bnx_rx_quick_cons_trip;
-	u16					bnx_comp_prod_trip_int;
-	u16					bnx_comp_prod_trip;
-	u16					bnx_tx_ticks_int;
-	u16					bnx_tx_ticks;
-	u16					bnx_rx_ticks_int;
-	u16					bnx_rx_ticks;
-	u16					bnx_com_ticks_int;
-	u16					bnx_com_ticks;
-	u16					bnx_cmd_ticks_int;
-	u16					bnx_cmd_ticks;
-	u32					bnx_stats_ticks;
+	u_int16_t					bnx_tx_quick_cons_trip_int;
+	u_int16_t					bnx_tx_quick_cons_trip;
+	u_int16_t					bnx_rx_quick_cons_trip_int;
+	u_int16_t					bnx_rx_quick_cons_trip;
+	u_int16_t					bnx_comp_prod_trip_int;
+	u_int16_t					bnx_comp_prod_trip;
+	u_int16_t					bnx_tx_ticks_int;
+	u_int16_t					bnx_tx_ticks;
+	u_int16_t					bnx_rx_ticks_int;
+	u_int16_t					bnx_rx_ticks;
+	u_int16_t					bnx_com_ticks_int;
+	u_int16_t					bnx_com_ticks;
+	u_int16_t					bnx_cmd_ticks_int;
+	u_int16_t					bnx_cmd_ticks;
+	u_int32_t					bnx_stats_ticks;
 
 	/* The address of the integrated PHY on the MII bus. */
 	int					bnx_phy_addr;
@@ -4709,22 +4701,22 @@ struct bnx_softc
 	struct mii_data				bnx_mii;
 
 	/* Driver maintained TX chain pointers and byte counter. */
-	u16					rx_prod;
-	u16					rx_cons;
-	u32					rx_prod_bseq;	/* Counts the bytes used.  */
-	u16					tx_prod;
-	u16					tx_cons;
-	u32					tx_prod_bseq;	/* Counts the bytes used.  */
+	u_int16_t					rx_prod;
+	u_int16_t					rx_cons;
+	u_int32_t					rx_prod_bseq;	/* Counts the bytes used.  */
+	u_int16_t					tx_prod;
+	u_int16_t					tx_cons;
+	u_int32_t					tx_prod_bseq;	/* Counts the bytes used.  */
 
 	int					bnx_link;
 	struct timeout				bnx_timeout;
 
 	/* Frame size and mbuf allocation size for RX frames. */
-	u32					max_frame_size;
+	u_int32_t					max_frame_size;
 	int					mbuf_alloc_size;
 
 	/* Receive mode settings (i.e promiscuous, multicast, etc.). */
-	u32					rx_mode;
+	u_int32_t					rx_mode;
 
 	/* Bus tag for the bnx controller. */
 	bus_dma_tag_t		bnx_dmatag;
@@ -4751,9 +4743,9 @@ struct bnx_softc
 	bus_addr_t			status_block_paddr;			/* Physical address */
 
 	/* Driver maintained status block values. */
-	u16					last_status_idx;
-	u16					hw_rx_cons;
-	u16					hw_tx_cons;
+	u_int16_t					last_status_idx;
+	u_int16_t					hw_rx_cons;
+	u_int16_t					hw_tx_cons;
 
 	/* H/W maintained statistics block. */
 	bus_dma_segment_t	stats_seg;
@@ -4777,65 +4769,65 @@ struct bnx_softc
 	struct mbuf			*rx_mbuf_ptr[TOTAL_RX_BD];
 
 	/* Track the number of rx_bd and tx_bd's in use. */
-	u16 free_rx_bd;
-	u16 used_tx_bd;
+	u_int16_t free_rx_bd;
+	u_int16_t used_tx_bd;
 
 	/* Provides access to hardware statistics through sysctl. */
-	u64 stat_IfHCInOctets;
-	u64 stat_IfHCInBadOctets;
-	u64 stat_IfHCOutOctets;
-	u64 stat_IfHCOutBadOctets;
-	u64 stat_IfHCInUcastPkts;
-	u64 stat_IfHCInMulticastPkts;
-	u64 stat_IfHCInBroadcastPkts;
-	u64 stat_IfHCOutUcastPkts;
-	u64 stat_IfHCOutMulticastPkts;
-	u64 stat_IfHCOutBroadcastPkts;
-
-	u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
-	u32 stat_Dot3StatsCarrierSenseErrors;
-	u32 stat_Dot3StatsFCSErrors;
-	u32 stat_Dot3StatsAlignmentErrors;
-	u32 stat_Dot3StatsSingleCollisionFrames;
-	u32 stat_Dot3StatsMultipleCollisionFrames;
-	u32 stat_Dot3StatsDeferredTransmissions;
-	u32 stat_Dot3StatsExcessiveCollisions;
-	u32 stat_Dot3StatsLateCollisions;
-	u32 stat_EtherStatsCollisions;
-	u32 stat_EtherStatsFragments;
-	u32 stat_EtherStatsJabbers;
-	u32 stat_EtherStatsUndersizePkts;
-	u32 stat_EtherStatsOverrsizePkts;
-	u32 stat_EtherStatsPktsRx64Octets;
-	u32 stat_EtherStatsPktsRx65Octetsto127Octets;
-	u32 stat_EtherStatsPktsRx128Octetsto255Octets;
-	u32 stat_EtherStatsPktsRx256Octetsto511Octets;
-	u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
-	u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
-	u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
-	u32 stat_EtherStatsPktsTx64Octets;
-	u32 stat_EtherStatsPktsTx65Octetsto127Octets;
-	u32 stat_EtherStatsPktsTx128Octetsto255Octets;
-	u32 stat_EtherStatsPktsTx256Octetsto511Octets;
-	u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
-	u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
-	u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
-	u32 stat_XonPauseFramesReceived;
-	u32 stat_XoffPauseFramesReceived;
-	u32 stat_OutXonSent;
-	u32 stat_OutXoffSent;
-	u32 stat_FlowControlDone;
-	u32 stat_MacControlFramesReceived;
-	u32 stat_XoffStateEntered;
-	u32 stat_IfInFramesL2FilterDiscards;
-	u32 stat_IfInRuleCheckerDiscards;
-	u32 stat_IfInFTQDiscards;
-	u32 stat_IfInMBUFDiscards;
-	u32 stat_IfInRuleCheckerP4Hit;
-	u32 stat_CatchupInRuleCheckerDiscards;
-	u32 stat_CatchupInFTQDiscards;
-	u32 stat_CatchupInMBUFDiscards;
-	u32 stat_CatchupInRuleCheckerP4Hit;
+	u_int64_t stat_IfHCInOctets;
+	u_int64_t stat_IfHCInBadOctets;
+	u_int64_t stat_IfHCOutOctets;
+	u_int64_t stat_IfHCOutBadOctets;
+	u_int64_t stat_IfHCInUcastPkts;
+	u_int64_t stat_IfHCInMulticastPkts;
+	u_int64_t stat_IfHCInBroadcastPkts;
+	u_int64_t stat_IfHCOutUcastPkts;
+	u_int64_t stat_IfHCOutMulticastPkts;
+	u_int64_t stat_IfHCOutBroadcastPkts;
+
+	u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
+	u_int32_t stat_Dot3StatsCarrierSenseErrors;
+	u_int32_t stat_Dot3StatsFCSErrors;
+	u_int32_t stat_Dot3StatsAlignmentErrors;
+	u_int32_t stat_Dot3StatsSingleCollisionFrames;
+	u_int32_t stat_Dot3StatsMultipleCollisionFrames;
+	u_int32_t stat_Dot3StatsDeferredTransmissions;
+	u_int32_t stat_Dot3StatsExcessiveCollisions;
+	u_int32_t stat_Dot3StatsLateCollisions;
+	u_int32_t stat_EtherStatsCollisions;
+	u_int32_t stat_EtherStatsFragments;
+	u_int32_t stat_EtherStatsJabbers;
+	u_int32_t stat_EtherStatsUndersizePkts;
+	u_int32_t stat_EtherStatsOverrsizePkts;
+	u_int32_t stat_EtherStatsPktsRx64Octets;
+	u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets;
+	u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets;
+	u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets;
+	u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
+	u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
+	u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
+	u_int32_t stat_EtherStatsPktsTx64Octets;
+	u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets;
+	u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets;
+	u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets;
+	u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
+	u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
+	u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
+	u_int32_t stat_XonPauseFramesReceived;
+	u_int32_t stat_XoffPauseFramesReceived;
+	u_int32_t stat_OutXonSent;
+	u_int32_t stat_OutXoffSent;
+	u_int32_t stat_FlowControlDone;
+	u_int32_t stat_MacControlFramesReceived;
+	u_int32_t stat_XoffStateEntered;
+	u_int32_t stat_IfInFramesL2FilterDiscards;
+	u_int32_t stat_IfInRuleCheckerDiscards;
+	u_int32_t stat_IfInFTQDiscards;
+	u_int32_t stat_IfInMBUFDiscards;
+	u_int32_t stat_IfInRuleCheckerP4Hit;
+	u_int32_t stat_CatchupInRuleCheckerDiscards;
+	u_int32_t stat_CatchupInFTQDiscards;
+	u_int32_t stat_CatchupInMBUFDiscards;
+	u_int32_t stat_CatchupInRuleCheckerP4Hit;
 
 #ifdef BNX_DEBUG
 	/* Track the number of enqueued mbufs. */
@@ -4843,17 +4835,17 @@ struct bnx_softc
 	int rx_mbuf_alloc;
 
 	/* Track how many and what type of interrupts are generated. */
-	u32 interrupts_generated;
-	u32 interrupts_handled;
-	u32 rx_interrupts;
-	u32 tx_interrupts;
-
-	u32	rx_low_watermark;			/* Lowest number of rx_bd's free. */
-	u32 tx_hi_watermark;			/* Greatest number of tx_bd's used. */
-	u32	mbuf_alloc_failed;			/* Mbuf allocation failure counter. */
-	u32 l2fhdr_status_errors;
-	u32 unexpected_attentions;
-	u32	lost_status_block_updates;
+	u_int32_t interrupts_generated;
+	u_int32_t interrupts_handled;
+	u_int32_t rx_interrupts;
+	u_int32_t tx_interrupts;
+
+	u_int32_t	rx_low_watermark;			/* Lowest number of rx_bd's free. */
+	u_int32_t tx_hi_watermark;			/* Greatest number of tx_bd's used. */
+	u_int32_t	mbuf_alloc_failed;			/* Mbuf allocation failure counter. */
+	u_int32_t l2fhdr_status_errors;
+	u_int32_t unexpected_attentions;
+	u_int32_t	lost_status_block_updates;
 #endif
 };