Turn GetCPSR() into an inline get_cpsr(), and remove more dead code.

4 files changed, 17 insertions, 91 deletions

diff --git a/sys/arch/arm/arm/arm32_machdep.c b/sys/arch/arm/arm/arm32_machdep.c
index f2a1b1d6d0d..0a0f4992ce4 100644
--- a/sys/arch/arm/arm/arm32_machdep.c
+++ b/sys/arch/arm/arm/arm32_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: arm32_machdep.c,v 1.21 2006/05/26 17:06:39 miod Exp $	*/
+/*	$OpenBSD: arm32_machdep.c,v 1.22 2006/07/12 17:29:53 miod Exp $	*/
 /*	$NetBSD: arm32_machdep.c,v 1.42 2003/12/30 12:33:15 pk Exp $	*/
 
 /*
@@ -224,7 +224,7 @@ bootsync(int howto)
 	bootsyncdone = 1;
 
 	/* Make sure we can still manage to do things */
-	if (GetCPSR() & I32_bit) {
+	if (__get_cpsr() & I32_bit) {
 		/*
 		 * If we get here then boot has been called without RB_NOSYNC
 		 * and interrupts were disabled. This means the boot() call
diff --git a/sys/arch/arm/arm/setcpsr.S b/sys/arch/arm/arm/setcpsr.S
deleted file mode 100644
index 27b4c642971..00000000000
--- a/sys/arch/arm/arm/setcpsr.S
+++ /dev/null
@@ -1,79 +0,0 @@
-/*	$OpenBSD: setcpsr.S,v 1.2 2004/02/01 06:10:33 drahn Exp $	*/
-/*	$NetBSD: setcpsr.S,v 1.2 2002/08/15 01:37:02 briggs Exp $	*/
-
-/*
- * Copyright (c) 1994 Mark Brinicombe.
- * Copyright (c) 1994 Brini.
- * All rights reserved.
- *
- * This code is derived from software written for Brini by Mark Brinicombe
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Brini.
- * 4. The name of the company nor the name of the author may be used to
- *    endorse or promote products derived from this software without specific
- *    prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RiscBSD kernel project
- *
- * setcpsr.S
- *
- * Miscellaneous routines to play with the CPSR register
- *
- * Eventually this routine can be inline assembly.
- *
- * Created      : 12/09/94
- *
- * Based of kate/display/setcpsr.s
- */
-
-#include <machine/asm.h>
-
-/* Sets and clears bits in the CPSR register
- *
- *  r0 - bic mask
- *  r1 - eor mask
- */
-
-ENTRY_NP(SetCPSR)
-        mrs     r3, cpsr		/* Set the CPSR */
-	bic	r2, r3, r0
-        eor     r2, r2, r1
-        msr     cpsr_all, r2
-
-        mov	r0, r3			/* Return the old CPSR */
-
-	mov	pc, lr
-
-
-/* Gets the CPSR register
- *
- * Returns the CPSR in r0
- */
-
-ENTRY_NP(GetCPSR)
-        mrs     r0, cpsr		/* Get the CPSR */
-
-	mov	pc, lr
-
diff --git a/sys/arch/arm/conf/files.arm b/sys/arch/arm/conf/files.arm
index 5ea4c726c65..d98e1736690 100644
--- a/sys/arch/arm/conf/files.arm
+++ b/sys/arch/arm/conf/files.arm
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.arm,v 1.9 2006/07/12 17:26:19 miod Exp $
+#	$OpenBSD: files.arm,v 1.10 2006/07/12 17:29:55 miod Exp $
 #	$NetBSD: files.arm,v 1.76 2003/11/05 12:53:15 scw Exp $
 
 # CPU types.  Make sure to update <arm/cpuconf.h> if you change this list.
@@ -117,7 +117,6 @@ file	arch/arm/arm/exception.S
 file	arch/arm/arm/fault.c
 file	arch/arm/arm/mem.c
 file	arch/arm/arm/pmap.c
-file	arch/arm/arm/setcpsr.S
 file	arch/arm/arm/setstack.S
 file	arch/arm/arm/stubs.c
 file	arch/arm/arm/sys_machdep.c
diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h
index 079d88fb379..0ed7890f686 100644
--- a/sys/arch/arm/include/cpufunc.h
+++ b/sys/arch/arm/include/cpufunc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.h,v 1.2 2004/05/19 03:17:07 drahn Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.3 2006/07/12 17:29:55 miod Exp $	*/
 /*	$NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $	*/
 
 /*
@@ -429,7 +429,9 @@ void	xscale_setup		(char *string);
  * Macros for manipulating CPU interrupts
  */
 #ifdef __PROG32
-static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
+/* Functions to manipulate the CPSR. */
+static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor);
+static __inline u_int32_t __get_cpsr(void);
 
 static __inline u_int32_t
 __set_cpsr_c(u_int bic, u_int eor)
@@ -447,6 +449,16 @@ __set_cpsr_c(u_int bic, u_int eor)
 	return ret;
 }
 
+static __inline u_int32_t
+__get_cpsr()
+{
+	u_int32_t	ret;
+
+	__asm __volatile("mrs	%0, cpsr" : "=&r" (ret));
+
+	return ret;
+}
+
 #define disable_interrupts(mask)					\
 	(__set_cpsr_c((mask) & (I32_bit | F32_bit), \
 		      (mask) & (I32_bit | F32_bit)))
@@ -467,13 +479,7 @@ __set_cpsr_c(u_int bic, u_int eor)
 #define	restore_interrupts(old_r15)					\
 	(set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE),			\
 		 (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
-#endif /* __PROG32 */
 
-#ifdef __PROG32
-/* Functions to manipulate the CPSR. */
-u_int	SetCPSR(u_int bic, u_int eor);
-u_int	GetCPSR(void);
-#else
 /* Functions to manipulate the processor control bits in r15. */
 u_int	set_r15(u_int bic, u_int eor);
 u_int	get_r15(void);