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authorJonathan Gray <jsg@jsg.id.au>2013-02-02 17:27:37 +1100
committerJonathan Gray <jsg@jsg.id.au>2013-02-02 17:27:37 +1100
commit197b5dfd4e4379a588ef5e872f9777f7d486e606 (patch)
treeee9784b8b5e67f1b9e9108c9d107d2a5fcdbf438
parentcb1dd6b3a69557e83ad41d584cc8a040f0477520 (diff)
make the feature macros take drm_device instead of inteldrm_softc
Diffstat
-rw-r--r--sys/dev/pci/drm/drm_drv.c8
-rw-r--r--sys/dev/pci/drm/i915_dma.c2
-rw-r--r--sys/dev/pci/drm/i915_drv.c212
-rw-r--r--sys/dev/pci/drm/i915_drv.h119
-rw-r--r--sys/dev/pci/drm/i915_gem.c16
-rw-r--r--sys/dev/pci/drm/i915_gem_tiling.c12
-rw-r--r--sys/dev/pci/drm/i915_irq.c40
-rw-r--r--sys/dev/pci/drm/i915_suspend.c112
-rw-r--r--sys/dev/pci/drm/intel_bios.c19
-rw-r--r--sys/dev/pci/drm/intel_crt.c33
-rw-r--r--sys/dev/pci/drm/intel_display.c287
-rw-r--r--sys/dev/pci/drm/intel_dp.c46
-rw-r--r--sys/dev/pci/drm/intel_hdmi.c10
-rw-r--r--sys/dev/pci/drm/intel_i2c.c7
-rw-r--r--sys/dev/pci/drm/intel_lvds.c36
-rw-r--r--sys/dev/pci/drm/intel_overlay.c34
-rw-r--r--sys/dev/pci/drm/intel_panel.c19
-rw-r--r--sys/dev/pci/drm/intel_sdvo.c16
-rw-r--r--sys/dev/pci/drm/intel_sprite.c7
-rw-r--r--sys/dev/pci/drm/intel_tv.c4
20 files changed, 535 insertions, 504 deletions
diff --git a/sys/dev/pci/drm/drm_drv.c b/sys/dev/pci/drm/drm_drv.c
index 8ee42801749..165847485a7 100644
--- a/sys/dev/pci/drm/drm_drv.c
+++ b/sys/dev/pci/drm/drm_drv.c
@@ -99,6 +99,7 @@ drm_attach_pci(const struct drm_driver_info *driver, struct pci_attach_args *pa,
int is_agp, struct device *dev)
{
struct drm_attach_args arg;
+ pcireg_t subsys;
arg.driver = driver;
arg.dmat = pa->pa_dmat;
@@ -106,6 +107,13 @@ drm_attach_pci(const struct drm_driver_info *driver, struct pci_attach_args *pa,
arg.irq = pa->pa_intrline;
arg.is_agp = is_agp;
+ arg.pci_vendor = PCI_VENDOR(pa->pa_id);
+ arg.pci_device = PCI_PRODUCT(pa->pa_id);
+
+ subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
+ arg.pci_subvendor = PCI_VENDOR(subsys);
+ arg.pci_subdevice = PCI_PRODUCT(subsys);
+
arg.busid_len = 20;
arg.busid = malloc(arg.busid_len + 1, M_DRM, M_NOWAIT);
if (arg.busid == NULL) {
diff --git a/sys/dev/pci/drm/i915_dma.c b/sys/dev/pci/drm/i915_dma.c
index 98a6eb058d5..6f849c917ca 100644
--- a/sys/dev/pci/drm/i915_dma.c
+++ b/sys/dev/pci/drm/i915_dma.c
@@ -20,7 +20,7 @@ i915_load_modeset_init(struct drm_device *dev)
#endif
/* IIR "flip pending" bit means done if this bit is set */
- if (IS_GEN3(dev_priv) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
+ if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
dev_priv->flip_pending_is_done = true;
intel_modeset_init(dev);
diff --git a/sys/dev/pci/drm/i915_drv.c b/sys/dev/pci/drm/i915_drv.c
index 3fde08914e2..df9d325d19b 100644
--- a/sys/dev/pci/drm/i915_drv.c
+++ b/sys/dev/pci/drm/i915_drv.c
@@ -439,7 +439,7 @@ i915_drm_freeze(struct inteldrm_softc *dev_priv)
drm_irq_uninstall(dev);
}
- i915_save_state(dev_priv);
+ i915_save_state(dev);
intel_opregion_fini(dev);
@@ -461,13 +461,13 @@ i915_drm_thaw(struct inteldrm_softc *dev_priv)
}
#endif
- i915_restore_state(dev_priv);
+ i915_restore_state(dev);
intel_opregion_setup(dev);
/* KMS EnterVT equivalent */
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
ironlake_init_pch_refclk(dev);
mtx_enter(&dev->mode_config.mutex);
@@ -518,11 +518,12 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
struct drm_device *dev;
const struct drm_pcidev *id_entry;
int i;
+ uint16_t pci_device;
id_entry = drm_find_description(PCI_VENDOR(pa->pa_id),
PCI_PRODUCT(pa->pa_id), inteldrm_pciidlist);
- dev_priv->pci_device = PCI_PRODUCT(pa->pa_id);
- dev_priv->info = i915_get_device_id(dev_priv->pci_device);
+ pci_device = PCI_PRODUCT(pa->pa_id);
+ dev_priv->info = i915_get_device_id(pci_device);
KASSERT(dev_priv->info->gen != 0);
dev_priv->pc = pa->pa_pc;
@@ -530,9 +531,14 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
dev_priv->dmat = pa->pa_dmat;
dev_priv->bst = pa->pa_memt;
+ /* All intel chipsets need to be treated as agp, so just pass one */
+ dev_priv->drmdev = drm_attach_pci(&inteldrm_driver, pa, 1, self);
+
+ dev = (struct drm_device *)dev_priv->drmdev;
+
/* we need to use this api for now due to sharing with intagp */
bar = vga_pci_bar_info((struct vga_pci_softc *)parent,
- (IS_I9XX(dev_priv) ? 0 : 1));
+ (IS_I9XX(dev) ? 0 : 1));
if (bar == NULL) {
printf(": can't get BAR info\n");
return;
@@ -549,7 +555,7 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
* i945G/GM report MSI capability despite not actually supporting it.
* so explicitly disable it.
*/
- if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
+ if (IS_I945G(dev) || IS_I945GM(dev))
pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED;
if (pci_intr_map(pa, &dev_priv->ih) != 0) {
@@ -562,7 +568,7 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
* on until the X server talks to us, kms will change this.
*/
dev_priv->irqh = pci_intr_establish(dev_priv->pc, dev_priv->ih, IPL_TTY,
- (HAS_PCH_SPLIT(dev_priv) ? inteldrm_ironlake_intr : inteldrm_intr),
+ (HAS_PCH_SPLIT(dev) ? inteldrm_ironlake_intr : inteldrm_intr),
dev_priv, dev_priv->dev.dv_xname);
if (dev_priv->irqh == NULL) {
printf(": couldn't establish interrupt\n");
@@ -570,7 +576,7 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
}
/* Unmask the interrupts that we always want on. */
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
dev_priv->irq_mask_reg = ~PCH_SPLIT_DISPLAY_INTR_FIX;
/* masked for now, turned on on demand */
dev_priv->gt_irq_mask_reg = ~PCH_SPLIT_RENDER_INTR_FIX;
@@ -598,7 +604,7 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
dev_priv->mm.suspended = 1;
/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
- if (IS_GEN3(dev_priv)) {
+ if (IS_GEN3(dev)) {
u_int32_t tmp = I915_READ(MI_ARB_STATE);
if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
/*
@@ -613,24 +619,24 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
/* For the X server, in kms mode this will not be needed */
dev_priv->fence_reg_start = 3;
- if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
- IS_I945GM(dev_priv) || IS_G33(dev_priv))
+ if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) ||
+ IS_I945GM(dev) || IS_G33(dev))
dev_priv->num_fence_regs = 16;
else
dev_priv->num_fence_regs = 8;
/* Initialise fences to zero, else on some macs we'll get corruption */
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
+ if (IS_GEN6(dev) || IS_GEN7(dev)) {
for (i = 0; i < 16; i++)
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
- } else if (INTEL_INFO(dev_priv)->gen >= 4) {
+ } else if (INTEL_INFO(dev)->gen >= 4) {
for (i = 0; i < 16; i++)
I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
} else {
for (i = 0; i < 8; i++)
I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
- if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
- IS_G33(dev_priv))
+ if (IS_I945G(dev) || IS_I945GM(dev) ||
+ IS_G33(dev))
for (i = 0; i < 8; i++)
I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
}
@@ -641,10 +647,10 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
}
/* Set up the IFP for chipset flushing */
- if (IS_I915G(dev_priv) || IS_I915GM(dev_priv) || IS_I945G(dev_priv) ||
- IS_I945GM(dev_priv)) {
+ if (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) ||
+ IS_I945GM(dev)) {
i915_alloc_ifp(dev_priv, &bpa);
- } else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_G33(dev_priv)) {
+ } else if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev)) {
i965_alloc_ifp(dev_priv, &bpa);
} else {
int nsegs;
@@ -666,7 +672,7 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
inteldrm_detect_bit_6_swizzle(dev_priv, &bpa);
/* Init HWS */
- if (!I915_NEED_GFX_HWS(dev_priv)) {
+ if (!I915_NEED_GFX_HWS(dev)) {
if (i915_init_phys_hws(dev_priv, pa->pa_dmat) != 0) {
printf(": couldn't alloc HWS page\n");
return;
@@ -681,20 +687,15 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
mtx_init(&dev_priv->fence_lock, IPL_NONE);
mtx_init(&dev_priv->gt_lock, IPL_NONE);
- if (IS_IVYBRIDGE(dev_priv))
+ if (IS_IVYBRIDGE(dev))
dev_priv->num_pipe = 3;
- else if (IS_MOBILE(dev_priv) || !IS_GEN2(dev_priv))
+ else if (IS_MOBILE(dev) || !IS_GEN2(dev))
dev_priv->num_pipe = 2;
else
dev_priv->num_pipe = 1;
intel_detect_pch(dev_priv);
- /* All intel chipsets need to be treated as agp, so just pass one */
- dev_priv->drmdev = drm_attach_pci(&inteldrm_driver, pa, 1, self);
-
- dev = (struct drm_device *)dev_priv->drmdev;
-
intel_opregion_setup(dev);
intel_setup_bios(dev);
intel_setup_gmbus(dev_priv);
@@ -727,7 +728,8 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
int
inteldrm_detach(struct device *self, int flags)
{
- struct inteldrm_softc *dev_priv = (struct inteldrm_softc *)self;
+ struct inteldrm_softc *dev_priv = (struct inteldrm_softc *)self;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
/* this will quiesce any dma that's going on and kill the timeouts. */
if (dev_priv->drmdev != NULL) {
@@ -735,7 +737,7 @@ inteldrm_detach(struct device *self, int flags)
dev_priv->drmdev = NULL;
}
- if (!I915_NEED_GFX_HWS(dev_priv) && dev_priv->hws_dmamem) {
+ if (!I915_NEED_GFX_HWS(dev) && dev_priv->hws_dmamem) {
drm_dmamem_free(dev_priv->dmat, dev_priv->hws_dmamem);
dev_priv->hws_dmamem = NULL;
/* Need to rewrite hardware status page */
@@ -743,11 +745,11 @@ inteldrm_detach(struct device *self, int flags)
dev_priv->hw_status_page = NULL;
}
- if (IS_I9XX(dev_priv) && dev_priv->ifp.i9xx.bsh != 0) {
+ if (IS_I9XX(dev) && dev_priv->ifp.i9xx.bsh != 0) {
bus_space_unmap(dev_priv->ifp.i9xx.bst, dev_priv->ifp.i9xx.bsh,
PAGE_SIZE);
- } else if ((IS_I830(dev_priv) || IS_845G(dev_priv) || IS_I85X(dev_priv) ||
- IS_I865G(dev_priv)) && dev_priv->ifp.i8xx.kva != NULL) {
+ } else if ((IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) ||
+ IS_I865G(dev)) && dev_priv->ifp.i8xx.kva != NULL) {
bus_dmamem_unmap(dev_priv->dmat, dev_priv->ifp.i8xx.kva,
PAGE_SIZE);
bus_dmamem_free(dev_priv->dmat, &dev_priv->ifp.i8xx.seg, 1);
@@ -765,16 +767,17 @@ int
inteldrm_activate(struct device *arg, int act)
{
struct inteldrm_softc *dev_priv = (struct inteldrm_softc *)arg;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
switch (act) {
case DVACT_QUIESCE:
inteldrm_quiesce(dev_priv);
break;
case DVACT_SUSPEND:
- i915_save_state(dev_priv);
+ i915_save_state(dev);
break;
case DVACT_RESUME:
- i915_restore_state(dev_priv);
+ i915_restore_state(dev);
/* entrypoints can stop sleeping now */
atomic_clearbits_int(&dev_priv->sc_flags, INTELDRM_QUIET);
wakeup(&dev_priv->flags);
@@ -905,7 +908,7 @@ inteldrm_ironlake_intr(void *arg)
pm_iir = I915_READ(GEN6_PMIIR);
if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
- (!IS_GEN6(dev_priv) || pm_iir == 0))
+ (!IS_GEN6(dev) || pm_iir == 0))
goto done;
ret = 1;
@@ -917,7 +920,7 @@ inteldrm_ironlake_intr(void *arg)
if (gt_iir & GT_RENDER_CS_ERROR_INTERRUPT)
inteldrm_error(dev_priv);
- if (IS_GEN7(dev_priv)) {
+ if (IS_GEN7(dev)) {
for (i = 0; i < 3; i++) {
if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
drm_handle_vblank(dev, i);
@@ -1007,7 +1010,7 @@ inteldrm_read_hws(struct inteldrm_softc *dev_priv, int reg)
bus_dmamap_t map;
u_int32_t val;
- if (I915_NEED_GFX_HWS(dev_priv)) {
+ if (I915_NEED_GFX_HWS(dev)) {
obj_priv = (struct drm_i915_gem_object *)dev_priv->hws_obj;
map = obj_priv->dmamap;
tag = dev_priv->agpdmat;
@@ -1035,7 +1038,7 @@ ring_wait_for_space(struct intel_ring_buffer *ring, int n)
u_int32_t acthd_reg, acthd, last_acthd, last_head;
int i;
- acthd_reg = INTEL_INFO(dev_priv)->gen >= 4 ? ACTHD_I965 : ACTHD;
+ acthd_reg = INTEL_INFO(dev)->gen >= 4 ? ACTHD_I965 : ACTHD;
last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
last_acthd = I915_READ(acthd_reg);
@@ -1238,11 +1241,13 @@ nope:
void
inteldrm_chipset_flush(struct inteldrm_softc *dev_priv)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+
/*
* Write to this flush page flushes the chipset write cache.
* The write will return when it is done.
*/
- if (IS_I9XX(dev_priv)) {
+ if (IS_I9XX(dev)) {
if (dev_priv->ifp.i9xx.bsh != 0)
bus_space_write_4(dev_priv->ifp.i9xx.bst,
dev_priv->ifp.i9xx.bsh, 0, 1);
@@ -1297,11 +1302,12 @@ int
inteldrm_getparam(struct inteldrm_softc *dev_priv, void *data)
{
drm_i915_getparam_t *param = data;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
int value;
switch (param->param) {
case I915_PARAM_CHIPSET_ID:
- value = dev_priv->pci_device;
+ value = dev->pci_device;
break;
case I915_PARAM_HAS_GEM:
value = 1;
@@ -1554,8 +1560,9 @@ u_int32_t
i915_gem_flush(struct inteldrm_softc *dev_priv, uint32_t invalidate_domains,
uint32_t flush_domains)
{
- uint32_t cmd;
- int ret = 0;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+ uint32_t cmd;
+ int ret = 0;
if (flush_domains & I915_GEM_DOMAIN_CPU)
inteldrm_chipset_flush(dev_priv);
@@ -1597,7 +1604,7 @@ i915_gem_flush(struct inteldrm_softc *dev_priv, uint32_t invalidate_domains,
* On the 965, the sampler cache always gets flushed
* and this bit is reserved.
*/
- if (INTEL_INFO(dev_priv)->gen < 4 &&
+ if (INTEL_INFO(dev)->gen < 4 &&
invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
cmd |= MI_READ_FLUSH;
if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
@@ -1788,7 +1795,7 @@ again:
reg->obj = obj;
TAILQ_INSERT_TAIL(&dev_priv->mm.fence_list, reg, list);
- switch (INTEL_INFO(dev_priv)->gen) {
+ switch (INTEL_INFO(dev)->gen) {
case 7:
case 6:
sandybridge_write_fence_reg(reg);
@@ -2147,7 +2154,7 @@ i915_dispatch_gem_execbuffer(struct drm_device *dev,
exec_start = (uint32_t)exec_offset + exec->batch_start_offset;
exec_len = (uint32_t)exec->batch_len;
- if (IS_I830(dev_priv) || IS_845G(dev_priv)) {
+ if (IS_I830(dev) || IS_845G(dev)) {
BEGIN_LP_RING(6);
OUT_RING(MI_BATCH_BUFFER);
OUT_RING(exec_start | MI_BATCH_NON_SECURE);
@@ -2155,8 +2162,8 @@ i915_dispatch_gem_execbuffer(struct drm_device *dev,
OUT_RING(MI_NOOP);
} else {
BEGIN_LP_RING(4);
- if (INTEL_INFO(dev_priv)->gen >= 4) {
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
+ if (INTEL_INFO(dev)->gen >= 4) {
+ if (IS_GEN6(dev) || IS_GEN7(dev))
OUT_RING(MI_BATCH_BUFFER_START |
MI_BATCH_NON_SECURE_I965);
else
@@ -2287,7 +2294,7 @@ i915_gem_init_hws(struct inteldrm_softc *dev_priv)
/* If we need a physical address for the status page, it's already
* initialized at driver load time.
*/
- if (!I915_NEED_GFX_HWS(dev_priv))
+ if (!I915_NEED_GFX_HWS(dev))
return 0;
obj = drm_gem_object_alloc(dev, 4096);
@@ -2336,10 +2343,11 @@ void
cleanup_status_page(struct intel_ring_buffer *ring)
{
drm_i915_private_t *dev_priv = ring->dev->dev_private;
+ struct drm_device *dev = ring->dev;
struct drm_obj *obj;
struct drm_i915_gem_object *obj_priv;
- if (!I915_NEED_GFX_HWS(dev_priv) || dev_priv->hws_obj == NULL)
+ if (!I915_NEED_GFX_HWS(dev) || dev_priv->hws_obj == NULL)
return;
obj = dev_priv->hws_obj;
@@ -2456,10 +2464,10 @@ init_ring_common(struct intel_ring_buffer *ring)
/* Update our cache of the ring state */
inteldrm_update_ring(ring);
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
I915_WRITE(MI_MODE | MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE,
(VS_TIMER_DISPATCH) << 15 | VS_TIMER_DISPATCH);
- else if (IS_I9XX(dev_priv) && !IS_GEN3(dev_priv))
+ else if (IS_I9XX(dev) && !IS_GEN3(dev))
I915_WRITE(MI_MODE, (VS_TIMER_DISPATCH) << 15 |
VS_TIMER_DISPATCH);
@@ -2482,17 +2490,18 @@ inteldrm_timeout(void *arg)
void
inteldrm_error(struct inteldrm_softc *dev_priv)
{
- u_int32_t eir, ipeir;
- u_int8_t reset = GRDOM_RENDER;
- char *errbitstr;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+ u_int32_t eir, ipeir;
+ u_int8_t reset = GRDOM_RENDER;
+ char *errbitstr;
eir = I915_READ(EIR);
if (eir == 0)
return;
- if (IS_IRONLAKE(dev_priv)) {
+ if (IS_IRONLAKE(dev)) {
errbitstr = "\20\x05PTEE\x04MPVE\x03CPVE";
- } else if (IS_G4X(dev_priv)) {
+ } else if (IS_G4X(dev)) {
errbitstr = "\20\x10 BCSINSTERR\x06PTEERR\x05MPVERR\x04CPVERR"
"\x03 BCSPTEERR\x02REFRESHERR\x01INSTERR";
} else {
@@ -2500,13 +2509,13 @@ inteldrm_error(struct inteldrm_softc *dev_priv)
}
printf("render error detected, EIR: %b\n", eir, errbitstr);
- if (IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
+ if (IS_IRONLAKE(dev) || IS_GEN6(dev) || IS_GEN7(dev)) {
if (eir & I915_ERROR_PAGE_TABLE) {
dev_priv->mm.wedged = 1;
reset = GRDOM_FULL;
}
} else {
- if (IS_G4X(dev_priv)) {
+ if (IS_G4X(dev)) {
if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
printf(" IPEIR: 0x%08x\n",
I915_READ(IPEIR_I965));
@@ -2528,7 +2537,7 @@ inteldrm_error(struct inteldrm_softc *dev_priv)
reset = GRDOM_FULL;
}
- } else if (IS_I9XX(dev_priv) && eir & I915_ERROR_PAGE_TABLE) {
+ } else if (IS_I9XX(dev) && eir & I915_ERROR_PAGE_TABLE) {
printf(" PGTBL_ER: 0x%08x\n", I915_READ(PGTBL_ER));
dev_priv->mm.wedged = 1;
reset = GRDOM_FULL;
@@ -2542,7 +2551,7 @@ inteldrm_error(struct inteldrm_softc *dev_priv)
if (eir & I915_ERROR_INSTRUCTION) {
printf(" INSTPM: 0x%08x\n",
I915_READ(INSTPM));
- if (INTEL_INFO(dev_priv)->gen < 4) {
+ if (INTEL_INFO(dev)->gen < 4) {
ipeir = I915_READ(IPEIR);
printf(" IPEIR: 0x%08x\n",
@@ -2586,8 +2595,8 @@ inteldrm_error(struct inteldrm_softc *dev_priv)
if (dev_priv->mm.wedged == 0)
DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
I915_WRITE(EMR, I915_READ(EMR) | eir);
- if (IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv) ||
- IS_GEN7(dev_priv)) {
+ if (IS_IRONLAKE(dev) || IS_GEN6(dev) ||
+ IS_GEN7(dev)) {
I915_WRITE(GTIIR, GT_RENDER_CS_ERROR_INTERRUPT);
} else {
I915_WRITE(IIR,
@@ -2613,7 +2622,7 @@ inteldrm_hung(void *arg, void *reset_type)
u_int8_t reset = (u_int8_t)(uintptr_t)reset_type;
DRM_LOCK();
- if (HAS_RESET(dev_priv)) {
+ if (HAS_RESET(dev)) {
DRM_INFO("resetting gpu: ");
inteldrm_965_reset(dev_priv, reset);
printf("done!\n");
@@ -2650,7 +2659,7 @@ inteldrm_hung(void *arg, void *reset_type)
/* unbind everything */
(void)i915_gem_evict_inactive(dev_priv, 0);
- if (HAS_RESET(dev_priv))
+ if (HAS_RESET(dev))
dev_priv->mm.wedged = 0;
DRM_UNLOCK();
}
@@ -2659,6 +2668,7 @@ void
inteldrm_hangcheck(void *arg)
{
struct inteldrm_softc *dev_priv = arg;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
u_int32_t acthd, instdone, instdone1;
/* are we idle? no requests, or ring is empty */
@@ -2669,7 +2679,7 @@ inteldrm_hangcheck(void *arg)
return;
}
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
acthd = I915_READ(ACTHD_I965);
instdone = I915_READ(INSTDONE_I965);
instdone1 = I915_READ(INSTDONE1);
@@ -2685,7 +2695,7 @@ inteldrm_hangcheck(void *arg)
dev_priv->mm.last_instdone1 == instdone1) {
/* if that's twice we didn't hit it, then we're hung */
if (++dev_priv->mm.hang_cnt >= 2) {
- if (!IS_GEN2(dev_priv)) {
+ if (!IS_GEN2(dev)) {
u_int32_t tmp = I915_READ(PRB0_CTL);
if (tmp & RING_WAIT) {
I915_WRITE(PRB0_CTL, tmp);
@@ -2803,14 +2813,15 @@ int
inteldrm_setup_mchbar(struct inteldrm_softc *dev_priv,
struct pci_attach_args *bpa)
{
- u_int64_t mchbar_addr;
- pcireg_t tmp, low, high = 0;
- u_long addr;
- int reg, ret = 1, enabled = 0;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+ u_int64_t mchbar_addr;
+ pcireg_t tmp, low, high = 0;
+ u_long addr;
+ int reg, ret = 1, enabled = 0;
- reg = INTEL_INFO(dev_priv)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
- if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
+ if (IS_I915G(dev) || IS_I915GM(dev)) {
tmp = pci_conf_read(bpa->pa_pc, bpa->pa_tag, DEVEN_REG);
enabled = !!(tmp & DEVEN_MCHBAR_EN);
} else {
@@ -2822,7 +2833,7 @@ inteldrm_setup_mchbar(struct inteldrm_softc *dev_priv,
return (0);
}
- if (INTEL_INFO(dev_priv)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
high = pci_conf_read(bpa->pa_pc, bpa->pa_tag, reg + 4);
low = pci_conf_read(bpa->pa_pc, bpa->pa_tag, reg);
mchbar_addr = ((u_int64_t)high << 32) | low;
@@ -2845,7 +2856,7 @@ inteldrm_setup_mchbar(struct inteldrm_softc *dev_priv,
mchbar_addr = addr;
ret = 2;
/* We've allocated it, now fill in the BAR again */
- if (INTEL_INFO(dev_priv)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
pci_conf_write(bpa->pa_pc, bpa->pa_tag,
reg + 4, upper_32_bits(mchbar_addr));
pci_conf_write(bpa->pa_pc, bpa->pa_tag,
@@ -2853,7 +2864,7 @@ inteldrm_setup_mchbar(struct inteldrm_softc *dev_priv,
}
}
/* set the enable bit */
- if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
+ if (IS_I915G(dev) || IS_I915GM(dev)) {
pci_conf_write(bpa->pa_pc, bpa->pa_tag, DEVEN_REG,
tmp | DEVEN_MCHBAR_EN);
} else {
@@ -2872,15 +2883,16 @@ void
inteldrm_teardown_mchbar(struct inteldrm_softc *dev_priv,
struct pci_attach_args *bpa, int disable)
{
- u_int64_t mchbar_addr;
- pcireg_t tmp, low, high = 0;
- int reg;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+ u_int64_t mchbar_addr;
+ pcireg_t tmp, low, high = 0;
+ int reg;
- reg = INTEL_INFO(dev_priv)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
switch(disable) {
case 2:
- if (INTEL_INFO(dev_priv)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
high = pci_conf_read(bpa->pa_pc, bpa->pa_tag, reg + 4);
low = pci_conf_read(bpa->pa_pc, bpa->pa_tag, reg);
mchbar_addr = ((u_int64_t)high << 32) | low;
@@ -2888,7 +2900,7 @@ inteldrm_teardown_mchbar(struct inteldrm_softc *dev_priv,
extent_free(bpa->pa_memex, mchbar_addr, MCHBAR_SIZE, 0);
/* FALLTHROUGH */
case 1:
- if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
+ if (IS_I915G(dev) || IS_I915GM(dev)) {
tmp = pci_conf_read(bpa->pa_pc, bpa->pa_tag, DEVEN_REG);
tmp &= ~DEVEN_MCHBAR_EN;
pci_conf_write(bpa->pa_pc, bpa->pa_tag, DEVEN_REG, tmp);
@@ -2912,24 +2924,25 @@ void
inteldrm_detect_bit_6_swizzle(struct inteldrm_softc *dev_priv,
struct pci_attach_args *bpa)
{
- uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
- uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
- int need_disable;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+ uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
+ uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
+ int need_disable;
- if (!IS_I9XX(dev_priv)) {
+ if (!IS_I9XX(dev)) {
/* As far as we know, the 865 doesn't have these bit 6
* swizzling issues.
*/
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
- } else if (HAS_PCH_SPLIT(dev_priv)) {
+ } else if (HAS_PCH_SPLIT(dev)) {
/*
* On ironlake and sandybridge the swizzling is the same
* no matter what the DRAM config
*/
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
- } else if (IS_MOBILE(dev_priv)) {
+ } else if (IS_MOBILE(dev)) {
uint32_t dcc;
/* try to enable MCHBAR, a lot of biosen disable it */
@@ -3128,9 +3141,10 @@ i915_gem_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
bus_size_t
i915_get_fence_size(struct inteldrm_softc *dev_priv, bus_size_t size)
{
- bus_size_t i, start;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+ bus_size_t i, start;
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
/* 965 can have fences anywhere, so align to gpu-page size */
return ((size + (4096 - 1)) & ~(4096 - 1));
} else {
@@ -3138,7 +3152,7 @@ i915_get_fence_size(struct inteldrm_softc *dev_priv, bus_size_t size)
* Align the size to a power of two greater than the smallest
* fence size.
*/
- if (IS_I9XX(dev_priv))
+ if (IS_I9XX(dev))
start = 1024 * 1024;
else
start = 512 * 1024;
@@ -3154,16 +3168,15 @@ int
i915_gem_object_fence_offset_ok(struct drm_obj *obj, int tiling_mode)
{
struct drm_device *dev = obj->dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
if (obj_priv->dmamap == NULL || tiling_mode == I915_TILING_NONE)
return (1);
- if (INTEL_INFO(dev_priv)->gen < 4) {
+ if (INTEL_INFO(dev)->gen < 4) {
if (obj_priv->gtt_offset & (obj->size -1))
return (0);
- if (IS_I9XX(dev_priv)) {
+ if (IS_I9XX(dev)) {
if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
return (0);
} else {
@@ -3188,8 +3201,9 @@ i915_gem_object_fence_offset_ok(struct drm_obj *obj, int tiling_mode)
void
inteldrm_965_reset(struct inteldrm_softc *dev_priv, u_int8_t flags)
{
- pcireg_t reg;
- int i = 0;
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+ pcireg_t reg;
+ int i = 0;
/*
* There seems to be soemthing wrong with !full reset modes, so force
@@ -3198,7 +3212,7 @@ inteldrm_965_reset(struct inteldrm_softc *dev_priv, u_int8_t flags)
flags = GRDOM_FULL;
if (flags == GRDOM_FULL)
- i915_save_display(dev_priv);
+ i915_save_display(dev);
reg = pci_conf_read(dev_priv->pc, dev_priv->tag, I965_GDRST);
/*
@@ -3234,7 +3248,7 @@ inteldrm_965_reset(struct inteldrm_softc *dev_priv, u_int8_t flags)
panic("can't restart ring, we're fucked");
/* put the hardware status page back */
- if (I915_NEED_GFX_HWS(dev_priv)) {
+ if (I915_NEED_GFX_HWS(dev)) {
I915_WRITE(HWS_PGA, ((struct drm_i915_gem_object *)
dev_priv->hws_obj)->gtt_offset);
} else {
@@ -3253,7 +3267,7 @@ inteldrm_965_reset(struct inteldrm_softc *dev_priv, u_int8_t flags)
if (flags == GRDOM_FULL)
- i915_restore_display(dev_priv);
+ i915_restore_display(dev);
}
/*
@@ -3466,7 +3480,7 @@ i915_ringbuffer_info(int kdev)
printf("RingTail : %08x\n", tail);
printf("RingMask : %08x\n", dev_priv->ring.size - 1);
printf("RingSize : %08lx\n", dev_priv->ring.size);
- printf("Acthd : %08x\n", I915_READ(INTEL_INFO(dev_priv)->gen >= 4 ?
+ printf("Acthd : %08x\n", I915_READ(INTEL_INFO(dev)->gen >= 4 ?
ACTHD_I965 : ACTHD));
}
diff --git a/sys/dev/pci/drm/i915_drv.h b/sys/dev/pci/drm/i915_drv.h
index c38846a78cd..0592a56b82c 100644
--- a/sys/dev/pci/drm/i915_drv.h
+++ b/sys/dev/pci/drm/i915_drv.h
@@ -233,7 +233,6 @@ struct inteldrm_softc {
struct gmbus_port gp;
u_long flags;
- u_int16_t pci_device;
pci_chipset_tag_t pc;
pcitag_t tag;
@@ -974,10 +973,10 @@ int i915_gem_evict_inactive(struct inteldrm_softc *, int);
/* i915_suspend.c */
-extern void i915_save_display(struct inteldrm_softc *);
-extern void i915_restore_display(struct inteldrm_softc *);
-extern int i915_save_state(struct inteldrm_softc *);
-extern int i915_restore_state(struct inteldrm_softc *);
+extern void i915_save_display(struct drm_device *);
+extern void i915_restore_display(struct drm_device *);
+extern int i915_save_state(struct drm_device *);
+extern int i915_restore_state(struct drm_device *);
/* intel_i2c.c */
extern int intel_setup_gmbus(struct inteldrm_softc *);
@@ -1123,41 +1122,41 @@ read64(struct inteldrm_softc *dev_priv, bus_size_t off)
#define READ_HWSP(dev_priv, reg) inteldrm_read_hws(dev_priv, reg)
#define I915_GEM_HWS_INDEX 0x20
-#define INTEL_INFO(dev) ((dev)->info)
+#define INTEL_INFO(dev) (((struct inteldrm_softc *) (dev)->dev_private)->info)
/* Chipset type macros */
-#define IS_I830(dev_priv) ((dev_priv)->pci_device == 0x3577)
-#define IS_845G(dev_priv) ((dev_priv)->pci_device == 0x2562)
-#define IS_I85X(dev_priv) (INTEL_INFO(dev_priv)->is_i85x)
-#define IS_I865G(dev_priv) ((dev_priv)->pci_device == 0x2572)
-#define IS_I915G(dev_priv) (INTEL_INFO(dev_priv)->is_i915g)
-#define IS_I915GM(dev_priv) ((dev_priv)->pci_device == 0x2592)
-#define IS_I945G(dev_priv) ((dev_priv)->pci_device == 0x2772)
-#define IS_I945GM(dev_priv) (INTEL_INFO(dev_priv)->is_i945gm)
-#define IS_BROADWATER(dev_priv) (INTEL_INFO(dev_priv)->is_broadwater)
-#define IS_CRESTLINE(dev_priv) (INTEL_INFO(dev_priv)->is_crestline)
-#define IS_GM45(dev_priv) ((dev_priv)->pci_device == 0x2A42)
-#define IS_G4X(dev_priv) (INTEL_INFO(dev_priv)->is_g4x)
-#define IS_PINEVIEW_G(dev_priv) ((dev_priv)->pci_device == 0xa001)
-#define IS_PINEVIEW_M(dev_priv) ((dev_priv)->pci_device == 0xa011)
-#define IS_PINEVIEW(dev_priv) (INTEL_INFO(dev_priv)->is_pineview)
-#define IS_G33(dev_priv) (INTEL_INFO(dev_priv)->is_g33)
-#define IS_IRONLAKE_D(dev_priv) ((dev_priv)->pci_device == 0x0042)
-#define IS_IRONLAKE_M(dev_priv) ((dev_priv)->pci_device == 0x0046)
-#define IS_IVYBRIDGE(dev_priv) (INTEL_INFO(dev_priv)->is_ivybridge)
-#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
-
-#define IS_I9XX(dev_priv) (INTEL_INFO(dev_priv)->gen >= 3)
-#define IS_IRONLAKE(dev_priv) (INTEL_INFO(dev_priv)->gen == 5)
-
-#define IS_SANDYBRIDGE(dev_priv) (INTEL_INFO(dev_priv)->gen == 6)
-#define IS_SANDYBRIDGE_D(dev_priv) (IS_SANDYBRIDGE(dev_priv) && \
- (INTEL_INFO(dev_priv)->is_mobile == 0))
-#define IS_SANDYBRIDGE_M(dev_priv) (IS_SANDYBRIDGE(dev_priv) && \
- (INTEL_INFO(dev_priv)->is_mobile == 1))
-#define IS_VALLEYVIEW(dev_priv) (INTEL_INFO(dev_priv)->is_valleyview)
-#define IS_HASWELL(dev_priv) (INTEL_INFO(dev_priv)->is_haswell)
+#define IS_I830(dev) ((dev)->pci_device == 0x3577)
+#define IS_845G(dev) ((dev)->pci_device == 0x2562)
+#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
+#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
+#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
+#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
+#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
+#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
+#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
+#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
+#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
+#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
+#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
+#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
+#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
+#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
+#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
+#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
+#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
+#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
+
+#define IS_I9XX(dev) (INTEL_INFO(dev)->gen >= 3)
+#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->gen == 5)
+
+#define IS_SANDYBRIDGE(dev) (INTEL_INFO(dev)->gen == 6)
+#define IS_SANDYBRIDGE_D(dev) (IS_SANDYBRIDGE(dev) && \
+ (INTEL_INFO(dev)->is_mobile == 0))
+#define IS_SANDYBRIDGE_M(dev) (IS_SANDYBRIDGE(dev) && \
+ (INTEL_INFO(dev)->is_mobile == 1))
+#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
+#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
/*
* The genX designation typically refers to the render engine, so render
@@ -1165,50 +1164,50 @@ read64(struct inteldrm_softc *dev_priv, bus_size_t off)
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN2(dev_priv) (INTEL_INFO(dev_priv)->gen == 2)
-#define IS_GEN3(dev_priv) (INTEL_INFO(dev_priv)->gen == 3)
-#define IS_GEN4(dev_priv) (INTEL_INFO(dev_priv)->gen == 4)
-#define IS_GEN5(dev_priv) (INTEL_INFO(dev_priv)->gen == 5)
-#define IS_GEN6(dev_priv) (INTEL_INFO(dev_priv)->gen == 6)
-#define IS_GEN7(dev_priv) (INTEL_INFO(dev_priv)->gen == 7)
+#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
+#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
+#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
+#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
+#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
+#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
-#define HAS_BSD(dev_priv) (INTEL_INFO(dev_priv)->has_bsd_ring)
-#define HAS_BLT(dev_priv) (INTEL_INFO(dev_priv)->has_blt_ring)
-#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
-#define I915_NEED_GFX_HWS(dev_priv) (INTEL_INFO(dev_priv)->need_gfx_hws)
+#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
+#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
+#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
+#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
-#define HAS_HW_CONTEXTS(dev_priv) (INTEL_INFO(dev_priv)->gen >= 6)
-#define HAS_ALIASING_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->gen >= 6)
+#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
+#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
-#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->has_overlay)
-#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
- (INTEL_INFO(dev_priv)->overlay_needs_physical)
+#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
+#define OVERLAY_NEEDS_PHYSICAL(dev) \
+ (INTEL_INFO(dev)->overlay_needs_physical)
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
-#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
+#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
/*
* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changes the alignment requirements and fence programming.
*/
-#define HAS_128_BYTE_Y_TILING(dev_priv) (IS_I9XX(dev_priv) && \
- !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
+#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && \
+ !(IS_I915G(dev) || IS_I915GM(dev)))
-#define HAS_RESET(dev_priv) (INTEL_INFO(dev_priv)->gen >= 4 && \
- (!IS_GEN6(dev_priv)) && (!IS_GEN7(dev_priv)))
+#define HAS_RESET(dev) (INTEL_INFO(dev)->gen >= 4 && \
+ (!IS_GEN6(dev)) && (!IS_GEN7(dev)))
#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
-#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->supports_tv)
-#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->has_hotplug)
+#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
+#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
-#define HAS_PIPE_CONTROL(dev_priv) (INTEL_INFO(dev_priv)->gen >= 5)
+#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev) || \
IS_GEN7(dev))
diff --git a/sys/dev/pci/drm/i915_gem.c b/sys/dev/pci/drm/i915_gem.c
index c8bfa2bbfaf..bc4a9f9869b 100644
--- a/sys/dev/pci/drm/i915_gem.c
+++ b/sys/dev/pci/drm/i915_gem.c
@@ -625,7 +625,7 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
return (0);
/* XXX until we have support for the rings on sandybridge */
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
return (0);
if (dev_priv->mm.wedged) {
@@ -1249,7 +1249,6 @@ bus_size_t
i915_gem_get_gtt_alignment(struct drm_obj *obj)
{
struct drm_device *dev = obj->dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bus_size_t start, i;
@@ -1257,7 +1256,7 @@ i915_gem_get_gtt_alignment(struct drm_obj *obj)
* Minimum alignment is 4k (GTT page size), but fence registers may
* modify this
*/
- if (INTEL_INFO(dev_priv)->gen >= 4 ||
+ if (INTEL_INFO(dev)->gen >= 4 ||
obj_priv->tiling_mode == I915_TILING_NONE)
return (4096);
@@ -1265,7 +1264,7 @@ i915_gem_get_gtt_alignment(struct drm_obj *obj)
* Older chips need to be aligned to the size of the smallest fence
* register that can contain the object.
*/
- if (IS_I9XX(dev_priv))
+ if (IS_I9XX(dev))
start = 1024 * 1024;
else
start = 512 * 1024;
@@ -1626,6 +1625,7 @@ i915_wait_request(struct inteldrm_softc *dev_priv, uint32_t seqno,
uint32_t
i915_add_request(struct inteldrm_softc *dev_priv)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
struct drm_i915_gem_request *request;
uint32_t seqno;
int was_empty;
@@ -1646,7 +1646,7 @@ i915_add_request(struct inteldrm_softc *dev_priv)
if (dev_priv->mm.next_gem_seqno == 0)
dev_priv->mm.next_gem_seqno++;
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
BEGIN_LP_RING(10);
else
BEGIN_LP_RING(4);
@@ -1774,7 +1774,7 @@ i915_write_fence_reg(struct drm_i915_fence_reg *reg)
}
if (obj_priv->tiling_mode == I915_TILING_Y &&
- HAS_128_BYTE_Y_TILING(dev_priv))
+ HAS_128_BYTE_Y_TILING(dev))
tile_width = 128;
else
tile_width = 512;
@@ -1785,7 +1785,7 @@ i915_write_fence_reg(struct drm_i915_fence_reg *reg)
/* XXX print more */
if ((obj_priv->tiling_mode == I915_TILING_Y &&
- HAS_128_BYTE_Y_TILING(dev_priv) &&
+ HAS_128_BYTE_Y_TILING(dev) &&
pitch_val > I830_FENCE_MAX_PITCH_VAL) ||
pitch_val > I915_FENCE_MAX_PITCH_VAL)
printf("%s: invalid pitch provided", __func__);
@@ -1878,7 +1878,7 @@ i915_gem_object_put_fence_reg(struct drm_obj *obj, int interruptible)
}
mtx_enter(&dev_priv->fence_lock);
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
} else {
u_int32_t fence_reg;
diff --git a/sys/dev/pci/drm/i915_gem_tiling.c b/sys/dev/pci/drm/i915_gem_tiling.c
index 8aaf879c63a..347e895937c 100644
--- a/sys/dev/pci/drm/i915_gem_tiling.c
+++ b/sys/dev/pci/drm/i915_gem_tiling.c
@@ -67,21 +67,21 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
if (tiling_mode == I915_TILING_NONE)
return (1);
- if (!IS_I9XX(dev_priv) || (tiling_mode == I915_TILING_Y &&
- HAS_128_BYTE_Y_TILING(dev_priv)))
+ if (!IS_I9XX(dev) || (tiling_mode == I915_TILING_Y &&
+ HAS_128_BYTE_Y_TILING(dev)))
tile_width = 128;
else
tile_width = 512;
/* Check stride and size constraints */
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
/* fence reg has end address, so size is ok */
if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
return (0);
- } else if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
+ } else if (IS_GEN3(dev) || IS_GEN2(dev)) {
if (stride > 8192)
return (0);
- if (IS_GEN3(dev_priv)) {
+ if (IS_GEN3(dev)) {
if (size > I830_FENCE_MAX_SIZE_VAL << 20)
return (0);
} else if (size > I830_FENCE_MAX_SIZE_VAL << 19)
@@ -89,7 +89,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
}
/* 965+ just needs multiples of the tile width */
- if (INTEL_INFO(dev_priv)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
return ((stride & (tile_width - 1)) == 0);
/* Pre-965 needs power-of-two */
diff --git a/sys/dev/pci/drm/i915_irq.c b/sys/dev/pci/drm/i915_irq.c
index c4c169f638f..f2173ef1d6f 100644
--- a/sys/dev/pci/drm/i915_irq.c
+++ b/sys/dev/pci/drm/i915_irq.c
@@ -63,10 +63,12 @@ i915_disable_irq(struct inteldrm_softc *dev_priv, u_int32_t mask)
inline void
ironlake_enable_graphics_irq(struct inteldrm_softc *dev_priv, u_int32_t mask)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+
if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
/* XXX imr bullshit */
dev_priv->gt_irq_mask_reg &= ~mask;
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
+ if (IS_GEN6(dev) || IS_GEN7(dev)) {
I915_WRITE(0x20a8, dev_priv->gt_irq_mask_reg);
(void)I915_READ(0x20a8);
} else {
@@ -79,9 +81,11 @@ ironlake_enable_graphics_irq(struct inteldrm_softc *dev_priv, u_int32_t mask)
inline void
ironlake_disable_graphics_irq(struct inteldrm_softc *dev_priv, u_int32_t mask)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+
if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
dev_priv->gt_irq_mask_reg |= mask;
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
+ if (IS_GEN6(dev) || IS_GEN7(dev)) {
I915_WRITE(0x20a8, dev_priv->gt_irq_mask_reg);
(void)I915_READ(0x20a8);
} else {
@@ -169,8 +173,8 @@ i915_get_vblank_counter(struct drm_device *dev, int pipe)
low_frame = PIPEFRAMEPIXEL(pipe);
/* GM45 just had to be different... */
- if (IS_GM45(dev_priv) || IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
- IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
+ if (IS_GM45(dev) || IS_G4X(dev) || IS_IRONLAKE(dev) ||
+ IS_GEN6(dev) || IS_GEN7(dev)) {
return (I915_READ(PIPE_FRMCOUNT_GM45(pipe)));
}
@@ -194,8 +198,10 @@ i915_get_vblank_counter(struct drm_device *dev, int pipe)
void
i915_user_irq_get(struct inteldrm_softc *dev_priv)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+
if (++dev_priv->user_irq_refcount == 1) {
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
ironlake_enable_graphics_irq(dev_priv,
GT_USER_INTERRUPT);
else
@@ -206,8 +212,10 @@ i915_user_irq_get(struct inteldrm_softc *dev_priv)
void
i915_user_irq_put(struct inteldrm_softc *dev_priv)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+
if (--dev_priv->user_irq_refcount == 0) {
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
ironlake_disable_graphics_irq(dev_priv,
GT_USER_INTERRUPT);
else
@@ -224,15 +232,15 @@ i915_enable_vblank(struct drm_device *dev, int pipe)
return (EINVAL);
mtx_enter(&dev_priv->user_irq_lock);
- if (IS_GEN7(dev_priv))
+ if (IS_GEN7(dev))
ironlake_enable_display_irq(dev_priv,
DE_PIPEA_VBLANK_IVB << (5 * pipe));
- else if (HAS_PCH_SPLIT(dev_priv))
+ else if (HAS_PCH_SPLIT(dev))
ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
else
i915_enable_pipestat(dev_priv, pipe,
- (INTEL_INFO(dev_priv)->gen >= 4 ?
+ (INTEL_INFO(dev)->gen >= 4 ?
PIPE_START_VBLANK_INTERRUPT_ENABLE :
PIPE_VBLANK_INTERRUPT_ENABLE));
mtx_leave(&dev_priv->user_irq_lock);
@@ -246,10 +254,10 @@ i915_disable_vblank(struct drm_device *dev, int pipe)
struct inteldrm_softc *dev_priv = dev->dev_private;
mtx_enter(&dev_priv->user_irq_lock);
- if (IS_GEN7(dev_priv))
+ if (IS_GEN7(dev))
ironlake_disable_display_irq(dev_priv,
DE_PIPEA_VBLANK_IVB << (pipe * 5));
- else if (HAS_PCH_SPLIT(dev_priv))
+ else if (HAS_PCH_SPLIT(dev))
ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
else
@@ -267,13 +275,13 @@ i915_driver_irq_install(struct drm_device *dev)
struct inteldrm_softc *dev_priv = dev->dev_private;
dev->vblank->vb_max = 0xffffff; /* only 24 bits of frame count */
- if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv) ||
- IS_GEN7(dev_priv))
+ if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev) ||
+ IS_GEN7(dev))
dev->vblank->vb_max = 0xffffffff;
I915_WRITE(HWSTAM, 0xeffe);
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
return (ironlake_irq_install(dev_priv));
I915_WRITE(_PIPEASTAT, 0);
@@ -287,7 +295,7 @@ i915_driver_irq_install(struct drm_device *dev)
* Enable some error detection, note the instruction error mask
* bit is reserved, so we leave it masked.
*/
- I915_WRITE(EMR, IS_G4X(dev_priv) ?
+ I915_WRITE(EMR, IS_G4X(dev) ?
~(GM45_ERROR_PAGE_TABLE | GM45_ERROR_MEM_PRIV |
GM45_ERROR_CP_PRIV | I915_ERROR_MEMORY_REFRESH) :
~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -358,7 +366,7 @@ i915_driver_irq_uninstall(struct drm_device *dev)
I915_WRITE(HWSTAM, 0xffffffff);
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(DEIMR, 0xffffffff);
I915_WRITE(DEIER, 0x0);
I915_WRITE(DEIIR, I915_READ(DEIIR));
diff --git a/sys/dev/pci/drm/i915_suspend.c b/sys/dev/pci/drm/i915_suspend.c
index a260310dfbb..20f8c176aa7 100644
--- a/sys/dev/pci/drm/i915_suspend.c
+++ b/sys/dev/pci/drm/i915_suspend.c
@@ -29,26 +29,26 @@
#include "i915_drm.h"
#include "i915_drv.h"
-int i915_pipe_enabled(struct inteldrm_softc *, enum pipe);
-void i915_save_palette(struct inteldrm_softc *, enum pipe);
-void i915_restore_palette(struct inteldrm_softc *, enum pipe);
-u_int8_t i915_read_indexed(struct inteldrm_softc *, u_int16_t,
+int i915_pipe_enabled(struct drm_device *, enum pipe);
+void i915_save_palette(struct drm_device *, enum pipe);
+void i915_restore_palette(struct drm_device *, enum pipe);
+u_int8_t i915_read_indexed(struct drm_device *, u_int16_t,
u_int16_t, u_int8_t);
-void i915_write_indexed(struct inteldrm_softc *, u_int16_t,
+void i915_write_indexed(struct drm_device *, u_int16_t,
u_int16_t, u_int8_t, u_int8_t);
-void i915_write_ar(struct inteldrm_softc *, u_int16_t, u_int8_t,
+void i915_write_ar(struct drm_device *, u_int16_t, u_int8_t,
u_int8_t, u_int16_t);
-u_int8_t i915_read_ar(struct inteldrm_softc *, u_int16_t,
+u_int8_t i915_read_ar(struct drm_device *, u_int16_t,
u_int8_t, u_int16_t);
-void i915_save_vga(struct inteldrm_softc *);
-void i915_restore_vga(struct inteldrm_softc *);
-void i915_save_modeset_reg(struct inteldrm_softc *);
-void i915_restore_modeset_reg(struct inteldrm_softc *);
+void i915_save_vga(struct drm_device *);
+void i915_restore_vga(struct drm_device *);
+void i915_save_modeset_reg(struct drm_device *);
+void i915_restore_modeset_reg(struct drm_device *);
int
-i915_pipe_enabled(struct inteldrm_softc *dev, enum pipe pipe)
+i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
u32 dpll_reg;
/* On IVB, 3rd pipe shares PLL with another one */
@@ -64,9 +64,9 @@ i915_pipe_enabled(struct inteldrm_softc *dev, enum pipe pipe)
}
void
-i915_save_palette(struct inteldrm_softc *dev, enum pipe pipe)
+i915_save_palette(struct drm_device *dev, enum pipe pipe)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
u32 *array;
int i;
@@ -87,9 +87,9 @@ i915_save_palette(struct inteldrm_softc *dev, enum pipe pipe)
}
void
-i915_restore_palette(struct inteldrm_softc *dev, enum pipe pipe)
+i915_restore_palette(struct drm_device *dev, enum pipe pipe)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
u32 *array;
int i;
@@ -110,43 +110,51 @@ i915_restore_palette(struct inteldrm_softc *dev, enum pipe pipe)
}
u_int8_t
-i915_read_indexed(struct inteldrm_softc *dev_priv, u_int16_t index_port,
+i915_read_indexed(struct drm_device *dev, u_int16_t index_port,
u_int16_t data_port, u_int8_t reg)
{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
I915_WRITE8(index_port, reg);
return I915_READ8(data_port);
}
u_int8_t
-i915_read_ar(struct inteldrm_softc *dev_priv, u_int16_t st01,
+i915_read_ar(struct drm_device *dev, u_int16_t st01,
u_int8_t reg, u_int16_t palette_enable)
{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
I915_READ8(st01);
I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
return I915_READ8(VGA_AR_DATA_READ);
}
void
-i915_write_ar(struct inteldrm_softc *dev_priv, u_int16_t st01, u_int8_t reg,
+i915_write_ar(struct drm_device *dev, u_int16_t st01, u_int8_t reg,
u_int8_t val, u_int16_t palette_enable)
{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
I915_READ8(st01);
I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
I915_WRITE8(VGA_AR_DATA_WRITE, val);
}
void
-i915_write_indexed(struct inteldrm_softc *dev_priv, u_int16_t index_port,
+i915_write_indexed(struct drm_device *dev, u_int16_t index_port,
u_int16_t data_port, u_int8_t reg, u_int8_t val)
{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
I915_WRITE8(index_port, reg);
I915_WRITE8(data_port, val);
}
void
-i915_save_vga(struct inteldrm_softc *dev)
+i915_save_vga(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
int i;
u16 cr_index, cr_data, st01;
@@ -203,9 +211,9 @@ i915_save_vga(struct inteldrm_softc *dev)
}
void
-i915_restore_vga(struct inteldrm_softc *dev)
+i915_restore_vga(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
int i;
u16 cr_index, cr_data, st01;
@@ -257,9 +265,9 @@ i915_restore_vga(struct inteldrm_softc *dev)
}
void
-i915_save_modeset_reg(struct inteldrm_softc *dev)
+i915_save_modeset_reg(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
int i;
/* Cursor state */
@@ -417,15 +425,15 @@ i915_save_modeset_reg(struct inteldrm_softc *dev)
}
void
-i915_restore_modeset_reg(struct inteldrm_softc *dev)
+i915_restore_modeset_reg(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
int dpll_a_reg, fpa0_reg, fpa1_reg;
int dpll_b_reg, fpb0_reg, fpb1_reg;
int i;
/* XXX until we have FDI link training */
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
return;
/* Fences */
@@ -625,9 +633,9 @@ i915_restore_modeset_reg(struct inteldrm_softc *dev)
}
void
-i915_save_display(struct inteldrm_softc *dev)
+i915_save_display(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
/* Display arbitration control */
dev_priv->saveDSPARB = I915_READ(DSPARB);
@@ -704,9 +712,9 @@ i915_save_display(struct inteldrm_softc *dev)
}
void
-i915_restore_display(struct inteldrm_softc *dev)
+i915_restore_display(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
/* Display arbitration */
I915_WRITE(DSPARB, dev_priv->saveDSPARB);
@@ -784,9 +792,9 @@ i915_restore_display(struct inteldrm_softc *dev)
}
int
-i915_save_state(struct inteldrm_softc *dev)
+i915_save_state(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
int i;
dev_priv->saveLBB = pci_conf_read(dev_priv->pc, dev_priv->tag, LBB);
@@ -815,28 +823,28 @@ i915_save_state(struct inteldrm_softc *dev)
/* XXX gen6_disable_rps(dev) */
/* Clock gating state */
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
dev_priv->saveDSPCLK_GATE_D = I915_READ(ILK_DSPCLK_GATE_D);
dev_priv->saveDSPCLK_GATE = I915_READ(ILK_DSPCLK_GATE_D);
- } else if (IS_G4X(dev_priv)) {
+ } else if (IS_G4X(dev)) {
dev_priv->saveRENCLK_GATE_D1 = I915_READ(RENCLK_GATE_D1);
dev_priv->saveRENCLK_GATE_D2 = I915_READ(RENCLK_GATE_D2);
dev_priv->saveRAMCLK_GATE_D = I915_READ(RAMCLK_GATE_D);
dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
- } else if (IS_CRESTLINE(dev_priv)) {
+ } else if (IS_CRESTLINE(dev)) {
dev_priv->saveRENCLK_GATE_D1 = I915_READ(RENCLK_GATE_D1);
dev_priv->saveRENCLK_GATE_D2 = I915_READ(RENCLK_GATE_D2);
dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
dev_priv->saveRAMCLK_GATE_D = I915_READ(RAMCLK_GATE_D);
dev_priv->saveDEUC = I915_READ16(DEUC);
- } else if (INTEL_INFO(dev_priv)->gen >= 4) {
+ } else if (INTEL_INFO(dev)->gen >= 4) {
dev_priv->saveRENCLK_GATE_D1 = I915_READ(RENCLK_GATE_D1);
dev_priv->saveRENCLK_GATE_D2 = I915_READ(RENCLK_GATE_D2);
- } else if (IS_I9XX(dev_priv)) {
+ } else if (IS_I9XX(dev)) {
dev_priv->saveD_STATE = I915_READ(D_STATE);
- } else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) {
+ } else if (IS_I85X(dev) || IS_I865G(dev)) {
dev_priv->saveRENCLK_GATE_D1 = I915_READ(RENCLK_GATE_D1);
- } else if (IS_I830(dev_priv)) {
+ } else if (IS_I830(dev)) {
dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
}
@@ -858,9 +866,9 @@ i915_save_state(struct inteldrm_softc *dev)
}
int
-i915_restore_state(struct inteldrm_softc *dev)
+i915_restore_state(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
int i;
pci_conf_write(dev_priv->pc, dev_priv->tag, LBB, dev_priv->saveLBB);
@@ -885,28 +893,28 @@ i915_restore_state(struct inteldrm_softc *dev)
}
/* Clock gating state */
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(ILK_DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
I915_WRITE(ILK_DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE);
- } if (IS_G4X(dev_priv)) {
+ } if (IS_G4X(dev)) {
I915_WRITE(RENCLK_GATE_D1, dev_priv->saveRENCLK_GATE_D1);
I915_WRITE(RENCLK_GATE_D2, dev_priv->saveRENCLK_GATE_D2);
I915_WRITE(RAMCLK_GATE_D, dev_priv->saveRAMCLK_GATE_D);
I915_WRITE(DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
- } else if (IS_CRESTLINE(dev_priv)) {
+ } else if (IS_CRESTLINE(dev)) {
I915_WRITE(RENCLK_GATE_D1, dev_priv->saveRENCLK_GATE_D1);
I915_WRITE(RENCLK_GATE_D2, dev_priv->saveRENCLK_GATE_D2);
I915_WRITE(DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
I915_WRITE(RAMCLK_GATE_D, dev_priv->saveRAMCLK_GATE_D);
I915_WRITE16(DEUC, dev_priv->saveDEUC);
- } else if (INTEL_INFO(dev_priv)->gen >= 4) {
+ } else if (INTEL_INFO(dev)->gen >= 4) {
I915_WRITE(RENCLK_GATE_D1, dev_priv->saveRENCLK_GATE_D1);
I915_WRITE(RENCLK_GATE_D2, dev_priv->saveRENCLK_GATE_D2);
- } else if (IS_I9XX(dev_priv)) {
+ } else if (IS_I9XX(dev)) {
I915_WRITE(D_STATE, dev_priv->saveD_STATE);
- } else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) {
+ } else if (IS_I85X(dev) || IS_I865G(dev)) {
I915_WRITE(RENCLK_GATE_D1, dev_priv->saveRENCLK_GATE_D1);
- } else if (IS_I830(dev_priv)) {
+ } else if (IS_I830(dev)) {
I915_WRITE(DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
}
diff --git a/sys/dev/pci/drm/intel_bios.c b/sys/dev/pci/drm/intel_bios.c
index 46b60d39697..4b4bb1f127d 100644
--- a/sys/dev/pci/drm/intel_bios.c
+++ b/sys/dev/pci/drm/intel_bios.c
@@ -48,7 +48,7 @@ const struct lvds_dvo_timing *
const struct bdb_lvds_lfp_data_ptrs *, int);
void parse_lfp_panel_data(struct inteldrm_softc *, struct bdb_header *);
void parse_sdvo_panel_data(struct inteldrm_softc *, struct bdb_header *);
-int intel_bios_ssc_frequency(struct inteldrm_softc *, bool);
+int intel_bios_ssc_frequency(struct drm_device *, bool);
void parse_general_features(struct inteldrm_softc *, struct bdb_header *);
void parse_general_definitions(struct inteldrm_softc *,
struct bdb_header *);
@@ -306,9 +306,9 @@ parse_sdvo_panel_data(struct inteldrm_softc *dev_priv, struct bdb_header *bdb)
}
int
-intel_bios_ssc_frequency(struct inteldrm_softc *dev_priv, bool alternate)
+intel_bios_ssc_frequency(struct drm_device *dev, bool alternate)
{
- switch (INTEL_INFO(dev_priv)->gen) {
+ switch (INTEL_INFO(dev)->gen) {
case 2:
return alternate ? 66 : 48;
case 3:
@@ -322,6 +322,7 @@ intel_bios_ssc_frequency(struct inteldrm_softc *dev_priv, bool alternate)
void
parse_general_features(struct inteldrm_softc *dev_priv, struct bdb_header *bdb)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
struct bdb_general_features *general;
general = find_section(bdb, BDB_GENERAL_FEATURES);
@@ -330,7 +331,7 @@ parse_general_features(struct inteldrm_softc *dev_priv, struct bdb_header *bdb)
dev_priv->int_crt_support = general->int_crt_support;
dev_priv->lvds_use_ssc = general->enable_ssc;
dev_priv->lvds_ssc_freq =
- intel_bios_ssc_frequency(dev_priv, general->ssc_freq);
+ intel_bios_ssc_frequency(dev, general->ssc_freq);
dev_priv->display_clock_mode = general->display_clock_mode;
DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d\n",
dev_priv->int_tv_support,
@@ -455,13 +456,14 @@ parse_sdvo_device_mapping(struct inteldrm_softc *dev_priv,
void
parse_driver_features(struct inteldrm_softc *dev_priv, struct bdb_header *bdb)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
struct bdb_driver_features *driver;
driver = find_section(bdb, BDB_DRIVER_FEATURES);
if (!driver)
return;
- if (SUPPORTS_EDP(dev_priv) &&
+ if (SUPPORTS_EDP(dev) &&
driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
dev_priv->edp.support = 1;
@@ -472,13 +474,14 @@ parse_driver_features(struct inteldrm_softc *dev_priv, struct bdb_header *bdb)
void
parse_edp(struct inteldrm_softc *dev_priv, struct bdb_header *bdb)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
struct bdb_edp *edp;
struct edp_power_seq *edp_pps;
struct edp_link_params *edp_link_params;
edp = find_section(bdb, BDB_EDP);
if (!edp) {
- if (SUPPORTS_EDP(dev_priv) && dev_priv->edp.support) {
+ if (SUPPORTS_EDP(dev) && dev_priv->edp.support) {
DRM_DEBUG_KMS("No eDP BDB found but eDP panel "
"supported, assume %dbpp panel color "
"depth.\n",
@@ -613,6 +616,8 @@ parse_device_mapping(struct inteldrm_softc *dev_priv, struct bdb_header *bdb)
void
init_vbt_defaults(struct inteldrm_softc *dev_priv)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+
dev_priv->crt_ddc_pin = GMBUS_PORT_VGADDC;
/* LFP panel data */
@@ -628,7 +633,7 @@ init_vbt_defaults(struct inteldrm_softc *dev_priv)
/* Default to using SSC */
dev_priv->lvds_use_ssc = 1;
- dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv, 1);
+ dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq);
/* eDP data */
diff --git a/sys/dev/pci/drm/intel_crt.c b/sys/dev/pci/drm/intel_crt.c
index 81578362dc4..e0c76913998 100644
--- a/sys/dev/pci/drm/intel_crt.c
+++ b/sys/dev/pci/drm/intel_crt.c
@@ -80,7 +80,7 @@ intel_crt_dpms(struct drm_encoder *encoder, int mode)
struct inteldrm_softc *dev_priv = dev->dev_private;
u32 temp, reg;
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
reg = PCH_ADPA;
else
reg = ADPA;
@@ -112,7 +112,6 @@ intel_crt_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
struct drm_device *dev = connector->dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
int max_clock = 0;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -121,7 +120,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
if (mode->clock < 25000)
return MODE_CLOCK_LOW;
- if (IS_GEN2(dev_priv))
+ if (IS_GEN2(dev))
max_clock = 350000;
else
max_clock = 400000;
@@ -153,7 +152,7 @@ intel_crt_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
dpll_md_reg = DPLL_MD(intel_crtc->pipe);
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
adpa_reg = PCH_ADPA;
else
adpa_reg = ADPA;
@@ -162,7 +161,7 @@ intel_crt_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
* Disable separate mode multiplier used when cloning SDVO to CRT
* XXX this needs to be adjusted when we really are cloning
*/
- if (INTEL_INFO(dev_priv)->gen >= 4 && !HAS_PCH_SPLIT(dev_priv)) {
+ if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
dpll_md = I915_READ(dpll_md_reg);
I915_WRITE(dpll_md_reg,
dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
@@ -182,7 +181,7 @@ intel_crt_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
else
adpa |= ADPA_PIPE_B_SELECT;
- if (!HAS_PCH_SPLIT(dev_priv))
+ if (!HAS_PCH_SPLIT(dev))
I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
I915_WRITE(adpa_reg, adpa);
@@ -200,7 +199,7 @@ intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
/* The first time through, trigger an explicit detection cycle */
if (crt->force_hotplug_required) {
- bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
+ bool turn_off_dac = HAS_PCH_SPLIT(dev);
u32 save_adpa;
crt->force_hotplug_required = 0;
@@ -257,7 +256,7 @@ intel_crt_detect_hotplug(struct drm_connector *connector)
bool ret = false;
int i, tries = 0, retries;
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
return intel_ironlake_crt_detect_hotplug(connector);
/*
@@ -265,7 +264,7 @@ intel_crt_detect_hotplug(struct drm_connector *connector)
* to get a reliable result.
*/
- if (IS_G4X(dev_priv) && !IS_GM45(dev_priv))
+ if (IS_G4X(dev) && !IS_GM45(dev))
tries = 2;
else
tries = 1;
@@ -384,7 +383,7 @@ intel_crt_load_detect(struct intel_crt *crt)
/* Set the border color to purple. */
I915_WRITE(bclrpat_reg, 0x500050);
- if (!IS_GEN2(dev_priv)) {
+ if (!IS_GEN2(dev)) {
uint32_t pipeconf = I915_READ(pipeconf_reg);
I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
POSTING_READ(pipeconf_reg);
@@ -465,12 +464,11 @@ enum drm_connector_status
intel_crt_detect(struct drm_connector *connector, bool force)
{
struct drm_device *dev = connector->dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
struct intel_crt *crt = intel_attached_crt(connector);
enum drm_connector_status status;
struct intel_load_detect_pipe tmp;
- if (I915_HAS_HOTPLUG(dev_priv)) {
+ if (I915_HAS_HOTPLUG(dev)) {
if (intel_crt_detect_hotplug(connector)) {
DRM_DEBUG_KMS("CRT detected via hotplug\n");
return connector_status_connected;
@@ -521,7 +519,7 @@ intel_crt_get_modes(struct drm_connector *connector)
intel_gmbus_set_port(dev_priv, dev_priv->crt_ddc_pin);
ret = intel_ddc_get_modes(connector, &dev_priv->ddc);
- if (ret || !IS_G4X(dev_priv))
+ if (ret || !IS_G4X(dev))
return ret;
/* Try to probe digital port for output in DVI-I -> VGA mode. */
@@ -540,10 +538,9 @@ void
intel_crt_reset(struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
struct intel_crt *crt = intel_attached_crt(connector);
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
crt->force_hotplug_required = 1;
}
@@ -627,7 +624,7 @@ intel_crt_init(struct drm_device *dev)
1 << INTEL_ANALOG_CLONE_BIT |
1 << INTEL_SDVO_LVDS_CLONE_BIT);
crt->base.crtc_mask = (1 << 0) | (1 << 1);
- if (IS_GEN2(dev_priv))
+ if (IS_GEN2(dev))
connector->interlace_allowed = 0;
else
connector->interlace_allowed = 1;
@@ -640,7 +637,7 @@ intel_crt_init(struct drm_device *dev)
drm_sysfs_connector_add(connector);
#endif
- if (I915_HAS_HOTPLUG(dev_priv))
+ if (I915_HAS_HOTPLUG(dev))
connector->polled = DRM_CONNECTOR_POLL_HPD;
else
connector->polled = DRM_CONNECTOR_POLL_CONNECT;
@@ -649,7 +646,7 @@ intel_crt_init(struct drm_device *dev)
* Configure the automatic hotplug detection stuff
*/
crt->force_hotplug_required = 0;
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
u32 adpa;
adpa = I915_READ(PCH_ADPA);
diff --git a/sys/dev/pci/drm/intel_display.c b/sys/dev/pci/drm/intel_display.c
index b46c583969b..5266f33e305 100644
--- a/sys/dev/pci/drm/intel_display.c
+++ b/sys/dev/pci/drm/intel_display.c
@@ -337,7 +337,7 @@ intel_fdi_link_freq(struct drm_device *dev)
{
struct inteldrm_softc *dev_priv = dev->dev_private;
- if (IS_GEN5(dev_priv)) {
+ if (IS_GEN5(dev)) {
return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
} else
return 27;
@@ -656,19 +656,18 @@ const intel_limit_t *
intel_limit(struct drm_crtc *crtc, int refclk)
{
struct drm_device *dev = crtc->dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
const intel_limit_t *limit;
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
limit = intel_ironlake_limit(crtc, refclk);
- else if (IS_G4X(dev_priv)) {
+ else if (IS_G4X(dev)) {
limit = intel_g4x_limit(crtc);
- } else if (IS_PINEVIEW(dev_priv)) {
+ } else if (IS_PINEVIEW(dev)) {
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
limit = &intel_limits_pineview_lvds;
else
limit = &intel_limits_pineview_sdvo;
- } else if (!IS_GEN2(dev_priv)) {
+ } else if (!IS_GEN2(dev)) {
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
limit = &intel_limits_i9xx_lvds;
else
@@ -695,9 +694,7 @@ pineview_clock(int refclk, intel_clock_t *clock)
void
intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
{
- struct inteldrm_softc *dev_priv = dev->dev_private;
-
- if (IS_PINEVIEW(dev_priv)) {
+ if (IS_PINEVIEW(dev)) {
pineview_clock(refclk, clock);
return;
}
@@ -737,8 +734,6 @@ bool
intel_PLL_is_valid(struct drm_device *dev, const intel_limit_t *limit,
const intel_clock_t *clock)
{
- struct inteldrm_softc *dev_priv = dev->dev_private;
-
if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
INTELPllInvalid("p1 out of range\n");
if (clock->p < limit->p.min || limit->p.max < clock->p)
@@ -747,7 +742,7 @@ intel_PLL_is_valid(struct drm_device *dev, const intel_limit_t *limit,
INTELPllInvalid("m2 out of range\n");
if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
INTELPllInvalid("m1 out of range\n");
- if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev_priv))
+ if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
INTELPllInvalid("m1 <= m2\n");
if (clock->m < limit->m.min || limit->m.max < clock->m)
INTELPllInvalid("m out of range\n");
@@ -801,7 +796,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
for (clock.m2 = limit->m2.min;
clock.m2 <= limit->m2.max; clock.m2++) {
/* m1 is always 0 in Pineview */
- if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev_priv))
+ if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
break;
for (clock.n = limit->n.min;
clock.n <= limit->n.max; clock.n++) {
@@ -847,7 +842,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
int lvds_reg;
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
lvds_reg = PCH_LVDS;
else
lvds_reg = LVDS;
@@ -1014,7 +1009,7 @@ void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
struct inteldrm_softc *dev_priv = dev->dev_private;
int retries;
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
int reg = PIPECONF(pipe);
/* Wait for the Pipe State to go off */
@@ -1136,7 +1131,7 @@ assert_fdi_tx_pll_enabled(struct inteldrm_softc *dev_priv, enum pipe pipe)
u32 val;
/* ILK FDI PLL is always enabled */
- if (INTEL_INFO(dev_priv)->gen == 5)
+ if (dev_priv->info->gen == 5)
return;
reg = FDI_TX_CTL(pipe);
@@ -1160,12 +1155,13 @@ assert_fdi_rx_pll_enabled(struct inteldrm_softc *dev_priv, enum pipe pipe)
void
assert_panel_unlocked(struct inteldrm_softc *dev_priv, enum pipe pipe)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
int pp_reg, lvds_reg;
u32 val;
enum pipe panel_pipe = PIPE_A;
bool locked = true;
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
pp_reg = PCH_PP_CONTROL;
lvds_reg = PCH_LVDS;
} else {
@@ -1226,12 +1222,13 @@ assert_plane(struct inteldrm_softc *dev_priv, enum plane plane, bool state)
void
assert_planes_disabled(struct inteldrm_softc *dev_priv, enum pipe pipe)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
int reg, i;
u32 val;
int cur_pipe;
/* Planes are fixed to pipes on ILK+ */
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
reg = DSPCNTR(pipe);
val = I915_READ(reg);
if ((val & DISPLAY_PLANE_ENABLE) != 0)
@@ -1407,14 +1404,15 @@ assert_pch_ports_disabled(struct inteldrm_softc *dev_priv, enum pipe pipe)
void
intel_enable_pll(struct inteldrm_softc *dev_priv, enum pipe pipe)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
int reg;
u32 val;
/* No really, not for ILK+ */
- KASSERT(INTEL_INFO(dev_priv)->gen < 5);
+ KASSERT(INTEL_INFO(dev)->gen < 5);
/* PLL is protected by panel, make sure we can write it */
- if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
+ if (IS_MOBILE(dev) && !IS_I830(dev))
assert_panel_unlocked(dev_priv, pipe);
reg = DPLL(pipe);
@@ -1473,6 +1471,7 @@ intel_disable_pll(struct inteldrm_softc *dev_priv, enum pipe pipe)
void
intel_enable_pch_pll(struct inteldrm_softc *dev_priv, enum pipe pipe)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
int reg;
u32 val;
@@ -1480,7 +1479,7 @@ intel_enable_pch_pll(struct inteldrm_softc *dev_priv, enum pipe pipe)
return;
/* PCH only available on ILK+ */
- KASSERT(INTEL_INFO(dev_priv)->gen >= 5);
+ KASSERT(INTEL_INFO(dev)->gen >= 5);
/* PCH refclock must be enabled first */
assert_pch_refclk_enabled(dev_priv);
@@ -1496,6 +1495,7 @@ intel_enable_pch_pll(struct inteldrm_softc *dev_priv, enum pipe pipe)
void
intel_disable_pch_pll(struct inteldrm_softc *dev_priv, enum pipe pipe)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
int reg;
u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
pll_sel = TRANSC_DPLL_ENABLE;
@@ -1504,7 +1504,7 @@ intel_disable_pch_pll(struct inteldrm_softc *dev_priv, enum pipe pipe)
return;
/* PCH only available on ILK+ */
- KASSERT(INTEL_INFO(dev_priv)->gen >= 5);
+ KASSERT(INTEL_INFO(dev)->gen >= 5);
/* Make sure transcoder isn't still depending on us */
assert_transcoder_disabled(dev_priv, pipe);
@@ -1529,13 +1529,14 @@ intel_disable_pch_pll(struct inteldrm_softc *dev_priv, enum pipe pipe)
void
intel_enable_transcoder(struct inteldrm_softc *dev_priv, enum pipe pipe)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
int reg;
u32 val, pipeconf_val;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
int retries;
/* PCH only available on ILK+ */
- KASSERT(INTEL_INFO(dev_priv)->gen >= 5);
+ KASSERT(INTEL_INFO(dev)->gen >= 5);
/* Make sure PCH DPLL is enabled */
assert_pch_pll_enabled(dev_priv, pipe);
@@ -1633,7 +1634,7 @@ intel_enable_pipe(struct inteldrm_softc *dev_priv, enum pipe pipe,
* a plane. On ILK+ the pipe PLLs are integrated, so we don't
* need the check.
*/
- if (!HAS_PCH_SPLIT(dev_priv))
+ if (!HAS_PCH_SPLIT(dev))
assert_pll_enabled(dev_priv, pipe);
else {
if (pch_port) {
@@ -1873,7 +1874,7 @@ i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
/* enable it... */
fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
- if (IS_I945GM(dev_priv))
+ if (IS_I945GM(dev))
fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
@@ -1994,7 +1995,7 @@ ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
/* enable it... */
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
- if (IS_GEN6(dev_priv)) {
+ if (IS_GEN6(dev)) {
I915_WRITE(SNB_DPFC_CTL_SA,
SNB_CPU_FENCE_ENABLE | obj->fence_reg);
I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
@@ -2195,7 +2196,7 @@ intel_update_fbc(struct drm_device *dev)
if (!i915_powersave)
return;
- if (!I915_HAS_FBC(dev_priv))
+ if (!I915_HAS_FBC(dev))
return;
/*
@@ -2233,7 +2234,7 @@ intel_update_fbc(struct drm_device *dev)
if (enable_fbc < 0) {
DRM_DEBUG_KMS("fbc set to per-chip default\n");
enable_fbc = 1;
- if (INTEL_INFO(dev_priv)->gen <= 6)
+ if (INTEL_INFO(dev)->gen <= 6)
enable_fbc = 0;
}
if (!enable_fbc) {
@@ -2264,7 +2265,7 @@ intel_update_fbc(struct drm_device *dev)
dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
goto out_disable;
}
- if ((IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) && intel_crtc->plane != 0) {
+ if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
DRM_DEBUG_KMS("plane not 0, disabling compression\n");
dev_priv->no_fbc_reason = FBC_BAD_PLANE;
goto out_disable;
@@ -2330,16 +2331,15 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
struct drm_i915_gem_object *obj,
struct intel_ring_buffer *pipelined)
{
- struct inteldrm_softc *dev_priv = dev->dev_private;
u32 alignment;
int ret;
alignment = 0; /* shut gcc */
switch (obj->tiling_mode) {
case I915_TILING_NONE:
- if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv))
+ if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
alignment = 128 * 1024;
- else if (INTEL_INFO(dev_priv)->gen >= 4)
+ else if (INTEL_INFO(dev)->gen >= 4)
alignment = 4 * 1024;
else
alignment = 64 * 1024;
@@ -2439,7 +2439,7 @@ i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, int x,
DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
return -EINVAL;
}
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
if (obj->tiling_mode != I915_TILING_NONE)
dspcntr |= DISPPLANE_TILED;
else
@@ -2454,7 +2454,7 @@ i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, int x,
DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
Start, Offset, x, y, fb->pitches[0]);
I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
I915_WRITE(DSPSURF(plane), Start);
I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
I915_WRITE(DSPADDR(plane), Offset);
@@ -2628,7 +2628,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
case 1:
break;
case 2:
- if (IS_IVYBRIDGE(dev_priv))
+ if (IS_IVYBRIDGE(dev))
break;
/* fall through otherwise */
default:
@@ -2746,7 +2746,7 @@ intel_fdi_normal_train(struct drm_crtc *crtc)
/* enable normal train */
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
- if (IS_IVYBRIDGE(dev_priv)) {
+ if (IS_IVYBRIDGE(dev)) {
temp &= ~FDI_LINK_TRAIN_NONE_IVB;
temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
} else {
@@ -2771,7 +2771,7 @@ intel_fdi_normal_train(struct drm_crtc *crtc)
DELAY(1000);
/* IVB wants error correction enabled */
- if (IS_IVYBRIDGE(dev_priv))
+ if (IS_IVYBRIDGE(dev))
I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
FDI_FE_ERRC_ENABLE);
}
@@ -2972,7 +2972,7 @@ gen6_fdi_link_train(struct drm_crtc *crtc)
temp = I915_READ(reg);
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_2;
- if (IS_GEN6(dev_priv)) {
+ if (IS_GEN6(dev)) {
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
/* SNB-B */
temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
@@ -3256,7 +3256,7 @@ intel_clear_scanline_wait(struct drm_device *dev)
struct intel_ring_buffer *ring;
u32 tmp;
- if (IS_GEN2(dev_priv))
+ if (IS_GEN2(dev))
/* Can't break the hang on i8xx */
return;
@@ -3886,9 +3886,8 @@ intel_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct drm_device *dev = crtc->dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
/* FDI link clock is fixed at 2.7G */
if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
return false;
@@ -4377,7 +4376,7 @@ pineview_update_wm(struct drm_device *dev)
u32 reg;
unsigned long wm;
- latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), dev_priv->is_ddr3,
+ latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
dev_priv->fsb_freq, dev_priv->mem_freq);
if (!latency) {
DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
@@ -4665,11 +4664,11 @@ i965_update_wm(struct drm_device *dev)
DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
"cursor %d\n", srwm, cursor_sr);
- if (IS_CRESTLINE(dev_priv))
+ if (IS_CRESTLINE(dev))
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
} else {
/* Turn off self refresh if both pipes are enabled */
- if (IS_CRESTLINE(dev_priv))
+ if (IS_CRESTLINE(dev))
I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
& ~FW_BLC_SELF_EN);
}
@@ -4697,9 +4696,9 @@ i9xx_update_wm(struct drm_device *dev)
int planea_wm, planeb_wm;
struct drm_crtc *crtc, *enabled = NULL;
- if (IS_I945GM(dev_priv))
+ if (IS_I945GM(dev))
wm_info = &i945_wm_info;
- else if (!IS_GEN2(dev_priv))
+ else if (!IS_GEN2(dev))
wm_info = &i915_wm_info;
else
wm_info = &i855_wm_info;
@@ -4737,13 +4736,13 @@ i9xx_update_wm(struct drm_device *dev)
cwm = 2;
/* Play safe and disable self-refresh before adjusting watermarks. */
- if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
+ if (IS_I945G(dev) || IS_I945GM(dev))
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
- else if (IS_I915GM(dev_priv))
+ else if (IS_I915GM(dev))
I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
/* Calc sr entries for one plane configs */
- if (HAS_FW_BLC(dev_priv) && enabled) {
+ if (HAS_FW_BLC(dev) && enabled) {
/* self-refresh has much higher latency */
static const int sr_latency_ns = 6000;
int clock = enabled->mode.clock;
@@ -4764,10 +4763,10 @@ i9xx_update_wm(struct drm_device *dev)
if (srwm < 0)
srwm = 1;
- if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
+ if (IS_I945G(dev) || IS_I945GM(dev))
I915_WRITE(FW_BLC_SELF,
FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
- else if (IS_I915GM(dev_priv))
+ else if (IS_I915GM(dev))
I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
}
@@ -4784,12 +4783,12 @@ i9xx_update_wm(struct drm_device *dev)
I915_WRITE(FW_BLC, fwater_lo);
I915_WRITE(FW_BLC2, fwater_hi);
- if (HAS_FW_BLC(dev_priv)) {
+ if (HAS_FW_BLC(dev)) {
if (enabled) {
- if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
+ if (IS_I945G(dev) || IS_I945GM(dev))
I915_WRITE(FW_BLC_SELF,
FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
- else if (IS_I915GM(dev_priv))
+ else if (IS_I915GM(dev))
I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
DRM_DEBUG_KMS("memory self refresh enabled\n");
} else
@@ -5048,7 +5047,7 @@ sandybridge_update_wm(struct drm_device *dev)
}
/* IVB has 3 pipes */
- if (IS_IVYBRIDGE(dev_priv) &&
+ if (IS_IVYBRIDGE(dev) &&
g4x_compute_wm0(dev, 2,
&sandybridge_display_wm_info, latency,
&sandybridge_cursor_wm_info, latency,
@@ -5256,7 +5255,7 @@ sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
I915_WRITE(WM1S_LP_ILK, sprite_wm);
/* Only IVB has two more LP watermarks for sprite */
- if (!IS_IVYBRIDGE(dev_priv))
+ if (!IS_IVYBRIDGE(dev))
return;
ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
@@ -5496,7 +5495,7 @@ i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
refclk = dev_priv->lvds_ssc_freq * 1000;
DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
refclk / 1000);
- } else if (!IS_GEN2(dev_priv)) {
+ } else if (!IS_GEN2(dev)) {
refclk = 96000;
} else {
refclk = 48000;
@@ -5538,7 +5537,7 @@ i9xx_update_pll_dividers(struct drm_crtc *crtc, intel_clock_t *clock,
int pipe = intel_crtc->pipe;
u32 fp, fp2 = 0;
- if (IS_PINEVIEW(dev_priv)) {
+ if (IS_PINEVIEW(dev)) {
fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
if (reduced_clock)
fp2 = (1 << reduced_clock->n) << 16 |
@@ -5657,7 +5656,7 @@ i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
dpll = DPLL_VGA_MODE_DIS;
- if (!IS_GEN2(dev_priv)) {
+ if (!IS_GEN2(dev)) {
if (is_lvds)
dpll |= DPLLB_MODE_LVDS;
else
@@ -5665,7 +5664,7 @@ i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
if (is_sdvo) {
int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
if (pixel_multiplier > 1) {
- if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv))
+ if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
}
dpll |= DPLL_DVO_HIGH_SPEED;
@@ -5674,11 +5673,11 @@ i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
dpll |= DPLL_DVO_HIGH_SPEED;
/* compute bitmask from p1 value */
- if (IS_PINEVIEW(dev_priv))
+ if (IS_PINEVIEW(dev))
dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
else {
dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
- if (IS_G4X(dev_priv) && has_reduced_clock)
+ if (IS_G4X(dev) && has_reduced_clock)
dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
}
switch (clock.p2) {
@@ -5695,7 +5694,7 @@ i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
break;
}
- if (INTEL_INFO(dev_priv)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
} else {
if (is_lvds) {
@@ -5732,7 +5731,7 @@ i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
else
dspcntr |= DISPPLANE_SEL_PIPE_B;
- if (pipe == 0 && INTEL_INFO(dev_priv)->gen < 4) {
+ if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
/* Enable pixel doubling when the dot clock is > 90% of the (display)
* core speed.
*
@@ -5793,7 +5792,7 @@ i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
* panels behave in the two modes.
*/
/* set the dithering flag on LVDS as needed */
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
if (dev_priv->lvds_dither)
temp |= LVDS_ENABLE_DITHER;
else
@@ -5828,7 +5827,7 @@ i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
POSTING_READ(DPLL(pipe));
DELAY(150);
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
temp = 0;
if (is_sdvo) {
temp = intel_mode_get_pixel_multiplier(adjusted_mode);
@@ -5847,7 +5846,7 @@ i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
I915_WRITE(DPLL(pipe), dpll);
}
- if (HAS_PIPE_CXSR(dev_priv)) {
+ if (HAS_PIPE_CXSR(dev)) {
if (intel_crtc->lowfreq_avail) {
DRM_DEBUG_KMS("enabling CxSR downclocking\n");
pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
@@ -5858,7 +5857,7 @@ i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
}
pipeconf &= ~PIPECONF_INTERLACE_MASK;
- if (!IS_GEN2(dev_priv) &&
+ if (!IS_GEN2(dev) &&
adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
/* the chip adds 2 halflines automatically */
@@ -5871,7 +5870,7 @@ i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
vsyncshift = 0;
}
- if (!IS_GEN3(dev_priv))
+ if (!IS_GEN3(dev))
I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
I915_WRITE(HTOTAL(pipe),
@@ -6448,13 +6447,13 @@ ironlake_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
if (is_lvds && has_reduced_clock && i915_powersave) {
I915_WRITE(PCH_FP1(pipe), fp2);
intel_crtc->lowfreq_avail = true;
- if (HAS_PIPE_CXSR(dev_priv)) {
+ if (HAS_PIPE_CXSR(dev)) {
DRM_DEBUG_KMS("enabling CxSR downclocking\n");
pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
}
} else {
I915_WRITE(PCH_FP1(pipe), fp);
- if (HAS_PIPE_CXSR(dev_priv)) {
+ if (HAS_PIPE_CXSR(dev)) {
DRM_DEBUG_KMS("disabling CxSR downclocking\n");
pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
}
@@ -6741,7 +6740,7 @@ intel_crtc_load_lut(struct drm_crtc *crtc)
return;
/* use legacy palette for Ironlake */
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
palreg = LGC_PALETTE(intel_crtc->pipe);
for (i = 0; i < 256; i++) {
@@ -6883,12 +6882,12 @@ intel_crtc_update_cursor(struct drm_crtc *crtc, bool on)
if (!visible && !intel_crtc->cursor_visible)
return;
- if (IS_IVYBRIDGE(dev_priv)) {
+ if (IS_IVYBRIDGE(dev)) {
I915_WRITE(CURPOS_IVB(pipe), pos);
ivb_update_cursor(crtc, base);
} else {
I915_WRITE(CURPOS(pipe), pos);
- if (IS_845G(dev_priv) || IS_I865G(dev_priv))
+ if (IS_845G(dev) || IS_I865G(dev))
i845_update_cursor(crtc, base);
else
i9xx_update_cursor(crtc, base);
@@ -6968,7 +6967,7 @@ intel_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file,
addr = obj->phys_obj->handle->segs[0].ds_addr;
}
- if (IS_GEN2(dev_priv))
+ if (IS_GEN2(dev))
I915_WRITE(CURSIZE, (height << 12) | width);
finish:
@@ -7338,7 +7337,7 @@ intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
fp = I915_READ(FP1(pipe));
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
- if (IS_PINEVIEW(dev_priv)) {
+ if (IS_PINEVIEW(dev)) {
clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
} else {
@@ -7346,8 +7345,8 @@ intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
}
- if (!IS_GEN2(dev_priv)) {
- if (IS_PINEVIEW(dev_priv))
+ if (!IS_GEN2(dev)) {
+ if (IS_PINEVIEW(dev))
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
else
@@ -7498,14 +7497,14 @@ intel_increase_pllclock(struct drm_crtc *crtc)
int dpll_reg = DPLL(pipe);
int dpll;
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
return;
if (!dev_priv->lvds_downclock_avail)
return;
dpll = I915_READ(dpll_reg);
- if (!HAS_PIPE_CXSR(dev_priv) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
+ if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
DRM_DEBUG_DRIVER("upclocking LVDS\n");
assert_panel_unlocked(dev_priv, pipe);
@@ -7530,7 +7529,7 @@ intel_decrease_pllclock(struct drm_crtc *crtc)
struct inteldrm_softc *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
return;
if (!dev_priv->lvds_downclock_avail)
@@ -7540,7 +7539,7 @@ intel_decrease_pllclock(struct drm_crtc *crtc)
* Since this is called by a timer, we should never get here in
* the manual case.
*/
- if (!HAS_PIPE_CXSR(dev_priv) && intel_crtc->lowfreq_avail) {
+ if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
int pipe = intel_crtc->pipe;
int dpll_reg = DPLL(pipe);
u32 dpll;
@@ -8095,7 +8094,7 @@ intel_sanitize_modesetting(struct drm_device *dev, int pipe, int plane)
I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
}
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
return;
/* Who knows what state these registers were left in by the BIOS or
@@ -8185,7 +8184,7 @@ intel_crtc_init(struct drm_device *dev, int pipe)
/* Swap pipes & planes for FBC on pre-965 */
intel_crtc->pipe = pipe;
intel_crtc->plane = pipe;
- if (IS_MOBILE(dev_priv) && IS_GEN3(dev_priv)) {
+ if (IS_MOBILE(dev) && IS_GEN3(dev)) {
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
intel_crtc->plane = !pipe;
}
@@ -8199,8 +8198,8 @@ intel_crtc_init(struct drm_device *dev, int pipe)
intel_crtc->active = true; /* force the pipe off on setup_init_config */
intel_crtc->bpp = 24; /* default for pre-Ironlake */
- if (HAS_PCH_SPLIT(dev_priv)) {
- if (pipe == 2 && IS_IVYBRIDGE(dev_priv))
+ if (HAS_PCH_SPLIT(dev)) {
+ if (pipe == 2 && IS_IVYBRIDGE(dev))
intel_crtc->no_pll = true;
intel_helper_funcs.prepare = ironlake_crtc_prepare;
intel_helper_funcs.commit = ironlake_crtc_commit;
@@ -8268,13 +8267,13 @@ has_edp_a(struct drm_device *dev)
{
struct inteldrm_softc *dev_priv = dev->dev_private;
- if (!IS_MOBILE(dev_priv))
+ if (!IS_MOBILE(dev))
return false;
if ((I915_READ(DP_A) & DP_DETECTED) == 0)
return false;
- if (IS_GEN5(dev_priv) &&
+ if (IS_GEN5(dev) &&
(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
return false;
@@ -8291,12 +8290,12 @@ intel_setup_outputs(struct drm_device *dev)
bool has_lvds;
has_lvds = intel_lvds_init(dev);
- if (!has_lvds && !HAS_PCH_SPLIT(dev_priv)) {
+ if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
/* disable the panel fitter on everything but LVDS */
I915_WRITE(PFIT_CONTROL, 0);
}
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
dpd_is_edp = intel_dpd_is_edp(dev);
if (has_edp_a(dev))
@@ -8308,7 +8307,7 @@ intel_setup_outputs(struct drm_device *dev)
intel_crt_init(dev);
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
int found;
DRM_DEBUG_KMS(
@@ -8342,18 +8341,18 @@ intel_setup_outputs(struct drm_device *dev)
if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
intel_dp_init(dev, PCH_DP_D);
- } else if (SUPPORTS_DIGITAL_OUTPUTS(dev_priv)) {
+ } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
bool found = false;
if (I915_READ(SDVOB) & SDVO_DETECTED) {
DRM_DEBUG_KMS("probing SDVOB\n");
found = intel_sdvo_init(dev, SDVOB);
- if (!found && SUPPORTS_INTEGRATED_HDMI(dev_priv)) {
+ if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
intel_hdmi_init(dev, SDVOB);
}
- if (!found && SUPPORTS_INTEGRATED_DP(dev_priv)) {
+ if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
DRM_DEBUG_KMS("probing DP_B\n");
intel_dp_init(dev, DP_B);
}
@@ -8368,26 +8367,26 @@ intel_setup_outputs(struct drm_device *dev)
if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
- if (SUPPORTS_INTEGRATED_HDMI(dev_priv)) {
+ if (SUPPORTS_INTEGRATED_HDMI(dev)) {
DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
intel_hdmi_init(dev, SDVOC);
}
- if (SUPPORTS_INTEGRATED_DP(dev_priv)) {
+ if (SUPPORTS_INTEGRATED_DP(dev)) {
DRM_DEBUG_KMS("probing DP_C\n");
intel_dp_init(dev, DP_C);
}
}
- if (SUPPORTS_INTEGRATED_DP(dev_priv) &&
+ if (SUPPORTS_INTEGRATED_DP(dev) &&
(I915_READ(DP_D) & DP_DETECTED)) {
DRM_DEBUG_KMS("probing DP_D\n");
intel_dp_init(dev, DP_D);
}
- } else if (IS_GEN2(dev_priv)) {
+ } else if (IS_GEN2(dev)) {
intel_dvo_init(dev);
}
- if (SUPPORTS_TV(dev_priv))
+ if (SUPPORTS_TV(dev))
intel_tv_init(dev);
TAILQ_FOREACH(encoder, &dev->mode_config.encoder_list, head) {
@@ -8405,7 +8404,7 @@ intel_setup_outputs(struct drm_device *dev)
__func__);
#endif
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
ironlake_init_pch_refclk(dev);
}
@@ -8774,8 +8773,6 @@ intel_init_emon(struct drm_device *dev)
int
intel_enable_rc6(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev->dev_private;
-
/*
* Respect the kernel parameter if it is set
*/
@@ -8785,13 +8782,13 @@ intel_enable_rc6(struct drm_device *dev)
/*
* Disable RC6 on Ironlake
*/
- if (INTEL_INFO(dev_priv)->gen == 5)
+ if (INTEL_INFO(dev)->gen == 5)
return 0;
/*
* Enable rc6 on Sandybridge if DMA remapping is disabled
*/
- if (INTEL_INFO(dev_priv)->gen == 6) {
+ if (INTEL_INFO(dev)->gen == 6) {
DRM_DEBUG_DRIVER(
"Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
intel_iommu_enabled ? "true" : "false",
@@ -9080,7 +9077,7 @@ ironlake_init_clock_gating(struct drm_device *dev)
* The bit 22 of 0x42004
* The bit 7,8,9 of 0x42020.
*/
- if (IS_IRONLAKE_M(dev_priv)) {
+ if (IS_IRONLAKE_M(dev)) {
I915_WRITE(ILK_DISPLAY_CHICKEN1,
I915_READ(ILK_DISPLAY_CHICKEN1) |
ILK_FBCQ_DIS);
@@ -9226,7 +9223,7 @@ g4x_init_clock_gating(struct drm_device *dev)
dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
OVRUNIT_CLOCK_GATE_DISABLE |
OVCUNIT_CLOCK_GATE_DISABLE;
- if (IS_GM45(dev_priv))
+ if (IS_GM45(dev))
dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
}
@@ -9468,7 +9465,7 @@ intel_init_display(struct drm_device *dev)
struct inteldrm_softc *dev_priv = dev->dev_private;
/* We always want a DPMS function */
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.dpms = ironlake_crtc_dpms;
dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
dev_priv->display.update_plane = ironlake_update_plane;
@@ -9478,16 +9475,16 @@ intel_init_display(struct drm_device *dev)
dev_priv->display.update_plane = i9xx_update_plane;
}
- if (I915_HAS_FBC(dev_priv)) {
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (I915_HAS_FBC(dev)) {
+ if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
dev_priv->display.enable_fbc = ironlake_enable_fbc;
dev_priv->display.disable_fbc = ironlake_disable_fbc;
- } else if (IS_GM45(dev_priv)) {
+ } else if (IS_GM45(dev)) {
dev_priv->display.fbc_enabled = g4x_fbc_enabled;
dev_priv->display.enable_fbc = g4x_enable_fbc;
dev_priv->display.disable_fbc = g4x_disable_fbc;
- } else if (IS_CRESTLINE(dev_priv)) {
+ } else if (IS_CRESTLINE(dev)) {
dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
dev_priv->display.enable_fbc = i8xx_enable_fbc;
dev_priv->display.disable_fbc = i8xx_disable_fbc;
@@ -9496,22 +9493,22 @@ intel_init_display(struct drm_device *dev)
}
/* Returns the core display clock speed */
- if (IS_I945G(dev_priv) || (IS_G33(dev_priv) && !IS_PINEVIEW_M(dev_priv)))
+ if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
dev_priv->display.get_display_clock_speed =
i945_get_display_clock_speed;
- else if (IS_I915G(dev_priv))
+ else if (IS_I915G(dev))
dev_priv->display.get_display_clock_speed =
i915_get_display_clock_speed;
- else if (IS_I945GM(dev_priv) || IS_845G(dev_priv) || IS_PINEVIEW_M(dev_priv))
+ else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
dev_priv->display.get_display_clock_speed =
i9xx_misc_get_display_clock_speed;
- else if (IS_I915GM(dev_priv))
+ else if (IS_I915GM(dev))
dev_priv->display.get_display_clock_speed =
i915gm_get_display_clock_speed;
- else if (IS_I865G(dev_priv))
+ else if (IS_I865G(dev))
dev_priv->display.get_display_clock_speed =
i865_get_display_clock_speed;
- else if (IS_I85X(dev_priv))
+ else if (IS_I85X(dev))
dev_priv->display.get_display_clock_speed =
i855_get_display_clock_speed;
else /* 852, 830 */
@@ -9519,12 +9516,12 @@ intel_init_display(struct drm_device *dev)
i830_get_display_clock_speed;
/* For FIFO watermark updates */
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
/* IVB configs may use multi-threaded forcewake */
- if (IS_IVYBRIDGE(dev_priv)) {
+ if (IS_IVYBRIDGE(dev)) {
u32 ecobus;
/* A small trick here - if the bios hasn't configured MT forcewake,
@@ -9553,7 +9550,7 @@ intel_init_display(struct drm_device *dev)
else if (HAS_PCH_CPT(dev_priv))
dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
- if (IS_GEN5(dev_priv)) {
+ if (IS_GEN5(dev)) {
if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
dev_priv->display.update_wm = ironlake_update_wm;
else {
@@ -9564,7 +9561,7 @@ intel_init_display(struct drm_device *dev)
dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
dev_priv->display.write_eld = ironlake_write_eld;
- } else if (IS_GEN6(dev_priv)) {
+ } else if (IS_GEN6(dev)) {
if (SNB_READ_WM0_LATENCY()) {
dev_priv->display.update_wm = sandybridge_update_wm;
dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
@@ -9576,7 +9573,7 @@ intel_init_display(struct drm_device *dev)
dev_priv->display.fdi_link_train = gen6_fdi_link_train;
dev_priv->display.init_clock_gating = gen6_init_clock_gating;
dev_priv->display.write_eld = ironlake_write_eld;
- } else if (IS_IVYBRIDGE(dev_priv)) {
+ } else if (IS_IVYBRIDGE(dev)) {
/* FIXME: detect B0+ stepping and use auto training */
dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
if (SNB_READ_WM0_LATENCY()) {
@@ -9591,8 +9588,8 @@ intel_init_display(struct drm_device *dev)
dev_priv->display.write_eld = ironlake_write_eld;
} else
dev_priv->display.update_wm = NULL;
- } else if (IS_PINEVIEW(dev_priv)) {
- if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
+ } else if (IS_PINEVIEW(dev)) {
+ if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
dev_priv->is_ddr3,
dev_priv->fsb_freq,
dev_priv->mem_freq)) {
@@ -9607,32 +9604,32 @@ intel_init_display(struct drm_device *dev)
} else
dev_priv->display.update_wm = pineview_update_wm;
dev_priv->display.init_clock_gating = gen3_init_clock_gating;
- } else if (IS_G4X(dev_priv)) {
+ } else if (IS_G4X(dev)) {
dev_priv->display.write_eld = g4x_write_eld;
dev_priv->display.update_wm = g4x_update_wm;
dev_priv->display.init_clock_gating = g4x_init_clock_gating;
- } else if (IS_GEN4(dev_priv)) {
+ } else if (IS_GEN4(dev)) {
dev_priv->display.update_wm = i965_update_wm;
- if (IS_CRESTLINE(dev_priv))
+ if (IS_CRESTLINE(dev))
dev_priv->display.init_clock_gating = crestline_init_clock_gating;
- else if (IS_BROADWATER(dev_priv))
+ else if (IS_BROADWATER(dev))
dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
- } else if (IS_GEN3(dev_priv)) {
+ } else if (IS_GEN3(dev)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
dev_priv->display.init_clock_gating = gen3_init_clock_gating;
- } else if (IS_I865G(dev_priv)) {
+ } else if (IS_I865G(dev)) {
dev_priv->display.update_wm = i830_update_wm;
dev_priv->display.init_clock_gating = i85x_init_clock_gating;
dev_priv->display.get_fifo_size = i830_get_fifo_size;
- } else if (IS_I85X(dev_priv)) {
+ } else if (IS_I85X(dev)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i85x_get_fifo_size;
dev_priv->display.init_clock_gating = i85x_init_clock_gating;
} else {
dev_priv->display.update_wm = i830_update_wm;
dev_priv->display.init_clock_gating = i830_init_clock_gating;
- if (IS_845G(dev_priv))
+ if (IS_845G(dev))
dev_priv->display.get_fifo_size = i845_get_fifo_size;
else
dev_priv->display.get_fifo_size = i830_get_fifo_size;
@@ -9642,7 +9639,7 @@ intel_init_display(struct drm_device *dev)
#ifdef notyet
dev_priv->display.queue_flip = intel_default_queue_flip;
- switch (INTEL_INFO(dev_priv)->gen) {
+ switch (INTEL_INFO(dev)->gen) {
case 2:
dev_priv->display.queue_flip = intel_gen2_queue_flip;
break;
@@ -9753,7 +9750,7 @@ i915_disable_vga(struct drm_device *dev)
u8 sr1;
u32 vga_reg;
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
vga_reg = CPU_VGACNTRL;
else
vga_reg = VGACNTRL;
@@ -9794,10 +9791,10 @@ intel_modeset_init(struct drm_device *dev)
intel_init_display(dev);
- if (IS_GEN2(dev_priv)) {
+ if (IS_GEN2(dev)) {
dev->mode_config.max_width = 2048;
dev->mode_config.max_height = 2048;
- } else if (IS_GEN3(dev_priv)) {
+ } else if (IS_GEN3(dev)) {
dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096;
} else {
@@ -9826,12 +9823,12 @@ intel_modeset_init(struct drm_device *dev)
intel_init_clock_gating(dev);
- if (IS_IRONLAKE_M(dev_priv)) {
+ if (IS_IRONLAKE_M(dev)) {
ironlake_enable_drps(dev);
intel_init_emon(dev);
}
- if (IS_GEN6(dev_priv)) {
+ if (IS_GEN6(dev)) {
gen6_enable_rps(dev_priv);
gen6_update_ring_freq(dev_priv);
}
@@ -9847,9 +9844,7 @@ intel_modeset_init(struct drm_device *dev)
void
intel_modeset_gem_init(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev->dev_private;
-
- if (IS_IRONLAKE_M(dev_priv))
+ if (IS_IRONLAKE_M(dev))
ironlake_enable_rc6(dev);
intel_setup_overlay(dev);
@@ -9880,12 +9875,12 @@ intel_modeset_cleanup(struct drm_device *dev)
intel_disable_fbc(dev);
- if (IS_IRONLAKE_M(dev_priv))
+ if (IS_IRONLAKE_M(dev))
ironlake_disable_drps(dev);
- if (IS_GEN6(dev_priv))
+ if (IS_GEN6(dev))
gen6_disable_rps(dev);
- if (IS_IRONLAKE_M(dev_priv))
+ if (IS_IRONLAKE_M(dev))
ironlake_disable_rc6(dev);
/* Disable the irq before mode object teardown, for the irq might
@@ -10012,7 +10007,7 @@ intel_display_capture_error_state(struct drm_device *dev)
error->plane[i].size = I915_READ(DSPSIZE(i));
error->plane[i].pos = I915_READ(DSPPOS(i));
error->plane[i].addr = I915_READ(DSPADDR(i));
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
error->plane[i].surface = I915_READ(DSPSURF(i));
error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
}
@@ -10054,7 +10049,7 @@ intel_display_print_error_state(struct sbuf *m, struct drm_device *dev,
sbuf_printf(m, " SIZE: %08x\n", error->plane[i].size);
sbuf_printf(m, " POS: %08x\n", error->plane[i].pos);
sbuf_printf(m, " ADDR: %08x\n", error->plane[i].addr);
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
sbuf_printf(m, " SURF: %08x\n", error->plane[i].surface);
sbuf_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
}
diff --git a/sys/dev/pci/drm/intel_dp.c b/sys/dev/pci/drm/intel_dp.c
index d5f03d70e22..bc34f5287cf 100644
--- a/sys/dev/pci/drm/intel_dp.c
+++ b/sys/dev/pci/drm/intel_dp.c
@@ -494,11 +494,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, uint8_t *send, int send_bytes,
* clock divider.
*/
if (is_cpu_edp(intel_dp)) {
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
else
aux_clock_divider = 225; /* eDP input clock at 450Mhz */
- } else if (HAS_PCH_SPLIT(dev_priv))
+ } else if (HAS_PCH_SPLIT(dev))
aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
else
aux_clock_divider = intel_hrawclk(dev) / 2;
@@ -899,7 +899,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
mode->clock, adjusted_mode->clock, &m_n);
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(TRANSDATA_M1(pipe),
((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
m_n.gmch_m);
@@ -991,7 +991,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
/* Split out the IBX/CPU vs CPT settings */
- if (is_cpu_edp(intel_dp) && IS_GEN7(dev_priv)) {
+ if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
intel_dp->DP |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -1230,7 +1230,7 @@ ironlake_edp_panel_on(struct intel_dp *intel_dp)
ironlake_wait_panel_power_cycle(intel_dp);
pp = ironlake_get_pp_control(dev_priv);
- if (IS_GEN5(dev_priv)) {
+ if (IS_GEN5(dev)) {
/* ILK workaround: disable reset around power sequence */
pp &= ~PANEL_POWER_RESET;
I915_WRITE(PCH_PP_CONTROL, pp);
@@ -1238,7 +1238,7 @@ ironlake_edp_panel_on(struct intel_dp *intel_dp)
}
pp |= POWER_TARGET_ON;
- if (!IS_GEN5(dev_priv))
+ if (!IS_GEN5(dev))
pp |= PANEL_POWER_RESET;
I915_WRITE(PCH_PP_CONTROL, pp);
@@ -1246,7 +1246,7 @@ ironlake_edp_panel_on(struct intel_dp *intel_dp)
ironlake_wait_panel_on(intel_dp);
- if (IS_GEN5(dev_priv)) {
+ if (IS_GEN5(dev)) {
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
@@ -1546,7 +1546,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp->base.base.dev;
struct inteldrm_softc *dev_priv = dev->dev_private;
- if (IS_GEN7(dev_priv) && is_cpu_edp(intel_dp))
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
return DP_TRAIN_VOLTAGE_SWING_800;
else if (HAS_PCH_CPT(dev_priv) && !is_cpu_edp(intel_dp))
return DP_TRAIN_VOLTAGE_SWING_1200;
@@ -1558,9 +1558,8 @@ uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
struct drm_device *dev = intel_dp->base.base.dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
- if (IS_GEN7(dev_priv) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_400:
return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1812,7 +1811,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
DP |= DP_PORT_EN;
- if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev_priv) || !is_cpu_edp(intel_dp)))
+ if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
DP &= ~DP_LINK_TRAIN_MASK_CPT;
else
DP &= ~DP_LINK_TRAIN_MASK;
@@ -1827,10 +1826,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
uint32_t signal_levels;
- if (IS_GEN7(dev_priv) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
- } else if (IS_GEN6(dev_priv) && is_cpu_edp(intel_dp)) {
+ } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
} else {
@@ -1839,7 +1838,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
}
- if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev_priv) || !is_cpu_edp(intel_dp)))
+ if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
else
reg = DP | DP_LINK_TRAIN_PAT_1;
@@ -1919,10 +1918,10 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
break;
}
- if (IS_GEN7(dev_priv) && is_cpu_edp(intel_dp)) {
+ if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
- } else if (IS_GEN6(dev_priv) && is_cpu_edp(intel_dp)) {
+ } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
} else {
@@ -1930,7 +1929,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
}
- if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev_priv) || !is_cpu_edp(intel_dp)))
+ if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
else
reg = DP | DP_LINK_TRAIN_PAT_2;
@@ -1970,7 +1969,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
++tries;
}
- if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev_priv) || !is_cpu_edp(intel_dp)))
+ if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
reg = DP | DP_LINK_TRAIN_OFF_CPT;
else
reg = DP | DP_LINK_TRAIN_OFF;
@@ -2000,7 +1999,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
DELAY(100);
}
- if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev_priv) || !is_cpu_edp(intel_dp))) {
+ if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
DP &= ~DP_LINK_TRAIN_MASK_CPT;
I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
} else {
@@ -2012,7 +2011,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
drm_msleep(17, "915dlo");
if (is_edp(intel_dp)) {
- if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev_priv) || !is_cpu_edp(intel_dp)))
+ if (HAS_PCH_CPT(dev_priv) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
DP |= DP_LINK_TRAIN_OFF_CPT;
else
DP |= DP_LINK_TRAIN_OFF;
@@ -2237,13 +2236,12 @@ intel_dp_detect(struct drm_connector *connector, bool force)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_device *dev = intel_dp->base.base.dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
enum drm_connector_status status;
struct edid *edid = NULL;
intel_dp->has_audio = false;
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
status = ironlake_dp_detect(intel_dp);
else
status = g4x_dp_detect(intel_dp);
@@ -2541,7 +2539,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
M_WAITOK | M_ZERO);
intel_encoder = &intel_dp->base;
- if (HAS_PCH_SPLIT(dev_priv) && output_reg == PCH_DP_D)
+ if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
if (intel_dpd_is_edp(dev))
intel_dp->is_pch_edp = true;
@@ -2696,7 +2694,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
* 0xd. Failure to do so will result in spurious interrupts being
* generated on the port when a cable is not attached.
*/
- if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
+ if (IS_G4X(dev) && !IS_GM45(dev)) {
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
}
diff --git a/sys/dev/pci/drm/intel_hdmi.c b/sys/dev/pci/drm/intel_hdmi.c
index 03afaaf2b85..94200f99937 100644
--- a/sys/dev/pci/drm/intel_hdmi.c
+++ b/sys/dev/pci/drm/intel_hdmi.c
@@ -259,7 +259,7 @@ intel_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
u32 sdvox;
sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
- if (!HAS_PCH_SPLIT(dev_priv))
+ if (!HAS_PCH_SPLIT(dev))
sdvox |= intel_hdmi->color_range;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
@@ -312,7 +312,7 @@ intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
/* HW workaround, need to toggle enable bit off and on for 12bpc, but
* we do this anyway which shows more stable in testing.
*/
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
POSTING_READ(intel_hdmi->sdvox_reg);
}
@@ -329,7 +329,7 @@ intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
/* HW workaround, need to write this twice for issue that may result
* in first write getting masked.
*/
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(intel_hdmi->sdvox_reg, temp);
POSTING_READ(intel_hdmi->sdvox_reg);
}
@@ -584,7 +584,7 @@ intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
intel_hdmi->sdvox_reg = sdvox_reg;
- if (!HAS_PCH_SPLIT(dev_priv)) {
+ if (!HAS_PCH_SPLIT(dev)) {
intel_hdmi->write_infoframe = i9xx_write_infoframe;
I915_WRITE(VIDEO_DIP_CTL, 0);
} else {
@@ -606,7 +606,7 @@ intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
* 0xd. Failure to do so will result in spurious interrupts being
* generated on the port when a cable is not attached.
*/
- if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
+ if (IS_G4X(dev) && !IS_GM45(dev)) {
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
}
diff --git a/sys/dev/pci/drm/intel_i2c.c b/sys/dev/pci/drm/intel_i2c.c
index 1dd4df3b21c..59f551b88a2 100644
--- a/sys/dev/pci/drm/intel_i2c.c
+++ b/sys/dev/pci/drm/intel_i2c.c
@@ -99,13 +99,14 @@ gmbus_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
void
i915_i2c_probe(struct inteldrm_softc *dev_priv)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
struct gmbus_port gp;
struct i2c_controller ic;
uint8_t buf[128];
uint8_t cmd;
int err, i;
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
else
dev_priv->gpio_mmio_base = 0;
@@ -133,7 +134,9 @@ i915_i2c_probe(struct inteldrm_softc *dev_priv)
int
intel_setup_gmbus(struct inteldrm_softc *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
+
+ if (HAS_PCH_SPLIT(dev))
dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
else
dev_priv->gpio_mmio_base = 0;
diff --git a/sys/dev/pci/drm/intel_lvds.c b/sys/dev/pci/drm/intel_lvds.c
index 713c10b6a8d..c67fe8a4719 100644
--- a/sys/dev/pci/drm/intel_lvds.c
+++ b/sys/dev/pci/drm/intel_lvds.c
@@ -102,7 +102,7 @@ intel_lvds_enable(struct intel_lvds *intel_lvds)
u32 ctl_reg, lvds_reg, stat_reg;
int retries;
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
ctl_reg = PCH_PP_CONTROL;
lvds_reg = PCH_LVDS;
stat_reg = PCH_PP_STATUS;
@@ -151,7 +151,7 @@ intel_lvds_disable(struct intel_lvds *intel_lvds)
u32 ctl_reg, lvds_reg, stat_reg;
int retries;
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
ctl_reg = PCH_PP_CONTROL;
lvds_reg = PCH_LVDS;
stat_reg = PCH_PP_STATUS;
@@ -281,7 +281,7 @@ intel_lvds_mode_fixup(struct drm_encoder *encoder,
int pipe;
/* Should never happen!! */
- if (INTEL_INFO(dev_priv)->gen < 4 && intel_crtc->pipe == 0) {
+ if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
DRM_ERROR("Can't support LVDS on pipe A\n");
return false;
}
@@ -303,7 +303,7 @@ intel_lvds_mode_fixup(struct drm_encoder *encoder,
*/
intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode);
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
intel_pch_panel_fitting(dev, intel_lvds->fitting_mode,
mode, adjusted_mode);
return true;
@@ -315,7 +315,7 @@ intel_lvds_mode_fixup(struct drm_encoder *encoder,
goto out;
/* 965+ wants fuzzy fitting */
- if (INTEL_INFO(dev_priv)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
PFIT_FILTER_FUZZY);
@@ -343,7 +343,7 @@ intel_lvds_mode_fixup(struct drm_encoder *encoder,
case DRM_MODE_SCALE_ASPECT:
/* Scale but preserve the aspect ratio */
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
@@ -403,7 +403,7 @@ intel_lvds_mode_fixup(struct drm_encoder *encoder,
if (mode->vdisplay != adjusted_mode->vdisplay ||
mode->hdisplay != adjusted_mode->hdisplay) {
pfit_control |= PFIT_ENABLE;
- if (INTEL_INFO(dev_priv)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
pfit_control |= PFIT_SCALING_AUTO;
else
pfit_control |= (VERT_AUTO_SCALE |
@@ -425,7 +425,7 @@ out:
}
/* Make sure pre-965 set dither correctly */
- if (INTEL_INFO(dev_priv)->gen < 4 && dev_priv->lvds_dither)
+ if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
if (pfit_control != intel_lvds->pfit_control ||
@@ -449,14 +449,14 @@ void
intel_lvds_prepare(struct drm_encoder *encoder)
{
struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
- struct inteldrm_softc *dev_priv = encoder->dev->dev_private;
+ struct drm_device *dev = encoder->dev;
/*
* Prior to Ironlake, we must disable the pipe if we want to adjust
* the panel fitter. However at all other times we can just reset
* the registers regardless.
*/
- if (!HAS_PCH_SPLIT(dev_priv) && intel_lvds->pfit_dirty)
+ if (!HAS_PCH_SPLIT(dev) && intel_lvds->pfit_dirty)
intel_lvds_disable(intel_lvds);
}
@@ -933,16 +933,14 @@ lvds_is_present_in_vbt(struct drm_device *dev, u8 *i2c_pin)
bool
intel_lvds_supported(struct drm_device *dev)
{
- struct inteldrm_softc *dev_priv = dev->dev_private;
-
/* With the introduction of the PCH we gained a dedicated
* LVDS presence pin, use it. */
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
return true;
/* Otherwise LVDS was only attached to mobile products,
* except for the inglorious 830gm */
- return IS_MOBILE(dev_priv) && !IS_I830(dev_priv);
+ return IS_MOBILE(dev) && !IS_I830(dev);
}
/**
@@ -980,7 +978,7 @@ intel_lvds_init(struct drm_device *dev)
return false;
}
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
return false;
if (dev_priv->edp.support) {
@@ -994,7 +992,7 @@ intel_lvds_init(struct drm_device *dev)
intel_connector = malloc(sizeof(struct intel_connector), M_DRM,
M_WAITOK | M_ZERO);
- if (!HAS_PCH_SPLIT(dev_priv)) {
+ if (!HAS_PCH_SPLIT(dev)) {
intel_lvds->pfit_control = I915_READ(PFIT_CONTROL);
}
@@ -1011,7 +1009,7 @@ intel_lvds_init(struct drm_device *dev)
intel_encoder->type = INTEL_OUTPUT_LVDS;
intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
else
intel_encoder->crtc_mask = (1 << 1);
@@ -1098,7 +1096,7 @@ intel_lvds_init(struct drm_device *dev)
*/
/* Ironlake: FIXME if still fail, not try pipe mode now */
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
goto failed;
lvds = I915_READ(LVDS);
@@ -1119,7 +1117,7 @@ intel_lvds_init(struct drm_device *dev)
goto failed;
out:
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
u32 pwm;
pipe = (I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) ? 1 : 0;
diff --git a/sys/dev/pci/drm/intel_overlay.c b/sys/dev/pci/drm/intel_overlay.c
index bd2e070a668..00b07b3ef95 100644
--- a/sys/dev/pci/drm/intel_overlay.c
+++ b/sys/dev/pci/drm/intel_overlay.c
@@ -256,7 +256,7 @@ intel_overlay_map_regs(struct intel_overlay *overlay)
struct overlay_registers *regs;
struct inteldrm_softc *dev_priv = overlay->dev->dev_private;
- if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) {
+ if (OVERLAY_NEEDS_PHYSICAL(dev)) {
regs = overlay->reg_bo->phys_obj->handle->vaddr;
} else {
regs = pmap_mapdev_attr(overlay->dev->agp->base +
@@ -275,7 +275,7 @@ intel_overlay_unmap_regs(struct intel_overlay *overlay,
#if 0
struct inteldrm_softc *dev_priv = overlay->dev->dev_private;
- if (!OVERLAY_NEEDS_PHYSICAL(dev_priv))
+ if (!OVERLAY_NEEDS_PHYSICAL(dev))
pmap_unmapdev((vm_offset_t)regs, PAGE_SIZE);
#endif
}
@@ -652,9 +652,8 @@ uv_vsubsampling(u32 format)
u32
calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
{
- struct inteldrm_softc *dev_priv = dev->dev_private;
u32 mask, shift, ret;
- if (IS_GEN2(dev_priv)) {
+ if (IS_GEN2(dev)) {
mask = 0x1f;
shift = 5;
} else {
@@ -662,7 +661,7 @@ calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
shift = 6;
}
ret = ((offset + width + mask) >> shift) - (offset >> shift);
- if (!IS_GEN2(dev_priv))
+ if (!IS_GEN2(dev))
ret <<= 1;
ret -= 1;
return ret << 2;
@@ -851,6 +850,7 @@ intel_overlay_do_put_image(struct intel_overlay *overlay,
struct drm_i915_gem_object *new_bo, struct put_image_params *params)
{
struct inteldrm_softc *dev_priv;
+ struct drm_device *dev = overlay->dev;
int ret, tmp_width;
struct overlay_registers *regs;
bool scale_changed = false;
@@ -881,7 +881,7 @@ intel_overlay_do_put_image(struct intel_overlay *overlay,
goto out_unpin;
}
regs->OCONFIG = OCONF_CC_OUT_8BIT;
- if (IS_GEN4(dev_priv))
+ if (IS_GEN4(dev))
regs->OCONFIG |= OCONF_CSC_MODE_BT709;
regs->OCONFIG |= overlay->crtc->pipe == 0 ?
OCONF_PIPE_A : OCONF_PIPE_B;
@@ -990,12 +990,13 @@ check_overlay_possible_on_crtc(struct intel_overlay *overlay,
struct intel_crtc *crtc)
{
struct inteldrm_softc *dev_priv = overlay->dev->dev_private;
+ struct drm_device *dev = overlay->dev;
if (!crtc->active)
return -EINVAL;
/* can't use the overlay with double wide pipe */
- if (INTEL_INFO(dev_priv)->gen < 4 &&
+ if (INTEL_INFO(dev)->gen < 4 &&
(I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
return -EINVAL;
@@ -1013,7 +1014,7 @@ update_pfit_vscale_ratio(struct intel_overlay *overlay)
/* XXX: This is not the same logic as in the xorg driver, but more in
* line with the intel documentation for the i965
*/
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
/* on i965 use the PGM reg to read out the autoscaler values */
ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
} else {
@@ -1063,7 +1064,6 @@ check_overlay_src(struct drm_device *dev,
struct drm_intel_overlay_put_image *rec,
struct drm_i915_gem_object *new_bo_priv)
{
- struct inteldrm_softc *dev_priv = dev->dev_private;
struct drm_obj *new_bo = (struct drm_obj *)new_bo_priv;
int uv_hscale = uv_hsubsampling(rec->flags);
int uv_vscale = uv_vsubsampling(rec->flags);
@@ -1131,7 +1131,7 @@ check_overlay_src(struct drm_device *dev,
if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
return -EINVAL;
- if (IS_GEN4(dev_priv) && rec->stride_Y < 512)
+ if (IS_GEN4(dev) && rec->stride_Y < 512)
return -EINVAL;
tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
@@ -1193,7 +1193,7 @@ intel_panel_fitter_pipe(struct drm_device *dev)
return -1;
/* 965 can place panel fitter on either pipe */
- if (IS_GEN4(dev_priv))
+ if (IS_GEN4(dev))
return (pfit_control >> 29) & 0x3;
/* older chips can only use pipe 1 */
@@ -1435,7 +1435,7 @@ intel_overlay_attrs(struct drm_device *dev, void *data,
attrs->contrast = overlay->contrast;
attrs->saturation = overlay->saturation;
- if (!IS_GEN2(dev_priv)) {
+ if (!IS_GEN2(dev)) {
attrs->gamma0 = I915_READ(OGAMC0);
attrs->gamma1 = I915_READ(OGAMC1);
attrs->gamma2 = I915_READ(OGAMC2);
@@ -1467,7 +1467,7 @@ intel_overlay_attrs(struct drm_device *dev, void *data,
intel_overlay_unmap_regs(overlay, regs);
if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
- if (IS_GEN2(dev_priv))
+ if (IS_GEN2(dev))
goto out_unlock;
if (overlay->active) {
@@ -1505,7 +1505,7 @@ intel_setup_overlay(struct drm_device *dev)
struct overlay_registers *regs;
int ret;
- if (!HAS_OVERLAY(dev_priv))
+ if (!HAS_OVERLAY(dev))
return;
overlay = malloc(sizeof(struct intel_overlay), M_DRM,
@@ -1522,7 +1522,7 @@ intel_setup_overlay(struct drm_device *dev)
goto out_free;
overlay->reg_bo = reg_bo;
- if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) {
+ if (OVERLAY_NEEDS_PHYSICAL(dev)) {
ret = i915_gem_attach_phys_object(dev, reg_bo,
I915_GEM_PHYS_OVERLAY_REGS,
PAGE_SIZE);
@@ -1568,7 +1568,7 @@ intel_setup_overlay(struct drm_device *dev)
return;
out_unpin_bo:
- if (!OVERLAY_NEEDS_PHYSICAL(dev_priv))
+ if (!OVERLAY_NEEDS_PHYSICAL(dev))
i915_gem_object_unpin(reg_bo);
out_free_bo:
drm_gem_object_unreference(&reg_bo->base);
@@ -1624,7 +1624,7 @@ intel_overlay_capture_error_state(struct drm_device *dev)
error->dovsta = I915_READ(DOVSTA);
error->isr = I915_READ(ISR);
- if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
+ if (OVERLAY_NEEDS_PHYSICAL(dev))
error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
else
error->base = (long) overlay->reg_bo->gtt_offset;
diff --git a/sys/dev/pci/drm/intel_panel.c b/sys/dev/pci/drm/intel_panel.c
index dad7481ee87..5b0ddb8071c 100644
--- a/sys/dev/pci/drm/intel_panel.c
+++ b/sys/dev/pci/drm/intel_panel.c
@@ -129,10 +129,10 @@ is_backlight_combination_mode(struct drm_device *dev)
{
struct inteldrm_softc *dev_priv = dev->dev_private;
- if (INTEL_INFO(dev_priv)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
- if (IS_GEN2(dev_priv))
+ if (IS_GEN2(dev))
return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
return 0;
@@ -141,11 +141,12 @@ is_backlight_combination_mode(struct drm_device *dev)
u32
i915_read_blc_pwm_ctl(struct inteldrm_softc *dev_priv)
{
+ struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
u32 val;
/* Restore the CTL value if it lost, e.g. GPU reset */
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
if (dev_priv->saveBLC_PWM_CTL2 == 0) {
dev_priv->saveBLC_PWM_CTL2 = val;
@@ -188,10 +189,10 @@ intel_panel_get_max_backlight(struct drm_device *dev)
return 1;
}
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
max >>= 16;
} else {
- if (INTEL_INFO(dev_priv)->gen < 4)
+ if (INTEL_INFO(dev)->gen < 4)
max >>= 17;
else
max >>= 16;
@@ -210,11 +211,11 @@ intel_panel_get_backlight(struct drm_device *dev)
struct inteldrm_softc *dev_priv = dev->dev_private;
u32 val;
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev)) {
val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
} else {
val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
- if (INTEL_INFO(dev_priv)->gen < 4)
+ if (INTEL_INFO(dev)->gen < 4)
val >>= 1;
if (is_backlight_combination_mode(dev)) {
@@ -246,7 +247,7 @@ intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
DRM_DEBUG("set backlight PWM = %d\n", level);
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev))
return intel_pch_panel_set_backlight(dev, level);
if (is_backlight_combination_mode(dev)) {
@@ -259,7 +260,7 @@ intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
}
tmp = I915_READ(BLC_PWM_CTL);
- if (INTEL_INFO(dev_priv)->gen < 4)
+ if (INTEL_INFO(dev)->gen < 4)
level <<= 1;
tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
I915_WRITE(BLC_PWM_CTL, tmp | level);
diff --git a/sys/dev/pci/drm/intel_sdvo.c b/sys/dev/pci/drm/intel_sdvo.c
index e2b2ba26af1..d55fad95fd3 100644
--- a/sys/dev/pci/drm/intel_sdvo.c
+++ b/sys/dev/pci/drm/intel_sdvo.c
@@ -1201,13 +1201,13 @@ intel_sdvo_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
return;
/* Set the SDVO control regs. */
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
/* The real mode polarity is set by the SDVO commands, using
* struct intel_sdvo_dtd. */
sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
if (intel_sdvo->is_hdmi)
sdvox |= intel_sdvo->color_range;
- if (INTEL_INFO(dev_priv)->gen < 5)
+ if (INTEL_INFO(dev)->gen < 5)
sdvox |= SDVO_BORDER_ENABLE;
} else {
sdvox = I915_READ(intel_sdvo->sdvo_reg);
@@ -1230,16 +1230,16 @@ intel_sdvo_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
if (intel_sdvo->has_hdmi_audio)
sdvox |= SDVO_AUDIO_ENABLE;
- if (INTEL_INFO(dev_priv)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4) {
/* done in crtc_mode_set as the dpll_md reg must be written early */
- } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
+ } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
/* done in crtc_mode_set as it lives inside the dpll register */
} else {
sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
}
if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
- INTEL_INFO(dev_priv)->gen < 5)
+ INTEL_INFO(dev)->gen < 5)
sdvox |= SDVO_STALL_SELECT;
intel_sdvo_write_sdvox(intel_sdvo, sdvox);
}
@@ -1361,12 +1361,11 @@ int
intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
{
struct drm_device *dev = intel_sdvo->base.base.dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
u8 response[2];
/* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
* on the line. */
- if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
+ if (IS_I945G(dev) || IS_I945GM(dev))
return false;
return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
@@ -2165,10 +2164,9 @@ void
intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
{
struct drm_device *dev = connector->base.base.dev;
- struct inteldrm_softc *dev_priv = dev->dev_private;
intel_attach_force_audio_property(&connector->base.base);
- if (INTEL_INFO(dev_priv)->gen >= 4 && IS_MOBILE(dev_priv))
+ if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
intel_attach_broadcast_rgb_property(&connector->base.base);
}
diff --git a/sys/dev/pci/drm/intel_sprite.c b/sys/dev/pci/drm/intel_sprite.c
index 73936a990dc..af00648035d 100644
--- a/sys/dev/pci/drm/intel_sprite.c
+++ b/sys/dev/pci/drm/intel_sprite.c
@@ -662,24 +662,23 @@ static uint32_t snb_plane_formats[] = {
int
intel_plane_init(struct drm_device *dev, enum pipe pipe)
{
- struct inteldrm_softc *dev_priv = dev->dev_private;
struct intel_plane *intel_plane;
unsigned long possible_crtcs;
int ret;
- if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
+ if (!(IS_GEN6(dev) || IS_GEN7(dev)))
return -ENODEV;
intel_plane = malloc(sizeof(struct intel_plane), M_DRM,
M_WAITOK | M_ZERO);
- if (IS_GEN6(dev_priv)) {
+ if (IS_GEN6(dev)) {
intel_plane->max_downscale = 16;
intel_plane->update_plane = snb_update_plane;
intel_plane->disable_plane = snb_disable_plane;
intel_plane->update_colorkey = snb_update_colorkey;
intel_plane->get_colorkey = snb_get_colorkey;
- } else if (IS_GEN7(dev_priv)) {
+ } else if (IS_GEN7(dev)) {
intel_plane->max_downscale = 2;
intel_plane->update_plane = ivb_update_plane;
intel_plane->disable_plane = ivb_disable_plane;
diff --git a/sys/dev/pci/drm/intel_tv.c b/sys/dev/pci/drm/intel_tv.c
index 80e861208e5..44cd04bae6b 100644
--- a/sys/dev/pci/drm/intel_tv.c
+++ b/sys/dev/pci/drm/intel_tv.c
@@ -1042,7 +1042,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
color_conversion->av);
}
- if (INTEL_INFO(dev_priv)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
I915_WRITE(TV_CLR_KNOBS, 0x00404000);
else
I915_WRITE(TV_CLR_KNOBS, 0x00606000);
@@ -1065,7 +1065,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
/* Wait for vblank for the disable to take effect */
- if (IS_GEN2(dev_priv))
+ if (IS_GEN2(dev))
intel_wait_for_vblank(dev, intel_crtc->pipe);
I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 08:07:31 +0000