diff options
| author | Jonathan Gray <jsg@jsg.id.au> | 2013-03-12 01:47:44 +1100 |
|---|---|---|
| committer | Jonathan Gray <jsg@jsg.id.au> | 2013-03-12 01:47:44 +1100 |
| commit | 1cac9ac0c9d879636c330b1ba8018b85450d9563 (patch) | |
| tree | 55309706f9583293222beac5ac6673e6dc349c3d | |
| parent | bdcd9722bc3beabf7ee408b633d4539c1faaec12 (diff) | |
make the gen6+ ordering workaround conditional again
| -rw-r--r-- | sys/dev/pci/drm/intel_ringbuffer.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/sys/dev/pci/drm/intel_ringbuffer.c b/sys/dev/pci/drm/intel_ringbuffer.c index a5d8f65a1a1..c206e3bec00 100644 --- a/sys/dev/pci/drm/intel_ringbuffer.c +++ b/sys/dev/pci/drm/intel_ringbuffer.c @@ -797,10 +797,7 @@ gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) /* Workaround to force correct ordering between irq and seqno writes on * ivb (and maybe also on snb) by reading from a CS register (like * ACTHD) before reading the status page. */ -#ifdef notyet - /* XXX conditionally doing this seems to make everything laggy */ if (!lazy_coherency) -#endif intel_ring_get_active_head(ring); return intel_read_status_page(ring, I915_GEM_HWS_INDEX); } |