diff options
author | Niklas Hallqvist <niklas@cvs.openbsd.org> | 1997-07-30 13:03:51 +0000 |
---|---|---|
committer | Niklas Hallqvist <niklas@cvs.openbsd.org> | 1997-07-30 13:03:51 +0000 |
commit | 29263e651adfbf32c9bad6fe1d6ff41d6d3d96a8 (patch) | |
tree | a9784d5c08c48e05d17e485f7c6de43860a724ec | |
parent | cfeaa5f121d873079d90ef06b60788b7604d0676 (diff) |
Sync to netbsd + use OpenBSD bus_space_*_raw_ API
-rw-r--r-- | sys/dev/isa/aic6360.c | 67 |
1 files changed, 38 insertions, 29 deletions
diff --git a/sys/dev/isa/aic6360.c b/sys/dev/isa/aic6360.c index 059fcb68f89..f99cd994f7a 100644 --- a/sys/dev/isa/aic6360.c +++ b/sys/dev/isa/aic6360.c @@ -1,10 +1,14 @@ -/* $OpenBSD: aic6360.c,v 1.14 1997/07/07 18:37:19 niklas Exp $ */ -/* $NetBSD: aic6360.c,v 1.46 1996/05/12 23:51:37 mycroft Exp $ */ +/* $OpenBSD: aic6360.c,v 1.15 1997/07/30 13:03:50 niklas Exp $ */ +/* $NetBSD: aic6360.c,v 1.52 1996/12/10 21:27:51 thorpej Exp $ */ +#ifdef DDB +#define integrate +#else #define integrate static inline +#endif /* - * Copyright (c) 1994, 1995 Charles Hannum. All rights reserved. + * Copyright (c) 1994, 1995, 1996 Charles Hannum. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -73,7 +77,7 @@ #define AIC_USE_DWORDS 0 /* Synchronous data transfers? */ -#define AIC_USE_SYNCHRONOUS 1 +#define AIC_USE_SYNCHRONOUS 0 #define AIC_SYNC_REQ_ACK_OFS 8 /* Wide data transfers? */ @@ -748,7 +752,8 @@ aic_find(sc, ia) bus_space_read_multi_1(iot, ioh, ID, chip_id, sizeof(IDSTRING) - 1); AIC_START(("AIC found at 0x%x ", ia->ia_iobase)); AIC_START(("ID: %s ", chip_id)); - AIC_START(("chip revision %d\n",(int)bus_space_read_1(iot, ioh, REV))); + AIC_START(("chip revision %d\n", + (int)bus_space_read_1(iot, ioh, REV))); sc->sc_initiator = 7; sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ @@ -833,7 +838,7 @@ aic_reset(sc) bus_space_write_1(iot, ioh, TEST, 0); /* Reset SCSI-FIFO and abort any transfers */ - bus_space_write_1(iot, ioh, + SXFRCTL0, CHEN | CLRCH | CLRSTCNT); + bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH | CLRSTCNT); /* Reset DMA-FIFO */ bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); @@ -1910,11 +1915,14 @@ aic_dataout_pio(sc, p, n) int out = 0; #define DOUTAMOUNT 128 /* Full FIFO */ + AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), + bus_space_read_1(iot, ioh, SSTAT2))); + /* Clear host FIFO and counter. */ bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO | WRITE); /* Enable FIFOs. */ - bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO | WRITE); + bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); /* Turn off ENREQINIT for now. */ bus_space_write_1(iot, ioh, SIMODE1, @@ -2006,11 +2014,6 @@ aic_dataout_pio(sc, p, n) } phasechange: - /* Stop the FIFO data path. */ - bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); - while ((bus_space_read_1(iot, ioh, SXFRCTL0) & SCSIEN) != 0) - ; - if ((dmastat & INTSTAT) != 0) { /* Some sort of phase change. */ int amount; @@ -2020,8 +2023,9 @@ phasechange: (bus_space_read_1(iot, ioh, SSTAT2) & 15); if (amount > 0) { out -= amount; - bus_space_write_1(iot, ioh, SXFRCTL0, - CHEN | CLRSTCNT | CLRCH); + bus_space_write_1(iot, ioh, DMACNTRL0, + RSTFIFO | WRITE); + bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH); AIC_MISC(("+%d ", amount)); } } @@ -2030,6 +2034,10 @@ phasechange: bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); + /* Stop the FIFO data path. */ + bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); + bus_space_write_1(iot, ioh, DMACNTRL0, 0); + return out; } @@ -2052,11 +2060,14 @@ aic_datain_pio(sc, p, n) int in = 0; #define DINAMOUNT 128 /* Full FIFO */ + AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), + bus_space_read_1(iot, ioh, SSTAT2))); + /* Clear host FIFO and counter. */ bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); /* Enable FIFOs. */ - bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO); + bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); /* Turn off ENREQINIT for now. */ bus_space_write_1(iot, ioh, SIMODE1, @@ -2145,15 +2156,14 @@ aic_datain_pio(sc, p, n) } phasechange: - /* Stop the FIFO data path. */ - bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); - while ((bus_space_read_1(iot, ioh, SXFRCTL0) & SCSIEN) != 0) - ; - /* Turn on ENREQINIT again. */ bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); + /* Stop the FIFO data path. */ + bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); + bus_space_write_1(iot, ioh, DMACNTRL0, 0); + return in; } @@ -2417,6 +2427,10 @@ loop: case AIC_DISCONNECT: AIC_ASSERT(sc->sc_nexus != NULL); acb = sc->sc_nexus; +#if 1 /* XXXX */ + acb->data_addr = sc->sc_dp; + acb->data_length = sc->sc_dleft; +#endif TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); sc->sc_nexus = NULL; goto sched; @@ -2463,7 +2477,7 @@ dophase: if ((aic_debug & AIC_SHOWMISC) != 0) { AIC_ASSERT(sc->sc_nexus != NULL); acb = sc->sc_nexus; - printf("cmd=0x%02x+%d ", + printf("cmd=0x%02x+%d ", acb->scsi_cmd.opcode, acb->scsi_cmd_length-1); } #endif @@ -2476,7 +2490,7 @@ dophase: case PH_DATAOUT: if (sc->sc_state != AIC_CONNECTED) break; - AIC_MISC(("dataout dleft=%d ", sc->sc_dleft)); + AIC_MISC(("dataout dleft=%d ", sc->sc_dleft)); n = aic_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); sc->sc_dp += n; sc->sc_dleft -= n; @@ -2486,7 +2500,7 @@ dophase: case PH_DATAIN: if (sc->sc_state != AIC_CONNECTED) break; - AIC_MISC(("datain ")); + AIC_MISC(("datain %d ", sc->sc_dleft)); n = aic_datain_pio(sc, sc->sc_dp, sc->sc_dleft); sc->sc_dp += n; sc->sc_dleft -= n; @@ -2498,15 +2512,10 @@ dophase: break; AIC_ASSERT(sc->sc_nexus != NULL); acb = sc->sc_nexus; - /* XXXX Don't clear FIFO. Wait for byte to come in. */ bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); - bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); acb->target_stat = bus_space_read_1(iot, ioh, SCSIDAT); bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); - bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); - while ((bus_space_read_1(iot, ioh, SXFRCTL0) & SCSIEN) != 0) - ; - AIC_MISC(("target_stat=0x%02x ", acb->target_stat)); + AIC_MISC(("target_stat=0x%02x ", acb->target_stat)); sc->sc_prevphase = PH_STAT; goto loop; } |