replace Adaptec AIC-6915 Starfire driver with the fully bus_dma(9)-able

driver from NetBSD

ok brad@ reyk@

additional testing Nick Nauwelaerts

7 files changed, 2679 insertions, 2457 deletions

diff --git a/sys/conf/files b/sys/conf/files
index 4969b16c42e..20cc159acbc 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -1,4 +1,4 @@
-#	$OpenBSD: files,v 1.391 2006/12/02 15:55:18 miod Exp $
+#	$OpenBSD: files,v 1.392 2006/12/06 20:07:52 martin Exp $
 #	$NetBSD: files,v 1.87 1996/05/19 17:17:50 jonathan Exp $
 
 #	@(#)files.newconf	7.5 (Berkeley) 5/10/93
@@ -378,6 +378,10 @@ file	dev/ic/acx100.c			acx
 device	pgt: ether, ifnet, ifmedia, firmload, wlan
 file	dev/ic/pgt.c			pgt
 
+# Adaptec AIC-6915 Ethernet interface
+device sf: ether, ifnet, ifmedia, mii
+file	dev/ic/aic6915.c		sf
+
 # Marvell Libertas Open
 device	malo: ether, ifnet, ifmedia, firmload, wlan
 file	dev/ic/malo.c			malo
diff --git a/sys/dev/ic/aic6915.c b/sys/dev/ic/aic6915.c
new file mode 100644
index 00000000000..9ed8b7a2e0a
--- /dev/null
+++ b/sys/dev/ic/aic6915.c
@@ -0,0 +1,1537 @@
+/*	$OpenBSD: aic6915.c,v 1.1 2006/12/06 20:07:52 martin Exp $	*/
+/*	$NetBSD: aic6915.c,v 1.15 2005/12/24 20:27:29 perry Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Device driver for the Adaptec AIC-6915 (``Starfire'')
+ * 10/100 Ethernet controller.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/timeout.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/ioctl.h>
+#include <sys/errno.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <net/if_media.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/mii/miivar.h>
+
+#include <dev/ic/aic6915.h>
+
+void	sf_start(struct ifnet *);
+void	sf_watchdog(struct ifnet *);
+int	sf_ioctl(struct ifnet *, u_long, caddr_t);
+int	sf_init(struct ifnet *);
+void	sf_stop(struct ifnet *, int);
+
+void	sf_shutdown(void *);
+
+void	sf_txintr(struct sf_softc *);
+void	sf_rxintr(struct sf_softc *);
+void	sf_stats_update(struct sf_softc *);
+
+void	sf_reset(struct sf_softc *);
+void	sf_macreset(struct sf_softc *);
+void	sf_rxdrain(struct sf_softc *);
+int	sf_add_rxbuf(struct sf_softc *, int);
+uint8_t	sf_read_eeprom(struct sf_softc *, int);
+void	sf_set_filter(struct sf_softc *);
+
+int	sf_mii_read(struct device *, int, int);
+void	sf_mii_write(struct device *, int, int, int);
+void	sf_mii_statchg(struct device *);
+
+void	sf_tick(void *);
+
+int	sf_mediachange(struct ifnet *);
+void	sf_mediastatus(struct ifnet *, struct ifmediareq *);
+
+uint32_t sf_reg_read(struct sf_softc *, bus_addr_t);
+void	sf_reg_write(struct sf_softc *, bus_addr_t , uint32_t);
+
+void	sf_set_filter_perfect(struct sf_softc *, int , uint8_t *);
+void	sf_set_filter_hash(struct sf_softc *, uint8_t *);
+
+struct cfdriver sf_cd = {
+	NULL, "sf", DV_IFNET
+};
+
+#define	sf_funcreg_read(sc, reg)					\
+	bus_space_read_4((sc)->sc_st, (sc)->sc_sh_func, (reg))
+#define	sf_funcreg_write(sc, reg, val)					\
+	bus_space_write_4((sc)->sc_st, (sc)->sc_sh_func, (reg), (val))
+
+uint32_t
+sf_reg_read(struct sf_softc *sc, bus_addr_t reg)
+{
+
+	if (__predict_false(sc->sc_iomapped)) {
+		bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoAccess,
+		    reg);
+		return (bus_space_read_4(sc->sc_st, sc->sc_sh,
+		    SF_IndirectIoDataPort));
+	}
+
+	return (bus_space_read_4(sc->sc_st, sc->sc_sh, reg));
+}
+
+void
+sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val)
+{
+
+	if (__predict_false(sc->sc_iomapped)) {
+		bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoAccess,
+		    reg);
+		bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoDataPort,
+		    val);
+		return;
+	}
+
+	bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);
+}
+
+#define	sf_genreg_read(sc, reg)						\
+	sf_reg_read((sc), (reg) + SF_GENREG_OFFSET)
+#define	sf_genreg_write(sc, reg, val)					\
+	sf_reg_write((sc), (reg) + SF_GENREG_OFFSET, (val))
+
+/*
+ * sf_attach:
+ *
+ *	Attach a Starfire interface to the system.
+ */
+void
+sf_attach(struct sf_softc *sc)
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	int i, rseg, error;
+	bus_dma_segment_t seg;
+	u_int8_t enaddr[ETHER_ADDR_LEN];
+
+	timeout_set(&sc->sc_mii_timeout, sf_tick, sc);
+
+	/*
+	 * If we're I/O mapped, the functional register handle is
+	 * the same as the base handle.  If we're memory mapped,
+	 * carve off a chunk of the register space for the functional
+	 * registers, to save on arithmetic later.
+	 */
+	if (sc->sc_iomapped)
+		sc->sc_sh_func = sc->sc_sh;
+	else {
+		if ((error = bus_space_subregion(sc->sc_st, sc->sc_sh,
+		    SF_GENREG_OFFSET, SF_FUNCREG_SIZE, &sc->sc_sh_func)) != 0) {
+			printf("%s: unable to sub-region functional "
+			    "registers, error = %d\n", sc->sc_dev.dv_xname,
+			    error);
+			return;
+		}
+	}
+
+	/*
+	 * Initialize the transmit threshold for this interface.  The
+	 * manual describes the default as 4 * 16 bytes.  We start out
+	 * at 10 * 16 bytes, to avoid a bunch of initial underruns on
+	 * several platforms.
+	 */
+	sc->sc_txthresh = 10;
+
+	/*
+	 * Allocate the control data structures, and create and load the
+	 * DMA map for it.
+	 */
+	if ((error = bus_dmamem_alloc(sc->sc_dmat,
+	    sizeof(struct sf_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
+	    BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to allocate control data, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		goto fail_0;
+	}
+
+	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
+	    sizeof(struct sf_control_data), (caddr_t *)&sc->sc_control_data,
+	    BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
+		printf("%s: unable to map control data, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		goto fail_1;
+	}
+
+	if ((error = bus_dmamap_create(sc->sc_dmat,
+	    sizeof(struct sf_control_data), 1,
+	    sizeof(struct sf_control_data), 0, BUS_DMA_NOWAIT,
+	    &sc->sc_cddmamap)) != 0) {
+		printf("%s: unable to create control data DMA map, "
+		    "error = %d\n", sc->sc_dev.dv_xname, error);
+		goto fail_2;
+	}
+
+	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
+	    sc->sc_control_data, sizeof(struct sf_control_data), NULL,
+	    BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to load control data DMA map, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		goto fail_3;
+	}
+
+	/*
+	 * Create the transmit buffer DMA maps.
+	 */
+	for (i = 0; i < SF_NTXDESC; i++) {
+		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
+		    SF_NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
+		    &sc->sc_txsoft[i].ds_dmamap)) != 0) {
+			printf("%s: unable to create tx DMA map %d, "
+			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
+			goto fail_4;
+		}
+	}
+
+	/*
+	 * Create the receive buffer DMA maps.
+	 */
+	for (i = 0; i < SF_NRXDESC; i++) {
+		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
+		    MCLBYTES, 0, BUS_DMA_NOWAIT,
+		    &sc->sc_rxsoft[i].ds_dmamap)) != 0) {
+			printf("%s: unable to create rx DMA map %d, "
+			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
+			goto fail_5;
+		}
+	}
+
+	/*
+	 * Reset the chip to a known state.
+	 */
+	sf_reset(sc);
+
+	/*
+	 * Read the Ethernet address from the EEPROM.
+	 */
+	for (i = 0; i < ETHER_ADDR_LEN; i++)
+		enaddr[i] = sf_read_eeprom(sc, (15 + (ETHER_ADDR_LEN - 1)) - i);
+
+	printf(", address %s\n", ether_sprintf(enaddr));
+
+#ifdef DEBUG
+	if (sf_funcreg_read(sc, SF_PciDeviceConfig) & PDC_System64)
+		printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname);
+#endif
+
+	/*
+	 * Initialize our media structures and probe the MII.
+	 */
+	sc->sc_mii.mii_ifp = ifp;
+	sc->sc_mii.mii_readreg = sf_mii_read;
+	sc->sc_mii.mii_writereg = sf_mii_write;
+	sc->sc_mii.mii_statchg = sf_mii_statchg;
+	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, sf_mediachange,
+	    sf_mediastatus);
+	mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
+	    MII_OFFSET_ANY, 0);
+	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
+		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
+		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
+	} else
+		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
+	bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
+	bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
+	ifp = &sc->sc_arpcom.ac_if;
+	ifp->if_softc = sc;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = sf_ioctl;
+	ifp->if_start = sf_start;
+	ifp->if_watchdog = sf_watchdog;
+	ifp->if_init = sf_init;
+#ifdef NetBSD
+	ifp->if_stop = sf_stop;
+#endif
+	IFQ_SET_READY(&ifp->if_snd);
+
+	/*
+	 * Attach the interface.
+	 */
+	if_attach(ifp);
+	ether_ifattach(ifp);
+	/*
+	 * Make sure the interface is shutdown during reboot.
+	 */
+	sc->sc_sdhook = shutdownhook_establish(sf_shutdown, sc);
+	if (sc->sc_sdhook == NULL)
+		printf("%s: WARNING: unable to establish shutdown hook\n",
+		    sc->sc_dev.dv_xname);
+	 return;
+
+	/*
+	 * Free any resources we've allocated during the failed attach
+	 * attempt.  Do this in reverse order an fall through.
+	 */
+ fail_5:
+	for (i = 0; i < SF_NRXDESC; i++) {
+		if (sc->sc_rxsoft[i].ds_dmamap != NULL)
+			bus_dmamap_destroy(sc->sc_dmat,
+			    sc->sc_rxsoft[i].ds_dmamap);
+	}
+ fail_4:
+	for (i = 0; i < SF_NTXDESC; i++) {
+		if (sc->sc_txsoft[i].ds_dmamap != NULL)
+			bus_dmamap_destroy(sc->sc_dmat,
+			    sc->sc_txsoft[i].ds_dmamap);
+	}
+	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
+ fail_3:
+	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
+ fail_2:
+	bus_dmamem_unmap(sc->sc_dmat, (caddr_t) sc->sc_control_data,
+	    sizeof(struct sf_control_data));
+ fail_1:
+	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
+ fail_0:
+	return;
+}
+
+/*
+ * sf_shutdown:
+ *
+ *	Shutdown hook -- make sure the interface is stopped at reboot.
+ */
+void
+sf_shutdown(void *arg)
+{
+	struct sf_softc *sc = arg;
+
+	sf_stop(&sc->sc_arpcom.ac_if, 1);
+}
+
+/*
+ * sf_start:		[ifnet interface function]
+ *
+ *	Start packet transmission on the interface.
+ */
+void
+sf_start(struct ifnet *ifp)
+{
+	struct sf_softc *sc = ifp->if_softc;
+	struct mbuf *m0, *m;
+	struct sf_txdesc0 *txd;
+	struct sf_descsoft *ds;
+	bus_dmamap_t dmamap;
+	int error, producer, last = -1, opending, seg;
+
+	/*
+	 * Remember the previous number of pending transmits.
+	 */
+	opending = sc->sc_txpending;
+
+	/*
+	 * Find out where we're sitting.
+	 */
+	producer = SF_TXDINDEX_TO_HOST(
+	    TDQPI_HiPrTxProducerIndex_get(
+	    sf_funcreg_read(sc, SF_TxDescQueueProducerIndex)));
+
+	/*
+	 * Loop through the send queue, setting up transmit descriptors
+	 * until we drain the queue, or use up all available transmit
+	 * descriptors.  Leave a blank one at the end for sanity's sake.
+	 */
+	while (sc->sc_txpending < (SF_NTXDESC - 1)) {
+		/*
+		 * Grab a packet off the queue.
+		 */
+		IFQ_POLL(&ifp->if_snd, m0);
+		if (m0 == NULL)
+			break;
+		m = NULL;
+
+		/*
+		 * Get the transmit descriptor.
+		 */
+		txd = &sc->sc_txdescs[producer];
+		ds = &sc->sc_txsoft[producer];
+		dmamap = ds->ds_dmamap;
+
+		/*
+		 * Load the DMA map.  If this fails, the packet either
+		 * didn't fit in the allotted number of frags, or we were
+		 * short on resources.  In this case, we'll copy and try
+		 * again.
+		 */
+		if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
+		    BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) {
+			MGETHDR(m, M_DONTWAIT, MT_DATA);
+			if (m == NULL) {
+				printf("%s: unable to allocate Tx mbuf\n",
+				    sc->sc_dev.dv_xname);
+				break;
+			}
+			if (m0->m_pkthdr.len > MHLEN) {
+				MCLGET(m, M_DONTWAIT);
+				if ((m->m_flags & M_EXT) == 0) {
+					printf("%s: unable to allocate Tx "
+					    "cluster\n", sc->sc_dev.dv_xname);
+					m_freem(m);
+					break;
+				}
+			}
+			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
+			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
+			error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
+			    m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
+			if (error) {
+				printf("%s: unable to load Tx buffer, "
+				    "error = %d\n", sc->sc_dev.dv_xname, error);
+				break;
+			}
+		}
+
+		/*
+		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
+		 */
+		IFQ_DEQUEUE(&ifp->if_snd, m0);
+		if (m != NULL) {
+			m_freem(m0);
+			m0 = m;
+		}
+
+		/* Initialize the descriptor. */
+		txd->td_word0 =
+		    htole32(TD_W0_ID | TD_W0_CRCEN | m0->m_pkthdr.len);
+		if (producer == (SF_NTXDESC - 1))
+			txd->td_word0 |= TD_W0_END;
+		txd->td_word1 = htole32(dmamap->dm_nsegs);
+		for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
+			txd->td_frags[seg].fr_addr =
+			    htole32(dmamap->dm_segs[seg].ds_addr);
+			txd->td_frags[seg].fr_len =
+			    htole32(dmamap->dm_segs[seg].ds_len);
+		}
+
+		/* Sync the descriptor and the DMA map. */
+		SF_CDTXDSYNC(sc, producer, BUS_DMASYNC_PREWRITE);
+		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
+		    BUS_DMASYNC_PREWRITE);
+
+		/*
+		 * Store a pointer to the packet so we can free it later.
+		 */
+		ds->ds_mbuf = m0;
+
+		/* Advance the Tx pointer. */
+		sc->sc_txpending++;
+		last = producer;
+		producer = SF_NEXTTX(producer);
+
+#if NBPFILTER > 0
+		/*
+		 * Pass the packet to any BPF listeners.
+		 */
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT);
+#endif
+	}
+
+	if (sc->sc_txpending == (SF_NTXDESC - 1)) {
+		/* No more slots left; notify upper layer. */
+		ifp->if_flags |= IFF_OACTIVE;
+	}
+
+	if (sc->sc_txpending != opending) {
+		KASSERT(last != -1);
+		/*
+		 * We enqueued packets.  Cause a transmit interrupt to
+		 * happen on the last packet we enqueued, and give the
+		 * new descriptors to the chip by writing the new
+		 * producer index.
+		 */
+		sc->sc_txdescs[last].td_word0 |= TD_W0_INTR;
+		SF_CDTXDSYNC(sc, last, BUS_DMASYNC_PREWRITE);
+
+		sf_funcreg_write(sc, SF_TxDescQueueProducerIndex,
+		    TDQPI_HiPrTxProducerIndex(SF_TXDINDEX_TO_CHIP(producer)));
+
+		/* Set a watchdog timer in case the chip flakes out. */
+		ifp->if_timer = 5;
+	}
+}
+
+/*
+ * sf_watchdog:		[ifnet interface function]
+ *
+ *	Watchdog timer handler.
+ */
+void
+sf_watchdog(struct ifnet *ifp)
+{
+	struct sf_softc *sc = ifp->if_softc;
+
+	printf("%s: device timeout\n", sc->sc_dev.dv_xname);
+	ifp->if_oerrors++;
+
+	(void) sf_init(ifp);
+
+	/* Try to get more packets going. */
+	sf_start(ifp);
+}
+
+/*
+ * sf_ioctl:		[ifnet interface function]
+ *
+ *	Handle control requests from the operator.
+ */
+int
+sf_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
+{
+	struct sf_softc *sc = (struct sf_softc *)ifp->if_softc;
+	struct ifaddr *ifa;
+	struct ifreq *ifr = (struct ifreq *) data;
+	int s, error = 1;
+
+	s = splnet();
+	if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
+		splx(s);
+		return (error);
+	}
+
+	switch (cmd) {
+	case SIOCSIFADDR:
+		ifa = (struct ifaddr *)data;
+		ifp->if_flags |= IFF_UP;
+#ifdef INET
+		if (ifa->ifa_addr->sa_family == AF_INET)
+			arp_ifinit(&sc->sc_arpcom, ifa);
+#endif
+		/* FALLTHROUGH */
+	case SIOCSIFFLAGS:
+		if (ifp->if_flags & IFF_UP) {
+			if (ifp->if_flags & IFF_RUNNING)
+				sf_set_filter(sc);
+			else
+				sf_init(ifp);
+		} else {
+			if (ifp->if_flags & IFF_RUNNING)
+				sf_stop(ifp, 1);
+		}
+		break;
+
+	case SIOCSIFMTU:
+		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
+			error = EINVAL;
+		else if (ifp->if_mtu != ifr->ifr_mtu)
+			ifp->if_mtu = ifr->ifr_mtu;
+		break;
+
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		ifr = (struct ifreq *)data;
+		error = (cmd == SIOCADDMULTI) ?
+			ether_addmulti(ifr, &sc->sc_arpcom) :
+			ether_delmulti(ifr, &sc->sc_arpcom);
+
+		if (error == ENETRESET) {
+			if (ifp->if_flags & IFF_RUNNING)
+				sf_set_filter(sc);
+			error = 0;
+		}
+		break;
+
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
+		break;
+
+	default:
+		error = ENOTTY;
+	}
+
+	if (error == ENETRESET) {
+		if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
+		    (IFF_UP | IFF_RUNNING))
+			/* Try to get more packets going. */
+			sf_start(ifp);
+		error = 0;
+	}
+
+	splx(s);
+	return (error);
+}
+
+/*
+ * sf_intr:
+ *
+ *	Interrupt service routine.
+ */
+int
+sf_intr(void *arg)
+{
+	struct sf_softc *sc = arg;
+	uint32_t isr;
+	int handled = 0, wantinit = 0;
+
+	for (;;) {
+		/* Reading clears all interrupts we're interested in. */
+		isr = sf_funcreg_read(sc, SF_InterruptStatus);
+		if ((isr & IS_PCIPadInt) == 0)
+			break;
+
+		handled = 1;
+
+		/* Handle receive interrupts. */
+		if (isr & IS_RxQ1DoneInt)
+			sf_rxintr(sc);
+
+		/* Handle transmit completion interrupts. */
+		if (isr & (IS_TxDmaDoneInt|IS_TxQueueDoneInt))
+			sf_txintr(sc);
+
+		/* Handle abnormal interrupts. */
+		if (isr & IS_AbnormalInterrupt) {
+			/* Statistics. */
+			if (isr & IS_StatisticWrapInt)
+				sf_stats_update(sc);
+
+			/* DMA errors. */
+			if (isr & IS_DmaErrInt) {
+				wantinit = 1;
+				printf("%s: WARNING: DMA error\n",
+				    sc->sc_dev.dv_xname);
+			}
+
+			/* Transmit FIFO underruns. */
+			if (isr & IS_TxDataLowInt) {
+				if (sc->sc_txthresh < 0xff)
+					sc->sc_txthresh++;
+#ifdef DEBUG
+				printf("%s: transmit FIFO underrun, new "
+				    "threshold: %d bytes\n",
+				    sc->sc_dev.dv_xname,
+				    sc->sc_txthresh * 16);
+#endif
+				sf_funcreg_write(sc, SF_TransmitFrameCSR,
+				    sc->sc_TransmitFrameCSR |
+				    TFCSR_TransmitThreshold(sc->sc_txthresh));
+				sf_funcreg_write(sc, SF_TxDescQueueCtrl,
+				    sc->sc_TxDescQueueCtrl |
+				    TDQC_TxHighPriorityFifoThreshold(
+							sc->sc_txthresh));
+			}
+		}
+	}
+
+	if (handled) {
+		/* Reset the interface, if necessary. */
+		if (wantinit)
+			sf_init(&sc->sc_arpcom.ac_if);
+
+		/* Try and get more packets going. */
+		sf_start(&sc->sc_arpcom.ac_if);
+	}
+
+	return (handled);
+}
+
+/*
+ * sf_txintr:
+ *
+ *	Helper -- handle transmit completion interrupts.
+ */
+void
+sf_txintr(struct sf_softc *sc)
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	struct sf_descsoft *ds;
+	uint32_t cqci, tcd;
+	int consumer, producer, txidx;
+
+ try_again:
+	cqci = sf_funcreg_read(sc, SF_CompletionQueueConsumerIndex);
+
+	consumer = CQCI_TxCompletionConsumerIndex_get(cqci);
+	producer = CQPI_TxCompletionProducerIndex_get(
+	    sf_funcreg_read(sc, SF_CompletionQueueProducerIndex));
+
+	if (consumer == producer)
+		return;
+
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	while (consumer != producer) {
+		SF_CDTXCSYNC(sc, consumer, BUS_DMASYNC_POSTREAD);
+		tcd = letoh32(sc->sc_txcomp[consumer].tcd_word0);
+
+		txidx = SF_TCD_INDEX_TO_HOST(TCD_INDEX(tcd));
+#ifdef DIAGNOSTIC
+		if ((tcd & TCD_PR) == 0)
+			printf("%s: Tx queue mismatch, index %d\n",
+			    sc->sc_dev.dv_xname, txidx);
+#endif
+		/*
+		 * NOTE: stats are updated later.  We're just
+		 * releasing packets that have been DMA'd to
+		 * the chip.
+		 */
+		ds = &sc->sc_txsoft[txidx];
+		SF_CDTXDSYNC(sc, txidx, BUS_DMASYNC_POSTWRITE);
+		bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap,
+		    0, ds->ds_dmamap->dm_mapsize,
+		    BUS_DMASYNC_POSTWRITE);
+		m_freem(ds->ds_mbuf);
+		ds->ds_mbuf = NULL;
+
+		consumer = SF_NEXTTCD(consumer);
+		sc->sc_txpending--;
+	}
+
+	/* XXXJRT -- should be KDASSERT() */
+	KASSERT(sc->sc_txpending >= 0);
+
+	/* If all packets are done, cancel the watchdog timer. */
+	if (sc->sc_txpending == 0)
+		ifp->if_timer = 0;
+
+	/* Update the consumer index. */
+	sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex,
+	    (cqci & ~CQCI_TxCompletionConsumerIndex(0x7ff)) |
+	     CQCI_TxCompletionConsumerIndex(consumer));
+
+	/* Double check for new completions. */
+	goto try_again;
+}
+
+/*
+ * sf_rxintr:
+ *
+ *	Helper -- handle receive interrupts.
+ */
+void
+sf_rxintr(struct sf_softc *sc)
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	struct sf_descsoft *ds;
+	struct sf_rcd_full *rcd;
+	struct mbuf *m;
+	uint32_t cqci, word0;
+	int consumer, producer, bufproducer, rxidx, len;
+
+ try_again:
+	cqci = sf_funcreg_read(sc, SF_CompletionQueueConsumerIndex);
+
+	consumer = CQCI_RxCompletionQ1ConsumerIndex_get(cqci);
+	producer = CQPI_RxCompletionQ1ProducerIndex_get(
+	    sf_funcreg_read(sc, SF_CompletionQueueProducerIndex));
+	bufproducer = RXQ1P_RxDescQ1Producer_get(
+	    sf_funcreg_read(sc, SF_RxDescQueue1Ptrs));
+
+	if (consumer == producer)
+		return;
+
+	while (consumer != producer) {
+		rcd = &sc->sc_rxcomp[consumer];
+		SF_CDRXCSYNC(sc, consumer,
+		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+		SF_CDRXCSYNC(sc, consumer,
+		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+
+		word0 = letoh32(rcd->rcd_word0);
+		rxidx = RCD_W0_EndIndex(word0);
+
+		ds = &sc->sc_rxsoft[rxidx];
+
+		consumer = SF_NEXTRCD(consumer);
+		bufproducer = SF_NEXTRX(bufproducer);
+
+		if ((word0 & RCD_W0_OK) == 0) {
+			SF_INIT_RXDESC(sc, rxidx);
+			continue;
+		}
+
+		bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
+		    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
+
+		/*
+		 * No errors; receive the packet.  Note that we have
+		 * configured the Starfire to NOT transfer the CRC
+		 * with the packet.
+		 */
+		len = RCD_W0_Length(word0);
+
+#ifdef __NO_STRICT_ALIGNMENT
+		/*
+		 * Allocate a new mbuf cluster.  If that fails, we are
+		 * out of memory, and must drop the packet and recycle
+		 * the buffer that's already attached to this descriptor.
+		 */
+		m = ds->ds_mbuf;
+		if (sf_add_rxbuf(sc, rxidx) != 0) {
+			ifp->if_ierrors++;
+			SF_INIT_RXDESC(sc, rxidx);
+			bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
+			    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
+			continue;
+		}
+#else
+		/*
+		 * The Starfire's receive buffer must be 4-byte aligned.
+		 * But this means that the data after the Ethernet header
+		 * is misaligned.  We must allocate a new buffer and
+		 * copy the data, shifted forward 2 bytes.
+		 */
+		MGETHDR(m, M_DONTWAIT, MT_DATA);
+		if (m == NULL) {
+ dropit:
+			ifp->if_ierrors++;
+			SF_INIT_RXDESC(sc, rxidx);
+			bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
+			    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
+			continue;
+		}
+		if (len > (MHLEN - 2)) {
+			MCLGET(m, M_DONTWAIT);
+			if ((m->m_flags & M_EXT) == 0) {
+				m_freem(m);
+				goto dropit;
+			}
+		}
+		m->m_data += 2;
+
+		/*
+		 * Note that we use cluster for incoming frames, so the
+		 * buffer is virtually contiguous.
+		 */
+		memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), len);
+
+		/* Allow the receive descriptor to continue using its mbuf. */
+		SF_INIT_RXDESC(sc, rxidx);
+		bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
+		    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
+#endif /* __NO_STRICT_ALIGNMENT */
+
+		m->m_pkthdr.rcvif = ifp;
+		m->m_pkthdr.len = m->m_len = len;
+
+#if NBPFILTER > 0
+		/*
+		 * Pass this up to any BPF listeners.
+		 */
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
+#endif /* NBPFILTER > 0 */
+
+		/* Pass it on. */
+		ether_input_mbuf(ifp, m);
+		ifp->if_ipackets++;
+	}
+
+	/* Update the chip's pointers. */
+	sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex,
+	    (cqci & ~CQCI_RxCompletionQ1ConsumerIndex(0x7ff)) |
+	     CQCI_RxCompletionQ1ConsumerIndex(consumer));
+	sf_funcreg_write(sc, SF_RxDescQueue1Ptrs,
+	    RXQ1P_RxDescQ1Producer(bufproducer));
+
+	/* Double-check for any new completions. */
+	goto try_again;
+}
+
+/*
+ * sf_tick:
+ *
+ *	One second timer, used to tick the MII and update stats.
+ */
+void
+sf_tick(void *arg)
+{
+	struct sf_softc *sc = arg;
+	int s;
+
+	s = splnet();
+	mii_tick(&sc->sc_mii);
+	sf_stats_update(sc);
+	splx(s);
+
+	timeout_add(&sc->sc_mii_timeout, hz);
+}
+
+/*
+ * sf_stats_update:
+ *
+ *	Read the statitistics counters.
+ */
+void
+sf_stats_update(struct sf_softc *sc)
+{
+	struct sf_stats stats;
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	uint32_t *p;
+	u_int i;
+
+	p = &stats.TransmitOKFrames;
+	for (i = 0; i < (sizeof(stats) / sizeof(uint32_t)); i++) {
+		*p++ = sf_genreg_read(sc,
+		    SF_STATS_BASE + (i * sizeof(uint32_t)));
+		sf_genreg_write(sc, SF_STATS_BASE + (i * sizeof(uint32_t)), 0);
+	}
+
+	ifp->if_opackets += stats.TransmitOKFrames;
+
+	ifp->if_collisions += stats.SingleCollisionFrames +
+	    stats.MultipleCollisionFrames;
+
+	ifp->if_oerrors += stats.TransmitAbortDueToExcessiveCollisions +
+	    stats.TransmitAbortDueToExcessingDeferral +
+	    stats.FramesLostDueToInternalTransmitErrors;
+
+	ifp->if_ipackets += stats.ReceiveOKFrames;
+
+	ifp->if_ierrors += stats.ReceiveCRCErrors + stats.AlignmentErrors +
+	    stats.ReceiveFramesTooLong + stats.ReceiveFramesTooShort +
+	    stats.ReceiveFramesJabbersError +
+	    stats.FramesLostDueToInternalReceiveErrors;
+}
+
+/*
+ * sf_reset:
+ *
+ *	Perform a soft reset on the Starfire.
+ */
+void
+sf_reset(struct sf_softc *sc)
+{
+	int i;
+
+	sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 0);
+
+	sf_macreset(sc);
+
+	sf_funcreg_write(sc, SF_PciDeviceConfig, PDC_SoftReset);
+	for (i = 0; i < 1000; i++) {
+		delay(10);
+		if ((sf_funcreg_read(sc, SF_PciDeviceConfig) &
+		     PDC_SoftReset) == 0)
+			break;
+	}
+
+	if (i == 1000) {
+		printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname);
+		sf_funcreg_write(sc, SF_PciDeviceConfig, 0);
+	}
+
+	delay(1000);
+}
+
+/*
+ * sf_macreset:
+ *
+ *	Reset the MAC portion of the Starfire.
+ */
+void
+sf_macreset(struct sf_softc *sc)
+{
+
+	sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1 | MC1_SoftRst);
+	delay(1000);
+	sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1);
+}
+
+/*
+ * sf_init:		[ifnet interface function]
+ *
+ *	Initialize the interface.  Must be called at splnet().
+ */
+int
+sf_init(struct ifnet *ifp)
+{
+	struct sf_softc *sc = ifp->if_softc;
+	struct sf_descsoft *ds;
+	int error = 0;
+	u_int i;
+
+	/*
+	 * Cancel any pending I/O.
+	 */
+	sf_stop(ifp, 0);
+
+	/*
+	 * Reset the Starfire to a known state.
+	 */
+	sf_reset(sc);
+
+	/* Clear the stat counters. */
+	for (i = 0; i < sizeof(struct sf_stats); i += sizeof(uint32_t))
+		sf_genreg_write(sc, SF_STATS_BASE + i, 0);
+
+	/*
+	 * Initialize the transmit descriptor ring.
+	 */
+	memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
+	sf_funcreg_write(sc, SF_TxDescQueueHighAddr, 0);
+	sf_funcreg_write(sc, SF_HiPrTxDescQueueBaseAddr, SF_CDTXDADDR(sc, 0));
+	sf_funcreg_write(sc, SF_LoPrTxDescQueueBaseAddr, 0);
+
+	/*
+	 * Initialize the transmit completion ring.
+	 */
+	for (i = 0; i < SF_NTCD; i++) {
+		sc->sc_txcomp[i].tcd_word0 = TCD_DMA_ID;
+		SF_CDTXCSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+	}
+	sf_funcreg_write(sc, SF_CompletionQueueHighAddr, 0);
+	sf_funcreg_write(sc, SF_TxCompletionQueueCtrl, SF_CDTXCADDR(sc, 0));
+
+	/*
+	 * Initialize the receive descriptor ring.
+	 */
+	for (i = 0; i < SF_NRXDESC; i++) {
+		ds = &sc->sc_rxsoft[i];
+		if (ds->ds_mbuf == NULL) {
+			if ((error = sf_add_rxbuf(sc, i)) != 0) {
+				printf("%s: unable to allocate or map rx "
+				    "buffer %d, error = %d\n",
+				    sc->sc_dev.dv_xname, i, error);
+				/*
+				 * XXX Should attempt to run with fewer receive
+				 * XXX buffers instead of just failing.
+				 */
+				sf_rxdrain(sc);
+				goto out;
+			}
+		} else
+			SF_INIT_RXDESC(sc, i);
+	}
+	sf_funcreg_write(sc, SF_RxDescQueueHighAddress, 0);
+	sf_funcreg_write(sc, SF_RxDescQueue1LowAddress, SF_CDRXDADDR(sc, 0));
+	sf_funcreg_write(sc, SF_RxDescQueue2LowAddress, 0);
+
+	/*
+	 * Initialize the receive completion ring.
+	 */
+	for (i = 0; i < SF_NRCD; i++) {
+		sc->sc_rxcomp[i].rcd_word0 = RCD_W0_ID;
+		sc->sc_rxcomp[i].rcd_word1 = 0;
+		sc->sc_rxcomp[i].rcd_word2 = 0;
+		sc->sc_rxcomp[i].rcd_timestamp = 0;
+		SF_CDRXCSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+	}
+	sf_funcreg_write(sc, SF_RxCompletionQueue1Ctrl, SF_CDRXCADDR(sc, 0) |
+	    RCQ1C_RxCompletionQ1Type(3));
+	sf_funcreg_write(sc, SF_RxCompletionQueue2Ctrl, 0);
+
+	/*
+	 * Initialize the Tx CSR.
+	 */
+	sc->sc_TransmitFrameCSR = 0;
+	sf_funcreg_write(sc, SF_TransmitFrameCSR,
+	    sc->sc_TransmitFrameCSR |
+	    TFCSR_TransmitThreshold(sc->sc_txthresh));
+
+	/*
+	 * Initialize the Tx descriptor control register.
+	 */
+	sc->sc_TxDescQueueCtrl = TDQC_SkipLength(0) |
+	    TDQC_TxDmaBurstSize(4) |	/* default */
+	    TDQC_MinFrameSpacing(3) |	/* 128 bytes */
+	    TDQC_TxDescType(0);
+	sf_funcreg_write(sc, SF_TxDescQueueCtrl,
+	    sc->sc_TxDescQueueCtrl |
+	    TDQC_TxHighPriorityFifoThreshold(sc->sc_txthresh));
+
+	/*
+	 * Initialize the Rx descriptor control registers.
+	 */
+	sf_funcreg_write(sc, SF_RxDescQueue1Ctrl,
+	    RDQ1C_RxQ1BufferLength(MCLBYTES) |
+	    RDQ1C_RxDescSpacing(0));
+	sf_funcreg_write(sc, SF_RxDescQueue2Ctrl, 0);
+
+	/*
+	 * Initialize the Tx descriptor producer indices.
+	 */
+	sf_funcreg_write(sc, SF_TxDescQueueProducerIndex,
+	    TDQPI_HiPrTxProducerIndex(0) |
+	    TDQPI_LoPrTxProducerIndex(0));
+
+	/*
+	 * Initialize the Rx descriptor producer indices.
+	 */
+	sf_funcreg_write(sc, SF_RxDescQueue1Ptrs,
+	    RXQ1P_RxDescQ1Producer(SF_NRXDESC - 1));
+	sf_funcreg_write(sc, SF_RxDescQueue2Ptrs,
+	    RXQ2P_RxDescQ2Producer(0));
+
+	/*
+	 * Initialize the Tx and Rx completion queue consumer indices.
+	 */
+	sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex,
+	    CQCI_TxCompletionConsumerIndex(0) |
+	    CQCI_RxCompletionQ1ConsumerIndex(0));
+	sf_funcreg_write(sc, SF_RxHiPrCompletionPtrs, 0);
+
+	/*
+	 * Initialize the Rx DMA control register.
+	 */
+	sf_funcreg_write(sc, SF_RxDmaCtrl,
+	    RDC_RxHighPriorityThreshold(6) |	/* default */
+	    RDC_RxBurstSize(4));		/* default */
+
+	/*
+	 * Set the receive filter.
+	 */
+	sc->sc_RxAddressFilteringCtl = 0;
+	sf_set_filter(sc);
+
+	/*
+	 * Set MacConfig1.  When we set the media, MacConfig1 will
+	 * actually be written and the MAC part reset.
+	 */
+	sc->sc_MacConfig1 = MC1_PadEn;
+
+	/*
+	 * Set the media.
+	 */
+	mii_mediachg(&sc->sc_mii);
+
+	/*
+	 * Initialize the interrupt register.
+	 */
+	sc->sc_InterruptEn = IS_PCIPadInt | IS_RxQ1DoneInt |
+	    IS_TxQueueDoneInt | IS_TxDmaDoneInt | IS_DmaErrInt |
+	    IS_StatisticWrapInt;
+	sf_funcreg_write(sc, SF_InterruptEn, sc->sc_InterruptEn);
+
+	sf_funcreg_write(sc, SF_PciDeviceConfig, PDC_IntEnable |
+	    PDC_PCIMstDmaEn | (1 << PDC_FifoThreshold_SHIFT));
+
+	/*
+	 * Start the transmit and receive processes.
+	 */
+	sf_funcreg_write(sc, SF_GeneralEthernetCtrl,
+	    GEC_TxDmaEn|GEC_RxDmaEn|GEC_TransmitEn|GEC_ReceiveEn);
+
+	/* Start the on second clock. */
+	timeout_add(&sc->sc_mii_timeout, hz);
+
+	/*
+	 * Note that the interface is now running.
+	 */
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+ out:
+	if (error) {
+		ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+		ifp->if_timer = 0;
+		printf("%s: interface not running\n", sc->sc_dev.dv_xname);
+	}
+	return (error);
+}
+
+/*
+ * sf_rxdrain:
+ *
+ *	Drain the receive queue.
+ */
+void
+sf_rxdrain(struct sf_softc *sc)
+{
+	struct sf_descsoft *ds;
+	int i;
+
+	for (i = 0; i < SF_NRXDESC; i++) {
+		ds = &sc->sc_rxsoft[i];
+		if (ds->ds_mbuf != NULL) {
+			bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
+			m_freem(ds->ds_mbuf);
+			ds->ds_mbuf = NULL;
+		}
+	}
+}
+
+/*
+ * sf_stop:		[ifnet interface function]
+ *
+ *	Stop transmission on the interface.
+ */
+void
+sf_stop(struct ifnet *ifp, int disable)
+{
+	struct sf_softc *sc = ifp->if_softc;
+	struct sf_descsoft *ds;
+	int i;
+
+	/* Stop the one second clock. */
+	timeout_del(&sc->sc_mii_timeout);
+
+	/* Down the MII. */
+	mii_down(&sc->sc_mii);
+
+	/* Disable interrupts. */
+	sf_funcreg_write(sc, SF_InterruptEn, 0);
+
+	/* Stop the transmit and receive processes. */
+	sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 0);
+
+	/*
+	 * Release any queued transmit buffers.
+	 */
+	for (i = 0; i < SF_NTXDESC; i++) {
+		ds = &sc->sc_txsoft[i];
+		if (ds->ds_mbuf != NULL) {
+			bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
+			m_freem(ds->ds_mbuf);
+			ds->ds_mbuf = NULL;
+		}
+	}
+
+	if (disable)
+		sf_rxdrain(sc);
+
+	/*
+	 * Mark the interface down and cancel the watchdog timer.
+	 */
+	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+	ifp->if_timer = 0;
+}
+
+/*
+ * sf_read_eeprom:
+ *
+ *	Read from the Starfire EEPROM.
+ */
+uint8_t
+sf_read_eeprom(struct sf_softc *sc, int offset)
+{
+	uint32_t reg;
+
+	reg = sf_genreg_read(sc, SF_EEPROM_BASE + (offset & ~3));
+
+	return ((reg >> (8 * (offset & 3))) & 0xff);
+}
+
+/*
+ * sf_add_rxbuf:
+ *
+ *	Add a receive buffer to the indicated descriptor.
+ */
+int
+sf_add_rxbuf(struct sf_softc *sc, int idx)
+{
+	struct sf_descsoft *ds = &sc->sc_rxsoft[idx];
+	struct mbuf *m;
+	int error;
+
+	MGETHDR(m, M_DONTWAIT, MT_DATA);
+	if (m == NULL)
+		return (ENOBUFS);
+
+	MCLGET(m, M_DONTWAIT);
+	if ((m->m_flags & M_EXT) == 0) {
+		m_freem(m);
+		return (ENOBUFS);
+	}
+
+	if (ds->ds_mbuf != NULL)
+		bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
+
+	ds->ds_mbuf = m;
+
+	error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
+	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
+	    BUS_DMA_READ|BUS_DMA_NOWAIT);
+	if (error) {
+		printf("%s: can't load rx DMA map %d, error = %d\n",
+		    sc->sc_dev.dv_xname, idx, error);
+		panic("sf_add_rxbuf"); /* XXX */
+	}
+
+	bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
+	    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
+
+	SF_INIT_RXDESC(sc, idx);
+
+	return (0);
+}
+
+void
+sf_set_filter_perfect(struct sf_softc *sc, int slot, uint8_t *enaddr)
+{
+	uint32_t reg0, reg1, reg2;
+
+	reg0 = enaddr[5] | (enaddr[4] << 8);
+	reg1 = enaddr[3] | (enaddr[2] << 8);
+	reg2 = enaddr[1] | (enaddr[0] << 8);
+
+	sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 0, reg0);
+	sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 4, reg1);
+	sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 8, reg2);
+}
+
+void
+sf_set_filter_hash(struct sf_softc *sc, uint8_t *enaddr)
+{
+	uint32_t hash, slot, reg;
+
+	hash = ether_crc32_be(enaddr, ETHER_ADDR_LEN) >> 23;
+	slot = hash >> 4;
+
+	reg = sf_genreg_read(sc, SF_HASH_BASE + (slot * 0x10));
+	reg |= 1 << (hash & 0xf);
+	sf_genreg_write(sc, SF_HASH_BASE + (slot * 0x10), reg);
+}
+
+/*
+ * sf_set_filter:
+ *
+ *	Set the Starfire receive filter.
+ */
+void
+sf_set_filter(struct sf_softc *sc)
+{
+	struct arpcom *ac = &sc->sc_arpcom;
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	struct ether_multi *enm;
+	struct ether_multistep step;
+	int i;
+
+	/* Start by clearing the perfect and hash tables. */
+	for (i = 0; i < SF_PERFECT_SIZE; i += sizeof(uint32_t))
+		sf_genreg_write(sc, SF_PERFECT_BASE + i, 0);
+
+	for (i = 0; i < SF_HASH_SIZE; i += sizeof(uint32_t))
+		sf_genreg_write(sc, SF_HASH_BASE + i, 0);
+
+	/*
+	 * Clear the perfect and hash mode bits.
+	 */
+	sc->sc_RxAddressFilteringCtl &=
+	    ~(RAFC_PerfectFilteringMode(3) | RAFC_HashFilteringMode(3));
+
+	if (ifp->if_flags & IFF_BROADCAST)
+		sc->sc_RxAddressFilteringCtl |= RAFC_PassBroadcast;
+	else
+		sc->sc_RxAddressFilteringCtl &= ~RAFC_PassBroadcast;
+
+	if (ifp->if_flags & IFF_PROMISC) {
+		sc->sc_RxAddressFilteringCtl |= RAFC_PromiscuousMode;
+		goto allmulti;
+	} else
+		sc->sc_RxAddressFilteringCtl &= ~RAFC_PromiscuousMode;
+
+	/*
+	 * Set normal perfect filtering mode.
+	 */
+	sc->sc_RxAddressFilteringCtl |= RAFC_PerfectFilteringMode(1);
+
+	/*
+	 * First, write the station address to the perfect filter
+	 * table.
+	 */
+	sf_set_filter_perfect(sc, 0, LLADDR(ifp->if_sadl));
+
+	/*
+	 * Now set the hash bits for each multicast address in our
+	 * list.
+	 */
+	ETHER_FIRST_MULTI(step, ac, enm);
+	if (enm == NULL)
+		goto done;
+	while (enm != NULL) {
+		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
+			/*
+			 * We must listen to a range of multicast addresses.
+			 * For now, just accept all multicasts, rather than
+			 * trying to set only those filter bits needed to match
+			 * the range.  (At this time, the only use of address
+			 * ranges is for IP multicast routing, for which the
+			 * range is big enough to require all bits set.)
+			 */
+			goto allmulti;
+		}
+		sf_set_filter_hash(sc, enm->enm_addrlo);
+		ETHER_NEXT_MULTI(step, enm);
+	}
+
+	/*
+	 * Set "hash only multicast dest, match regardless of VLAN ID".
+	 */
+	sc->sc_RxAddressFilteringCtl |= RAFC_HashFilteringMode(2);
+	goto done;
+
+ allmulti:
+	/*
+	 * XXX RAFC_PassMulticast is sub-optimal if using VLAN mode.
+	 */
+	sc->sc_RxAddressFilteringCtl |= RAFC_PassMulticast;
+	ifp->if_flags |= IFF_ALLMULTI;
+
+ done:
+	sf_funcreg_write(sc, SF_RxAddressFilteringCtl,
+	    sc->sc_RxAddressFilteringCtl);
+}
+
+/*
+ * sf_mii_read:		[mii interface function]
+ *
+ *	Read from the MII.
+ */
+int
+sf_mii_read(struct device *self, int phy, int reg)
+{
+	struct sf_softc *sc = (void *) self;
+	uint32_t v;
+	int i;
+
+	for (i = 0; i < 1000; i++) {
+		v = sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg));
+		if (v & MiiDataValid)
+			break;
+		delay(1);
+	}
+
+	if ((v & MiiDataValid) == 0)
+		return (0);
+
+	if (MiiRegDataPort(v) == 0xffff)
+		return (0);
+
+	return (MiiRegDataPort(v));
+}
+
+/*
+ * sf_mii_write:	[mii interface function]
+ *
+ *	Write to the MII.
+ */
+void
+sf_mii_write(struct device *self, int phy, int reg, int val)
+{
+	struct sf_softc *sc = (void *) self;
+	int i;
+
+	sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val);
+
+	for (i = 0; i < 1000; i++) {
+		if ((sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)) &
+		     MiiBusy) == 0)
+			return;
+		delay(1);
+	}
+
+	printf("%s: MII write timed out\n", sc->sc_dev.dv_xname);
+}
+
+/*
+ * sf_mii_statchg:	[mii interface function]
+ *
+ *	Callback from the PHY when the media changes.
+ */
+void
+sf_mii_statchg(struct device *self)
+{
+	struct sf_softc *sc = (void *) self;
+	uint32_t ipg;
+
+	if (sc->sc_mii.mii_media_active & IFM_FDX) {
+		sc->sc_MacConfig1 |= MC1_FullDuplex;
+		ipg = 0x15;
+	} else {
+		sc->sc_MacConfig1 &= ~MC1_FullDuplex;
+		ipg = 0x11;
+	}
+
+	sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1);
+	sf_macreset(sc);
+
+	sf_genreg_write(sc, SF_BkToBkIPG, ipg);
+}
+
+/*
+ * sf_mediastatus:	[ifmedia interface function]
+ *
+ *	Callback from ifmedia to request current media status.
+ */
+void
+sf_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+	struct sf_softc *sc = ifp->if_softc;
+
+	mii_pollstat(&sc->sc_mii);
+	ifmr->ifm_status = sc->sc_mii.mii_media_status;
+	ifmr->ifm_active = sc->sc_mii.mii_media_active;
+}
+
+/*
+ * sf_mediachange:	[ifmedia interface function]
+ *
+ *	Callback from ifmedia to request new media setting.
+ */
+int
+sf_mediachange(struct ifnet *ifp)
+{
+	struct sf_softc *sc = ifp->if_softc;
+
+	if (ifp->if_flags & IFF_UP)
+		mii_mediachg(&sc->sc_mii);
+	return (0);
+}
diff --git a/sys/dev/ic/aic6915.h b/sys/dev/ic/aic6915.h
new file mode 100644
index 00000000000..fd5f07be5a8
--- /dev/null
+++ b/sys/dev/ic/aic6915.h
@@ -0,0 +1,845 @@
+/*	$OpenBSD: aic6915.h,v 1.1 2006/12/06 20:07:52 martin Exp $	*/
+/*	$NetBSD: aic6915reg.h,v 1.4 2005/12/11 12:21:25 christos Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_IC_AIC6915_H_
+#define	_DEV_IC_AIC6915_H_
+
+#include <sys/timeout.h>
+
+/*
+ * Register description for the Adaptec AIC-6915 (``Starfire'')
+ * 10/100 Ethernet controller.
+ */
+
+/*
+ * Receive Buffer Descriptor (One-size, 32-bit addressing)
+ */
+struct sf_rbd32 {
+	uint32_t	rbd32_addr;		/* address, flags */
+};
+
+/*
+ * Receive Buffer Descriptor (One-size, 64-bit addressing)
+ */
+struct sf_rbd64 {
+	uint32_t	rbd64_addr_lo;		/* address (LSD), flags */
+	uint32_t	rbd64_addr_hi;		/* address (MDS) */
+};
+
+#define	RBD_V		(1U << 0)	/* valid descriptor */
+#define	RBD_E		(1U << 1)	/* end of ring */
+
+/*
+ * Short (Type 0) Completion Descriptor
+ */
+struct sf_rcd_short {
+	uint32_t	rcd_word0;	/* length, end index, status1 */
+};
+
+/*
+ * Basic (Type 1) Completion Descriptor
+ */
+struct sf_rcd_basic {
+	uint32_t	rcd_word0;	/* length, end index, status1 */
+	uint32_t	rcd_word1;	/* VLAN ID, status2 */
+};
+
+/*
+ * Checksum (Type 2) Completion Descriptor
+ */
+struct sf_rcd_checksum {
+	uint32_t	rcd_word0;	/* length, end index, status1 */
+	uint32_t	rcd_word1;	/* partial TCP/UDP checksum, status2 */
+};
+
+/*
+ * Full (Type 3) Completion Descriptor
+ */
+struct sf_rcd_full {
+	uint32_t	rcd_word0;	/* length, end index, status1 */
+	uint32_t	rcd_word1;	/* start index, status3, status2 */
+	uint32_t	rcd_word2;	/* VLAN ID + priority, TCP/UDP csum */
+	uint32_t	rcd_timestamp;	/* timestamp */
+};
+
+#define	RCD_W0_ID		(1U << 30)
+
+#define	RCD_W0_Length(x)	((x) & 0xffff)
+#define	RCD_W0_EndIndex(x)	(((x) >> 16) & 0x7ff)
+#define	RCD_W0_BufferQueue	(1U << 27)	/* 1 == Queue 2 */
+#define	RCD_W0_FifoFull		(1U << 28)	/* FIFO full */
+#define	RCD_W0_OK		(1U << 29)	/* packet is OK */
+
+/* Status2 field */
+#define	RCD_W1_FrameType	(7U << 16)
+#define	RCD_W1_FrameType_Unknown (0 << 16)
+#define	RCD_W1_FrameType_IPv4	(1U << 16)
+#define	RCD_W1_FrameType_IPv6	(2U << 16)
+#define	RCD_W1_FrameType_IPX	(3U << 16)
+#define	RCD_W1_FrameType_ICMP	(4U << 16)
+#define	RCD_W1_FrameType_Unsupported (5U << 16)
+#define	RCD_W1_UdpFrame		(1U << 19)
+#define	RCD_W1_TcpFrame		(1U << 20)
+#define	RCD_W1_Fragmented	(1U << 21)
+#define	RCD_W1_PartialChecksumValid (1U << 22)
+#define	RCD_W1_ChecksumBad	(1U << 23)
+#define	RCD_W1_ChecksumOk	(1U << 24)
+#define	RCD_W1_VlanFrame	(1U << 25)
+#define	RCD_W1_ReceiveCodeViolation (1U << 26)
+#define	RCD_W1_Dribble		(1U << 27)
+#define	RCD_W1_ISLCRCerror	(1U << 28)
+#define	RCD_W1_CRCerror		(1U << 29)
+#define	RCD_W1_Hash		(1U << 30)
+#define	RCD_W1_Perfect		(1U << 31)
+
+#define	RCD_W1_VLANID(x)	((x) & 0xffff)
+#define	RCD_W1_TCP_UDP_Checksum(x) ((x) & 0xffff)
+
+/* Status3 field */
+#define	RCD_W1_Trailer		(1U << 11)
+#define	RCD_W1_Header		(1U << 12)
+#define	RCD_W1_ControlFrame	(1U << 13)
+#define	RCD_W1_PauseFrame	(1U << 14)
+#define	RCD_W1_IslFrame		(1U << 15)
+
+#define	RCD_W1_StartIndex(x)	((x) & 0x7ff)
+
+#define	RCD_W2_TCP_UDP_Checksum(x) ((x) >> 16)
+#define	RCD_W2_VLANID(x)	((x) & 0xffff)
+
+/*
+ * Number of transmit buffer fragments we use.  This is arbitrary, but
+ * we choose it carefully; see blow.
+ */
+#define	SF_NTXFRAGS		15
+
+/*
+ * Type 0, 32-bit addressing mode (Frame Descriptor) Transmit Descriptor
+ *
+ * NOTE: The total length of this structure is: 8 + (15 * 8) == 128
+ * This means 16 Tx indices per Type 0 descriptor.  This is important later
+ * on; see below.
+ */
+struct sf_txdesc0 {
+	/* skip field */
+	uint32_t	td_word0;	/* ID, flags */
+	uint32_t	td_word1;	/* Tx buffer count */
+	struct {
+		uint32_t fr_addr;	/* address */
+		uint32_t fr_len;	/* length */
+	} td_frags[SF_NTXFRAGS];
+};
+
+#define	TD_W1_NTXBUFS		(0xff << 0)
+
+/*
+ * Type 1, 32-bit addressing mode (Buffer Descriptor) Transmit Descriptor
+ */
+struct sf_txdesc1 {
+	/* skip field */
+	uint32_t	td_word0;	/* ID, flags */
+	uint32_t	td_addr;	/* buffer address */
+};
+
+#define	TD_W0_ID		(0xb << 28)
+#define	TD_W0_INTR		(1U << 27)
+#define	TD_W0_END		(1U << 26)
+#define	TD_W0_CALTCP		(1U << 25)
+#define	TD_W0_CRCEN		(1U << 24)
+#define	TD_W0_LEN		(0xffff << 0)
+#define	TD_W0_NTXBUFS		(0xff << 16)
+#define	TD_W0_NTXBUFS_SHIFT	16
+
+/*
+ * Type 2, 64-bit addressing mode (Buffer Descriptor) Transmit Descriptor
+ */
+struct sf_txdesc2 {
+	/* skip field */
+	uint32_t	td_word0;	/* ID, flags */
+	uint32_t	td_reserved;
+	uint32_t	td_addr_lo;	/* buffer address (LSD) */
+	uint32_t	td_addr_hi;	/* buffer address (MSD) */
+};
+
+/*
+ * Transmit Completion Descriptor.
+ */
+struct sf_tcd {
+	uint32_t	tcd_word0;	/* index, priority, flags */
+};
+
+#define	TCD_DMA_ID		(0x4 << 29)
+#define	TCD_INDEX(x)		((x) & 0x7fff)
+#define	TCD_PR			(1U << 15)
+#define	TCD_TIMESTAMP(x)	(((x) >> 16) & 0x1fff)
+
+#define	TCD_TX_ID		(0x5 << 29)
+#define	TCD_CRCerror		(1U << 16)
+#define	TCD_FieldLengthCkError	(1U << 17)
+#define	TCD_FieldLengthRngError	(1U << 18)
+#define	TCD_PacketTxOk		(1U << 19)
+#define	TCD_Deferred		(1U << 20)
+#define	TCD_ExDeferral		(1U << 21)
+#define	TCD_ExCollisions	(1U << 22)
+#define	TCD_LateCollision	(1U << 23)
+#define	TCD_LongFrame		(1U << 24)
+#define	TCD_FIFOUnderrun	(1U << 25)
+#define	TCD_ControlTx		(1U << 26)
+#define	TCD_PauseTx		(1U << 27)
+#define	TCD_TxPaused		(1U << 28)
+
+/*
+ * The Tx indices are in units of 8 bytes, and since we are using
+ * Tx descriptors that are 128 bytes long, we need to divide by 16
+ * to get the actual index that we care about.
+ */
+#define	SF_TXDINDEX_TO_HOST(x)		((x) >> 4)
+#define	SF_TXDINDEX_TO_CHIP(x)		((x) << 4)
+
+/*
+ * To make matters worse, the manual lies about the indices in the
+ * completion queue entires.  It claims they are in 8-byte units,
+ * but they're actually *BYTES*, which means we need to divide by
+ * 128 to get the actual index.
+ */
+#define	SF_TCD_INDEX_TO_HOST(x)		((x) >> 7)
+
+/*
+ * PCI configuration space addresses.
+ */
+#define	SF_PCI_MEMBA		(PCI_MAPREG_START + 0x00)
+#define	SF_PCI_IOBA		(PCI_MAPREG_START + 0x08)
+
+#define	SF_GENREG_OFFSET	0x50000
+#define	SF_FUNCREG_SIZE		0x100
+
+/*
+ * PCI functional registers.
+ */
+#define	SF_PciDeviceConfig	0x40
+#define	PDC_EnDpeInt		(1U << 31)	/* enable DPE PCIint */
+#define	PDC_EnSseInt		(1U << 30)	/* enable SSE PCIint */
+#define	PDC_EnRmaInt		(1U << 29)	/* enable RMA PCIint */
+#define	PDC_EnRtaInt		(1U << 28)	/* enable RTA PCIint */
+#define	PDC_EnStaInt		(1U << 27)	/* enable STA PCIint */
+#define	PDC_EnDprInt		(1U << 24)	/* enable DPR PCIint */
+#define	PDC_IntEnable		(1U << 23)	/* enable PCI_INTA_ */
+#define	PDC_ExternalRegCsWidth	(7U << 20)	/* external chip-sel width */
+#define	PDC_StopMWrOnCacheLineDis (1U << 19)
+#define	PDC_EpromCsWidth	(7U << 16)
+#define	PDC_EnBeLogic		(1U << 15)
+#define	PDC_LatencyStopOnCacheLine (1U << 14)
+#define	PDC_PCIMstDmaEn		(1U << 13)
+#define	PDC_StopOnCachelineEn	(1U << 12)
+#define	PDC_FifoThreshold	(0xf << 8)
+#define	PDC_FifoThreshold_SHIFT	8
+#define	PDC_MemRdCmdEn		(1U << 7)
+#define	PDC_StopOnPerr		(1U << 6)
+#define	PDC_AbortOnAddrParityErr (1U << 5)
+#define	PDC_EnIncrement		(1U << 4)
+#define	PDC_System64		(1U << 2)
+#define	PDC_Force64		(1U << 1)
+#define	PDC_SoftReset		(1U << 0)
+
+#define	SF_BacControl		0x44
+#define	BC_DescSwapMode		(0x3 << 6)
+#define	BC_DataSwapMode		(0x3 << 4)
+#define	BC_SingleDmaMode	(1U << 3)
+#define	BC_PreferTxDmaReq	(1U << 2)
+#define	BC_PreferRxDmaReq	(1U << 1)
+#define	BC_BacDmaEn		(1U << 0)
+
+#define	SF_PciMonitor1		0x48
+
+#define	SF_PciMonitor2		0x4c
+
+#define	SF_PMC			0x50
+
+#define	SF_PMCSR		0x54
+
+#define	SF_PMEvent		0x58
+
+#define	SF_SerialEpromControl	0x60
+#define	SEC_InitDone		(1U << 3)
+#define	SEC_Idle		(1U << 2)
+#define	SEC_WriteEnable		(1U << 1)
+#define	SEC_WriteDisable	(1U << 0)
+
+#define	SF_PciComplianceTesting	0x64
+
+#define	SF_IndirectIoAccess	0x68
+
+#define	SF_IndirectIoDataPort	0x6c
+
+/*
+ * Ethernet functional registers.
+ */
+#define	SF_GeneralEthernetCtrl	0x70
+#define	GEC_SetSoftInt		(1U << 8)
+#define	GEC_TxGfpEn		(1U << 5)
+#define	GEC_RxGfpEn		(1U << 4)
+#define	GEC_TxDmaEn		(1U << 3)
+#define	GEC_RxDmaEn		(1U << 2)
+#define	GEC_TransmitEn		(1U << 1)
+#define	GEC_ReceiveEn		(1U << 0)
+
+#define	SF_TimersControl	0x74
+#define	TC_EarlyRxQ1IntDelayDisable	(1U << 31)
+#define	TC_RxQ1DoneIntDelayDisable	(1U << 30)
+#define	TC_EarlyRxQ2IntDelayDisable	(1U << 29)
+#define	TC_RxQ2DoneIntDelayDisable	(1U << 28)
+#define	TC_TimeStampResolution		(1U << 26)
+#define	TC_GeneralTimerResolution	(1U << 25)
+#define	TC_OneShotMode			(1U << 24)
+#define	TC_GeneralTimerInterval		(0xff << 16)
+#define	TC_GeneralTimerInterval_SHIFT	16
+#define	TC_TxFrameCompleteIntDelayDisable (1U << 15)
+#define	TC_TxQueueDoneIntDelayDisable	(1U << 14)
+#define	TC_TxDmaDoneIntDelayDisable	(1U << 13)
+#define	TC_RxHiPrBypass			(1U << 12)
+#define	TC_Timer10X			(1U << 11)
+#define	TC_SmallRxFrame			(3U << 9)
+#define	TC_SmallFrameBypass		(1U << 8)
+#define	TC_IntMaskMode			(3U << 5)
+#define	TC_IntMaskPeriod		(0x1f << 0)
+
+#define	SF_CurrentTime		0x78
+
+#define	SF_InterruptStatus	0x80
+#define	IS_GPIO3			(1U << 31)
+#define	IS_GPIO2			(1U << 30)
+#define	IS_GPIO1			(1U << 29)
+#define	IS_GPIO0			(1U << 28)
+#define	IS_StatisticWrapInt		(1U << 27)
+#define	IS_AbnormalInterrupt		(1U << 25)
+#define	IS_GeneralTimerInt		(1U << 24)
+#define	IS_SoftInt			(1U << 23)
+#define	IS_RxCompletionQueue1Int	(1U << 22)
+#define	IS_TxCompletionQueueInt		(1U << 21)
+#define	IS_PCIInt			(1U << 20)
+#define	IS_DmaErrInt			(1U << 19)
+#define	IS_TxDataLowInt			(1U << 18)
+#define	IS_RxCompletionQueue2Int	(1U << 17)
+#define	IS_RxQ1LowBuffersInt		(1U << 16)
+#define	IS_NormalInterrupt		(1U << 15)
+#define	IS_TxFrameCompleteInt		(1U << 14)
+#define	IS_TxDmaDoneInt			(1U << 13)
+#define	IS_TxQueueDoneInt		(1U << 12)
+#define	IS_EarlyRxQ2Int			(1U << 11)
+#define	IS_EarlyRxQ1Int			(1U << 10)
+#define	IS_RxQ2DoneInt			(1U << 9)
+#define	IS_RxQ1DoneInt			(1U << 8)
+#define	IS_RxGfpNoResponseInt		(1U << 7)
+#define	IS_RxQ2LowBuffersInt		(1U << 6)
+#define	IS_NoTxChecksumInt		(1U << 5)
+#define	IS_TxLowPrMismatchInt		(1U << 4)
+#define	IS_TxHiPrMismatchInt		(1U << 3)
+#define	IS_GfpRxInt			(1U << 2)
+#define	IS_GfpTxInt			(1U << 1)
+#define	IS_PCIPadInt			(1U << 0)
+
+#define	SF_ShadowInterruptStatus 0x84
+
+#define	SF_InterruptEn		0x88
+
+#define	SF_GPIO			0x8c
+#define	GPIOCtrl(x)		(1U << (24 + (x)))
+#define	GPIOOutMode(x)		(1U << (16 + (x)))
+#define	GPIOInpMode(x, y)	((y) << (8 + ((x) * 2)))
+#define	GPIOData(x)		(1U << (x))
+
+#define	SF_TxDescQueueCtrl	0x90
+#define	TDQC_TxHighPriorityFifoThreshold(x)	((x) << 24)
+#define	TDQC_SkipLength(x)			((x) << 16)
+#define	TDQC_TxDmaBurstSize(x)			((x) << 8)
+#define	TDQC_TxDescQueue64bitAddr		(1U << 7)
+#define	TDQC_MinFrameSpacing(x)			((x) << 4)
+#define	TDQC_DisableTxDmaCompletion		(1U << 3)
+#define	TDQC_TxDescType(x)			((x) << 0)
+
+#define	SF_HiPrTxDescQueueBaseAddr 0x94
+
+#define	SF_LoPrTxDescQueueBaseAddr 0x98
+
+#define	SF_TxDescQueueHighAddr	0x9c
+
+#define	SF_TxDescQueueProducerIndex 0xa0
+#define	TDQPI_HiPrTxProducerIndex(x)		((x) << 16)
+#define	TDQPI_LoPrTxProducerIndex(x)		((x) << 0)
+#define	TDQPI_HiPrTxProducerIndex_get(x)	(((x) >> 16) & 0x7ff)
+#define	TDQPI_LoPrTxProducerIndex_get(x)	(((x) >> 0) & 0x7ff)
+
+#define	SF_TxDescQueueConsumerIndex 0xa4
+#define	TDQCI_HiPrTxConsumerIndex(x)		(((x) >> 16) & 0x7ff)
+#define	TDQCI_LoPrTxConsumerIndex(s)		(((x) >> 0) & 0x7ff)
+
+#define	SF_TxDmaStatus1		0xa8
+
+#define	SF_TxDmaStatus2		0xac
+
+#define	SF_TransmitFrameCSR	0xb0
+#define	TFCSR_TxFrameStatus			(0xff << 16)
+#define	TFCSR_TxDebugConfigBits			(0x7f << 9)
+#define	TFCSR_DmaCompletionAfterTransmitComplete (1U << 8)
+#define	TFCSR_TransmitThreshold(x)		((x) << 0)
+
+#define	SF_CompletionQueueHighAddr 0xb4
+
+#define	SF_TxCompletionQueueCtrl 0xb8
+#define	TCQC_TxCompletionBaseAddress		0xffffff00
+#define	TCQC_TxCompletion64bitAddress		(1U << 7)
+#define	TCQC_TxCompletionProducerWe		(1U << 6)
+#define	TCQC_TxCompletionSize			(1U << 5)
+#define	TCQC_CommonQueueMode			(1U << 4)
+#define	TCQC_TxCompletionQueueThreshold		((x) << 0)
+
+#define	SF_RxCompletionQueue1Ctrl 0xbc
+#define	RCQ1C_RxCompletionQ1BaseAddress		0xffffff00
+#define	RCQ1C_RxCompletionQ164bitAddress	(1U << 7)
+#define	RCQ1C_RxCompletionQ1ProducerWe		(1U << 6)
+#define	RCQ1C_RxCompletionQ1Type(x)		((x) << 4)
+#define	RCQ1C_RxCompletionQ1Threshold(x)	((x) << 0)
+
+#define	SF_RxCompletionQueue2Ctrl 0xc0
+#define	RCQ1C_RxCompletionQ2BaseAddress		0xffffff00
+#define	RCQ1C_RxCompletionQ264bitAddress	(1U << 7)
+#define	RCQ1C_RxCompletionQ2ProducerWe		(1U << 6)
+#define	RCQ1C_RxCompletionQ2Type(x)		((x) << 4)
+#define	RCQ1C_RxCompletionQ2Threshold(x)	((x) << 0)
+
+#define	SF_CompletionQueueConsumerIndex 0xc4
+#define	CQCI_TxCompletionThresholdMode		(1U << 31)
+#define	CQCI_TxCompletionConsumerIndex(x)	((x) << 16)
+#define	CQCI_TxCompletionConsumerIndex_get(x)	(((x) >> 16) & 0x7ff)
+#define	CQCI_RxCompletionQ1ThresholdMode	(1U << 15)
+#define	CQCI_RxCompletionQ1ConsumerIndex(x)	((x) << 0)
+#define	CQCI_RxCompletionQ1ConsumerIndex_get(x)	((x) & 0x7ff)
+
+#define	SF_CompletionQueueProducerIndex 0xc8
+#define	CQPI_TxCompletionProducerIndex(x)	((x) << 16)
+#define	CQPI_TxCompletionProducerIndex_get(x)	(((x) >> 16) & 0x7ff)
+#define	CQPI_RxCompletionQ1ProducerIndex(x)	((x) << 0)
+#define	CQPI_RxCompletionQ1ProducerIndex_get(x)	((x) & 0x7ff)
+
+#define	SF_RxHiPrCompletionPtrs	0xcc
+#define	RHPCP_RxCompletionQ2ProducerIndex(x)	((x) << 16)
+#define	RHPCP_RxCompletionQ2ThresholdMode	(1U << 15)
+#define	RHPCP_RxCompletionQ2ConsumerIndex(x)	((x) << 0)
+
+#define	SF_RxDmaCtrl		0xd0
+#define	RDC_RxReportBadFrames			(1U << 31)
+#define	RDC_RxDmaShortFrames			(1U << 30)
+#define	RDC_RxDmaBadFrames			(1U << 29)
+#define	RDC_RxDmaCrcErrorFrames			(1U << 28)
+#define	RDC_RxDmaControlFrame			(1U << 27)
+#define	RDC_RxDmaPauseFrame			(1U << 26)
+#define	RDC_RxChecksumMode(x)			((x) << 24)
+#define	RDC_RxCompletionQ2Enable		(1U << 23)
+#define	RDC_RxDmaQueueMode(x)			((x) << 20)
+#define	RDC_RxUseBackupQueue			(1U << 19)
+#define	RDC_RxDmaCrc				(1U << 18)
+#define	RDC_RxEarlyIntThreshold(x)		((x) << 12)
+#define	RDC_RxHighPriorityThreshold(x)		((x) << 8)
+#define	RDC_RxBurstSize(x)			((x) << 0)
+
+#define	SF_RxDescQueue1Ctrl	0xd4
+#define	RDQ1C_RxQ1BufferLength(x)		((x) << 16)
+#define	RDQ1C_RxPrefetchDescriptorsMode		(1U << 15)
+#define	RDQ1C_RxDescQ1Entries			(1U << 14)
+#define	RDQ1C_RxVariableSizeQueues		(1U << 13)
+#define	RDQ1C_Rx64bitBufferAddresses		(1U << 12)
+#define	RDQ1C_Rx64bitDescQueueAddress		(1U << 11)
+#define	RDQ1C_RxDescSpacing(x)			((x) << 8)
+#define	RDQ1C_RxQ1ConsumerWe			(1U << 7)
+#define	RDQ1C_RxQ1MinDescriptorsThreshold(x)	((x) << 0)
+
+#define	SF_RxDescQueue2Ctrl	0xd8
+#define	RDQ2C_RxQ2BufferLength(x)		((x) << 16)
+#define	RDQ2C_RxDescQ2Entries			(1U << 14)
+#define	RDQ2C_RxQ2MinDescriptorsThreshold(x)	((x) << 0)
+
+#define	SF_RxDescQueueHighAddress 0xdc
+
+#define	SF_RxDescQueue1LowAddress 0xe0
+
+#define	SF_RxDescQueue2LowAddress 0xe4
+
+#define	SF_RxDescQueue1Ptrs	0xe8
+#define	RXQ1P_RxDescQ1Consumer(x)		((x) << 16)
+#define	RXQ1P_RxDescQ1Producer(x)		((x) << 0)
+#define	RXQ1P_RxDescQ1Producer_get(x)		((x) & 0x7ff)
+
+#define	SF_RxDescQueue2Ptrs	0xec
+#define	RXQ2P_RxDescQ2Consumer(x)		((x) << 16)
+#define	RXQ2P_RxDescQ2Producer(x)		((x) << 0)
+
+#define	SF_RxDmaStatus		0xf0
+#define	RDS_RxFramesLostCount(x)		((x) & 0xffff)
+
+#define	SF_RxAddressFilteringCtl 0xf4
+#define	RAFC_PerfectAddressPriority(x)		(1U << ((x) + 16))
+#define	RAFC_MinVlanPriority(x)			((x) << 13)
+#define	RAFC_PassMulticastExceptBroadcast	(1U << 12)
+#define	RAFC_WakeupMode(x)			((x) << 10)
+#define	RAFC_VlanMode(x)			((x) << 8)
+#define	RAFC_PerfectFilteringMode(x)		((x) << 6)
+#define	RAFC_HashFilteringMode(x)		((x) << 4)
+#define	RAFC_HashPriorityEnable			(1U << 3)
+#define	RAFC_PassBroadcast			(1U << 2)
+#define	RAFC_PassMulticast			(1U << 1)
+#define	RAFC_PromiscuousMode			(1U << 0)
+
+#define	SF_RxFrameTestOut	0xf8
+
+/*
+ * Additional PCI registers.  To access these registers via I/O space,
+ * indirect access must be used.
+ */
+#define	SF_PciTargetStatus	0x100
+
+#define	SF_PciMasterStatus1	0x104
+
+#define	SF_PciMasterStatus2	0x108
+
+#define	SF_PciDmaLowHostAddr	0x10c
+
+#define	SF_BacDmaDiagnostic0	0x110
+
+#define	SF_BacDmaDiagnostic1	0x114
+
+#define	SF_BacDmaDiagnostic2	0x118
+
+#define	SF_BacDmaDiagnostic3	0x11c
+
+#define	SF_MacAddr1		0x120
+
+#define	SF_MacAddr2		0x124
+
+#define	SF_FunctionEvent	0x130
+
+#define	SF_FunctionEventMask	0x134
+
+#define	SF_FunctionPresentState	0x138
+
+#define	SF_ForceFunction	0x13c
+
+#define	SF_EEPROM_BASE		0x1000
+
+#define	SF_MII_BASE		0x2000
+#define	MiiDataValid		(1U << 31)
+#define	MiiBusy			(1U << 30)
+#define	MiiRegDataPort(x)	((x) & 0xffff)
+
+#define	SF_MII_PHY_REG(p, r)	(SF_MII_BASE +				\
+				 ((p) * 32 * sizeof(uint32_t)) +	\
+				 ((r) * sizeof(uint32_t)))
+
+#define	SF_TestMode		0x4000
+
+#define	SF_RxFrameProcessorCtrl	0x4004
+
+#define	SF_TxFrameProcessorCtrl	0x4008
+
+#define	SF_MacConfig1		0x5000
+#define	MC1_SoftRst			(1U << 15)
+#define	MC1_MiiLoopBack			(1U << 14)
+#define	MC1_TestMode(x)			((x) << 12)
+#define	MC1_TxFlowEn			(1U << 11)
+#define	MC1_RxFlowEn			(1U << 10)
+#define	MC1_PreambleDetectCount		(1U << 9)
+#define	MC1_PassAllRxPackets		(1U << 8)
+#define	MC1_PurePreamble		(1U << 7)
+#define	MC1_LengthCheck			(1U << 6)
+#define	MC1_NoBackoff			(1U << 5)
+#define	MC1_DelayCRC			(1U << 4)
+#define	MC1_TxHalfDuplexJam		(1U << 3)
+#define	MC1_PadEn			(1U << 2)
+#define	MC1_FullDuplex			(1U << 1)
+#define	MC1_HugeFrame			(1U << 0)
+
+#define	SF_MacConfig2		0x5004
+#define	MC2_TxCRCerr			(1U << 15)
+#define	MC2_TxIslCRCerr			(1U << 14)
+#define	MC2_RxCRCerr			(1U << 13)
+#define	MC2_RxIslCRCerr			(1U << 12)
+#define	MC2_TXCF			(1U << 11)
+#define	MC2_CtlSoftRst			(1U << 10)
+#define	MC2_RxSoftRst			(1U << 9)
+#define	MC2_TxSoftRst			(1U << 8)
+#define	MC2_RxISLEn			(1U << 7)
+#define	MC2_BackPressureNoBackOff	(1U << 6)
+#define	MC2_AutoVlanPad			(1U << 5)
+#define	MC2_MandatoryVLANPad		(1U << 4)
+#define	MC2_TxISLAppen			(1U << 3)
+#define	MC2_TxISLEn			(1U << 2)
+#define	MC2_SimuRst			(1U << 1)
+#define	MC2_TxXmtEn			(1U << 0)
+
+#define	SF_BkToBkIPG		0x5008
+
+#define	SF_NonBkToBkIPG		0x500c
+
+#define	SF_ColRetry		0x5010
+
+#define	SF_MaxLength		0x5014
+
+#define	SF_TxNibbleCnt		0x5018
+
+#define	SF_TxByteCnt		0x501c
+
+#define	SF_ReTxCnt		0x5020
+
+#define	SF_RandomNumGen		0x5024
+
+#define	SF_MskRandomNum		0x5028
+
+#define	SF_TotalTxCnt		0x5034
+
+#define	SF_RxByteCnt		0x5040
+
+#define	SF_TxPauseTimer		0x5060
+
+#define	SF_VLANType		0x5064
+
+#define	SF_MiiStatus		0x5070
+
+#define	SF_PERFECT_BASE		0x6000
+#define	SF_PERFECT_SIZE		0x100
+
+#define	SF_HASH_BASE		0x6100
+#define	SF_HASH_SIZE		0x200
+
+#define	SF_STATS_BASE		0x7000
+struct sf_stats {
+	uint32_t	TransmitOKFrames;
+	uint32_t	SingleCollisionFrames;
+	uint32_t	MultipleCollisionFrames;
+	uint32_t	TransmitCRCErrors;
+	uint32_t	TransmitOKOctets;
+	uint32_t	TransmitDeferredFrames;
+	uint32_t	TransmitLateCollisionCount;
+	uint32_t	TransmitPauseControlFrames;
+	uint32_t	TransmitControlFrames;
+	uint32_t	TransmitAbortDueToExcessiveCollisions;
+	uint32_t	TransmitAbortDueToExcessingDeferral;
+	uint32_t	MulticastFramesTransmittedOK;
+	uint32_t	BroadcastFramesTransmittedOK;
+	uint32_t	FramesLostDueToInternalTransmitErrors;
+	uint32_t	ReceiveOKFrames;
+	uint32_t	ReceiveCRCErrors;
+	uint32_t	AlignmentErrors;
+	uint32_t	ReceiveOKOctets;
+	uint32_t	PauseFramesReceivedOK;
+	uint32_t	ControlFramesReceivedOK;
+	uint32_t	ControlFramesReceivedWithUnsupportedOpcode;
+	uint32_t	ReceiveFramesTooLong;
+	uint32_t	ReceiveFramesTooShort;
+	uint32_t	ReceiveFramesJabbersError;
+	uint32_t	ReceiveFramesFragments;
+	uint32_t	ReceivePackets64Bytes;
+	uint32_t	ReceivePackets127Bytes;
+	uint32_t	ReceivePackets255Bytes;
+	uint32_t	ReceivePackets511Bytes;
+	uint32_t	ReceivePackets1023Bytes;
+	uint32_t	ReceivePackets1518Bytes;
+	uint32_t	FramesLostDueToInternalReceiveErrors;
+	uint32_t	TransmitFifoUnderflowCounts;
+};
+
+#define	SF_TxGfpMem		0x8000
+
+#define	SF_RxGfpMem		0xa000
+
+/*
+ * Data structure definitions for the Adaptec AIC-6915 (``Starfire'')
+ * PCI 10/100 Ethernet controller driver.
+ */
+
+/*
+ * Transmit descriptor list size.
+ */
+#define	SF_NTXDESC		256
+#define	SF_NTXDESC_MASK		(SF_NTXDESC - 1)
+#define	SF_NEXTTX(x)		((x + 1) & SF_NTXDESC_MASK)
+
+/*
+ * Transmit completion queue size.  1024 is a hardware requirement.
+ */
+#define	SF_NTCD			1024
+#define	SF_NTCD_MASK		(SF_NTCD - 1)
+#define	SF_NEXTTCD(x)		((x + 1) & SF_NTCD_MASK)
+
+/*
+ * Receive descriptor list size.
+ */
+#define	SF_NRXDESC		256
+#define	SF_NRXDESC_MASK		(SF_NRXDESC - 1)
+#define	SF_NEXTRX(x)		((x + 1) & SF_NRXDESC_MASK)
+
+/*
+ * Receive completion queue size.  1024 is a hardware requirement.
+ */
+#define	SF_NRCD			1024
+#define	SF_NRCD_MASK		(SF_NRCD - 1)
+#define	SF_NEXTRCD(x)		((x + 1) & SF_NRCD_MASK)
+
+/*
+ * Control structures are DMA to the Starfire chip.  We allocate them in
+ * a single clump that maps to a single DMA segment to make several things
+ * easier.
+ */
+struct sf_control_data {
+	/*
+	 * The transmit descriptors.
+	 */
+	struct sf_txdesc0 scd_txdescs[SF_NTXDESC];
+
+	/*
+	 * The transmit completion queue entires.
+	 */
+	struct sf_tcd scd_txcomp[SF_NTCD];
+
+	/*
+	 * The receive buffer descriptors.
+	 */
+	struct sf_rbd32 scd_rxbufdescs[SF_NRXDESC];
+
+	/*
+	 * The receive completion queue entries.
+	 */
+	struct sf_rcd_full scd_rxcomp[SF_NRCD];
+};
+
+#define	SF_CDOFF(x)		offsetof(struct sf_control_data, x)
+#define	SF_CDTXDOFF(x)		SF_CDOFF(scd_txdescs[(x)])
+#define	SF_CDTXCOFF(x)		SF_CDOFF(scd_txcomp[(x)])
+#define	SF_CDRXDOFF(x)		SF_CDOFF(scd_rxbufdescs[(x)])
+#define	SF_CDRXCOFF(x)		SF_CDOFF(scd_rxcomp[(x)])
+
+/*
+ * Software state for transmit and receive descriptors.
+ */
+struct sf_descsoft {
+	struct mbuf *ds_mbuf;		/* head of mbuf chain */
+	bus_dmamap_t ds_dmamap;		/* our DMA map */
+};
+
+/*
+ * Software state per device.
+ */
+struct sf_softc {
+	struct device sc_dev;		/* generic device information */
+	bus_space_tag_t sc_st;		/* bus space tag */
+	bus_space_handle_t sc_sh;	/* bus space handle */
+	bus_space_handle_t sc_sh_func;	/* sub-handle for func regs */
+	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
+	struct arpcom sc_arpcom;	/* ethernet common data */
+	void *sc_sdhook;		/* shutdown hook */
+	int sc_iomapped;		/* are we I/O mapped? */
+
+	struct mii_data sc_mii;		/* MII/media information */
+	struct timeout sc_mii_timeout;	/* MII callout */
+
+	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
+#define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
+
+	/*
+	 * Software state for transmit and receive descriptors.
+	 */
+	struct sf_descsoft sc_txsoft[SF_NTXDESC];
+	struct sf_descsoft sc_rxsoft[SF_NRXDESC];
+
+	/*
+	 * Control data structures.
+	 */
+	struct sf_control_data *sc_control_data;
+#define	sc_txdescs	sc_control_data->scd_txdescs
+#define	sc_txcomp	sc_control_data->scd_txcomp
+#define	sc_rxbufdescs	sc_control_data->scd_rxbufdescs
+#define	sc_rxcomp	sc_control_data->scd_rxcomp
+
+	int	sc_txpending;		/* number of Tx requests pending */
+
+	uint32_t sc_InterruptEn;	/* prototype InterruptEn register */
+
+	uint32_t sc_TransmitFrameCSR;	/* prototype TransmitFrameCSR reg */
+	uint32_t sc_TxDescQueueCtrl;	/* prototype TxDescQueueCtrl reg */
+	int	sc_txthresh;		/* current Tx threshold */
+
+	uint32_t sc_MacConfig1;		/* prototype MacConfig1 register */
+
+	uint32_t sc_RxAddressFilteringCtl;
+};
+
+#define	SF_CDTXDADDR(sc, x)	((sc)->sc_cddma + SF_CDTXDOFF((x)))
+#define	SF_CDTXCADDR(sc, x)	((sc)->sc_cddma + SF_CDTXCOFF((x)))
+#define	SF_CDRXDADDR(sc, x)	((sc)->sc_cddma + SF_CDRXDOFF((x)))
+#define	SF_CDRXCADDR(sc, x)	((sc)->sc_cddma + SF_CDRXCOFF((x)))
+
+#define	SF_CDTXDSYNC(sc, x, ops)					\
+	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
+	    SF_CDTXDOFF((x)), sizeof(struct sf_txdesc0), (ops))
+
+#define	SF_CDTXCSYNC(sc, x, ops)					\
+	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
+	    SF_CDTXCOFF((x)), sizeof(struct sf_tcd), (ops))
+
+#define	SF_CDRXDSYNC(sc, x, ops)					\
+	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
+	    SF_CDRXDOFF((x)), sizeof(struct sf_rbd32), (ops))
+
+#define	SF_CDRXCSYNC(sc, x, ops)					\
+	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
+	    SF_CDRXCOFF((x)), sizeof(struct sf_rcd_full), (ops))
+
+#define	SF_INIT_RXDESC(sc, x)						\
+do {									\
+	struct sf_descsoft *__ds = &sc->sc_rxsoft[(x)];			\
+									\
+	(sc)->sc_rxbufdescs[(x)].rbd32_addr =				\
+	    __ds->ds_dmamap->dm_segs[0].ds_addr | RBD_V;		\
+	SF_CDRXDSYNC((sc), (x), BUS_DMASYNC_PREWRITE);			\
+} while (/*CONSTCOND*/0)
+
+#ifdef _KERNEL
+void	sf_attach(struct sf_softc *);
+int	sf_intr(void *);
+#endif /* _KERNEL */
+
+#endif /* _DEV_IC_AIC6915_H_ */
diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci
index 18f6070d4d3..199e4768333 100644
--- a/sys/dev/pci/files.pci
+++ b/sys/dev/pci/files.pci
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.pci,v 1.220 2006/11/27 16:47:05 grange Exp $
+#	$OpenBSD: files.pci,v 1.221 2006/12/06 20:07:52 martin Exp $
 #	$NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $
 #
 # Config file and device description for machine-independent PCI code.
@@ -398,9 +398,8 @@ attach	wb at pci
 file	dev/pci/if_wb.c			wb
 
 # Adaptec AIC-6915 "Starfire" ethernet
-device	sf: ether, ifnet, mii, ifmedia
-attach	sf at pci
-file	dev/pci/if_sf.c			sf
+attach	sf at pci with sf_pci
+file	dev/pci/if_sf_pci.c		sf_pci
 
 # SiS 900/7016 ethernet
 device	sis: ether, ifnet, mii, ifmedia
diff --git a/sys/dev/pci/if_sf.c b/sys/dev/pci/if_sf.c
deleted file mode 100644
index 77cd73aebe7..00000000000
--- a/sys/dev/pci/if_sf.c
+++ /dev/null
@@ -1,1395 +0,0 @@
-/*	$OpenBSD: if_sf.c,v 1.40 2006/08/22 19:11:46 martin Exp $ */
-/*
- * Copyright (c) 1997, 1998, 1999
- *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Bill Paul.
- * 4. Neither the name of the author nor the names of any co-contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD: src/sys/pci/if_sf.c,v 1.23 2000/07/14 19:11:02 wpaul Exp $
- */
-
-/*
- * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
- * Programming manual is available from:
- * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf.
- *
- * Written by Bill Paul <wpaul@ctr.columbia.edu>
- * Department of Electical Engineering
- * Columbia University, New York City
- */
-
-/*
- * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
- * controller designed with flexibility and reducing CPU load in mind.
- * The Starfire offers high and low priority buffer queues, a
- * producer/consumer index mechanism and several different buffer
- * queue and completion queue descriptor types. Any one of a number
- * of different driver designs can be used, depending on system and
- * OS requirements. This driver makes use of type0 transmit frame
- * descriptors (since BSD fragments packets across an mbuf chain)
- * and two RX buffer queues prioritized on size (one queue for small
- * frames that will fit into a single mbuf, another with full size
- * mbuf clusters for everything else). The producer/consumer indexes
- * and completion queues are also used.
- *
- * One downside to the Starfire has to do with alignment: buffer
- * queues must be aligned on 256-byte boundaries, and receive buffers
- * must be aligned on longword boundaries. The receive buffer alignment
- * causes problems on the Alpha platform, where the packet payload
- * should be longword aligned. There is no simple way around this.
- *
- * For receive filtering, the Starfire offers 16 perfect filter slots
- * and a 512-bit hash table.
- *
- * The Starfire has no internal transceiver, relying instead on an
- * external MII-based transceiver. Accessing registers on external
- * PHYs is done through a special register map rather than with the
- * usual bitbang MDIO method.
- *
- * Accessing the registers on the Starfire is a little tricky. The
- * Starfire has a 512K internal register space. When programmed for
- * PCI memory mapped mode, the entire register space can be accessed
- * directly. However in I/O space mode, only 256 bytes are directly
- * mapped into PCI I/O space. The other registers can be accessed
- * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
- * registers inside the 256-byte I/O window.
- */
-
-#include "bpfilter.h"
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/mbuf.h>
-#include <sys/protosw.h>
-#include <sys/socket.h>
-#include <sys/ioctl.h>
-#include <sys/errno.h>
-#include <sys/malloc.h>
-#include <sys/kernel.h>
-#include <sys/timeout.h>
-
-#include <net/if.h>
-#include <net/if_dl.h>
-#include <net/if_types.h>
-
-#include <netinet/in.h>
-#include <netinet/in_systm.h>
-#include <netinet/in_var.h>
-#include <netinet/ip.h>
-#include <netinet/if_ether.h>
-
-#include <net/if_media.h>
-
-#if NBPFILTER > 0
-#include <net/bpf.h>
-#endif
-
-#include <uvm/uvm_extern.h>              /* for vtophys */
-
-#include <sys/device.h>
-
-#include <dev/mii/mii.h>
-#include <dev/mii/miivar.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcidevs.h>
-
-#define SF_USEIOSPACE
-
-#include <dev/pci/if_sfreg.h>
-
-int sf_probe(struct device *, void *, void *);
-void sf_attach(struct device *, struct device *, void *);
-int sf_intr(void *);
-void sf_shutdown(void *);
-void sf_stats_update(void *);
-void sf_rxeof(struct sf_softc *);
-void sf_txeof(struct sf_softc *);
-int sf_encap(struct sf_softc *, struct sf_tx_bufdesc_type0 *,
-				struct mbuf *);
-void sf_start(struct ifnet *);
-int sf_ioctl(struct ifnet *, u_long, caddr_t);
-void sf_init(void *);
-void sf_stop(struct sf_softc *);
-void sf_watchdog(struct ifnet *);
-int sf_ifmedia_upd(struct ifnet *);
-void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *);
-void sf_reset(struct sf_softc *);
-int sf_init_rx_ring(struct sf_softc *);
-void sf_init_tx_ring(struct sf_softc *);
-int sf_newbuf(struct sf_softc *, struct sf_rx_bufdesc_type0 *,
-				struct mbuf *);
-void sf_setmulti(struct sf_softc *);
-int sf_setperf(struct sf_softc *, int, caddr_t);
-int sf_sethash(struct sf_softc *, caddr_t, int);
-#ifdef notdef
-int sf_setvlan(struct sf_softc *, int, u_int32_t);
-#endif
-
-u_int8_t sf_read_eeprom(struct sf_softc *, int);
-
-int sf_miibus_readreg(struct device *, int, int);
-void sf_miibus_writereg(struct device *, int, int, int);
-void sf_miibus_statchg(struct device *);
-
-u_int32_t csr_read_4(struct sf_softc *, int);
-void csr_write_4(struct sf_softc *, int, u_int32_t);
-void sf_txthresh_adjust(struct sf_softc *);
-
-#define SF_SETBIT(sc, reg, x)	\
-	csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
-
-#define SF_CLRBIT(sc, reg, x)				\
-	csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
-
-u_int32_t csr_read_4(sc, reg)
-	struct sf_softc		*sc;
-	int			reg;
-{
-	u_int32_t		val;
-
-#ifdef SF_USEIOSPACE
-	CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
-	val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
-#else
-	val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
-#endif
-
-	return(val);
-}
-
-u_int8_t sf_read_eeprom(sc, reg)
-	struct sf_softc		*sc;
-	int			reg;
-{
-	u_int8_t		val;
-
-	val = (csr_read_4(sc, SF_EEADDR_BASE +
-	    (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
-
-	return(val);
-}
-
-void csr_write_4(sc, reg, val)
-	struct sf_softc		*sc;
-	int			reg;
-	u_int32_t		val;
-{
-#ifdef SF_USEIOSPACE
-	CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
-	CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
-#else
-	CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
-#endif
-	return;
-}
-
-/*
- * Copy the address 'mac' into the perfect RX filter entry at
- * offset 'idx.' The perfect filter only has 16 entries so do
- * some sanity tests.
- */
-int sf_setperf(sc, idx, mac)
-	struct sf_softc		*sc;
-	int			idx;
-	caddr_t			mac;
-{
-	u_int16_t		*p;
-
-	if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
-		return(EINVAL);
-
-	if (mac == NULL)
-		return(EINVAL);
-
-	p = (u_int16_t *)mac;
-
-	csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
-	    (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
-	csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
-	    (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
-	csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
-	    (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
-
-	return(0);
-}
-
-/*
- * Set the bit in the 512-bit hash table that corresponds to the
- * specified mac address 'mac.' If 'prio' is nonzero, update the
- * priority hash table instead of the filter hash table.
- */
-int sf_sethash(sc, mac, prio)
-	struct sf_softc		*sc;
-	caddr_t			mac;
-	int			prio;
-{
-	u_int32_t		h = 0;
-
-	if (mac == NULL)
-		return(EINVAL);
-
-	h = (ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23) & 0x1FF;
-
-	if (prio) {
-		SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
-		    (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
-	} else {
-		SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
-		    (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
-	}
-
-	return(0);
-}
-
-#ifdef notdef
-/*
- * Set a VLAN tag in the receive filter.
- */
-int sf_setvlan(sc, idx, vlan)
-	struct sf_softc		*sc;
-	int			idx;
-	u_int32_t		vlan;
-{
-	if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
-		return(EINVAL);
-
-	csr_write_4(sc, SF_RXFILT_HASH_BASE +
-	    (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
-
-	return(0);
-}
-#endif
-
-int sf_miibus_readreg(self, phy, reg)
-	struct device		*self;
-	int			phy, reg;
-{
-	struct sf_softc		*sc = (struct sf_softc *)self;
-	int			i;
-	u_int32_t		val = 0;
-
-	for (i = 0; i < SF_TIMEOUT; i++) {
-		val = csr_read_4(sc, SF_PHY_REG(phy, reg));
-		if (val & SF_MII_DATAVALID)
-			break;
-	}
-
-	if (i == SF_TIMEOUT)
-		return(0);
-
-	if ((val & 0x0000FFFF) == 0xFFFF)
-		return(0);
-
-	return(val & 0x0000FFFF);
-}
-
-void sf_miibus_writereg(self, phy, reg, val)
-	struct device		*self;
-	int phy, reg, val;
-{
-	struct sf_softc		*sc = (struct sf_softc *)self;
-	int			i;
-	int			busy;
-
-	csr_write_4(sc, SF_PHY_REG(phy, reg), val);
-
-	for (i = 0; i < SF_TIMEOUT; i++) {
-		busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
-		if (!(busy & SF_MII_BUSY))
-			break;
-	}
-
-	return;
-}
-
-void sf_miibus_statchg(self)
-	struct device		*self;
-{
-	struct sf_softc		*sc = (struct sf_softc *)self;
-	struct mii_data		*mii;
-
-	mii = &sc->sc_mii;
-
-	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
-		SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
-		csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
-	} else {
-		SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
-		csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
-	}
-
-	return;
-}
-
-void sf_setmulti(sc)
-	struct sf_softc		*sc;
-{
-	struct ifnet		*ifp;
-	int			i;
-	struct arpcom		*ac = &sc->arpcom;
-	struct ether_multi	*enm;
-	struct ether_multistep	step;
-	u_int8_t		dummy[] = { 0, 0, 0, 0, 0, 0 };
-
-	ifp = &sc->arpcom.ac_if;
-
-	/* First zot all the existing filters. */
-	for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
-		sf_setperf(sc, i, (char *)&dummy);
-	for (i = SF_RXFILT_HASH_BASE;
-	    i < (SF_RXFILT_HASH_MAX + 1); i += 4)
-		csr_write_4(sc, i, 0);
-	SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
-
-	/* Now program new ones. */
-allmulti:
-	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
-		SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
-	} else {
-		i = 1;
-		/* First find the tail of the list. */
-		ETHER_FIRST_MULTI(step, ac, enm);
-
-		/* Now traverse the list backwards. */
-		while (enm != NULL) {
-			if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
-			    ETHER_ADDR_LEN)) {
-				ifp->if_flags |= IFF_ALLMULTI;
-				goto allmulti;
-			}
-
-			/* if (enm->enm_addrlo->sa_family != AF_LINK)
-				continue; */
-			/*
-			 * Program the first 15 multicast groups
-			 * into the perfect filter. For all others,
-			 * use the hash table.
-			 */
-			if (i < SF_RXFILT_PERFECT_CNT) {
-				sf_setperf(sc, i, enm->enm_addrlo);
-				i++;
-				continue;
-			}
-
-			sf_sethash(sc, enm->enm_addrlo, 0);
-			ETHER_NEXT_MULTI(step, enm);
-		}
-	}
-
-	return;
-}
-
-/*
- * Set media options.
- */
-int sf_ifmedia_upd(ifp)
-	struct ifnet		*ifp;
-{
-	struct sf_softc		*sc;
-	struct mii_data		*mii;
-
-	sc = ifp->if_softc;
-	mii = &sc->sc_mii;
-	sc->sf_link = 0;
-	if (mii->mii_instance) {
-		struct mii_softc	*miisc;
-		LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
-			mii_phy_reset(miisc);
-	}
-	mii_mediachg(mii);
-
-	return(0);
-}
-
-/*
- * Report current media status.
- */
-void sf_ifmedia_sts(ifp, ifmr)
-	struct ifnet		*ifp;
-	struct ifmediareq	*ifmr;
-{
-	struct sf_softc		*sc;
-	struct mii_data		*mii;
-
-	sc = ifp->if_softc;
-	mii = &sc->sc_mii;
-
-	mii_pollstat(mii);
-	ifmr->ifm_active = mii->mii_media_active;
-	ifmr->ifm_status = mii->mii_media_status;
-
-	return;
-}
-
-int sf_ioctl(ifp, command, data)
-	struct ifnet		*ifp;
-	u_long			command;
-	caddr_t			data;
-{
-	struct sf_softc		*sc = ifp->if_softc;
-	struct ifreq		*ifr = (struct ifreq *) data;
-	struct ifaddr		*ifa = (struct ifaddr *)data;
-	struct mii_data		*mii;
-	int			s, error = 0;
-
-	s = splnet();
-
-	if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
-		splx(s);
-		return error;
-	}
-
-	switch(command) {
-	case SIOCSIFADDR:
-		ifp->if_flags |= IFF_UP;
-		switch (ifa->ifa_addr->sa_family) {
-		case AF_INET:
-			sf_init(sc);
-			arp_ifinit(&sc->arpcom, ifa);
-			break;
-		default:
-			sf_init(sc);
-			break;
-		}
-		break;
-	case SIOCSIFFLAGS:
-		if (ifp->if_flags & IFF_UP) {
-			if (ifp->if_flags & IFF_RUNNING &&
-			    ifp->if_flags & IFF_PROMISC &&
-			    !(sc->sf_if_flags & IFF_PROMISC)) {
-				SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
-			} else if (ifp->if_flags & IFF_RUNNING &&
-			    !(ifp->if_flags & IFF_PROMISC) &&
-			    sc->sf_if_flags & IFF_PROMISC) {
-				SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
-			} else if (!(ifp->if_flags & IFF_RUNNING))
-				sf_init(sc);
-		} else {
-			if (ifp->if_flags & IFF_RUNNING)
-				sf_stop(sc);
-		}
-		sc->sf_if_flags = ifp->if_flags;
-		error = 0;
-		break;
-	case SIOCADDMULTI:
-	case SIOCDELMULTI:
-		error = (command == SIOCADDMULTI) ?
-		    ether_addmulti(ifr, &sc->arpcom) :
-		    ether_delmulti(ifr, &sc->arpcom);
-
-		if (error == ENETRESET) {
-			/*
-			 * Multicast list has changed; set the hardware
-			 * filter accordingly.
-			 */
-			if (ifp->if_flags & IFF_RUNNING)
-				sf_setmulti(sc);
-			error = 0;
-		}
-		break;
-	case SIOCGIFMEDIA:
-	case SIOCSIFMEDIA:
-		mii = &sc->sc_mii;
-		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
-		break;
-	default:
-		error = ENOTTY;
-		break;
-	}
-
-	splx(s);
-
-	return(error);
-}
-
-void sf_reset(sc)
-	struct sf_softc		*sc;
-{
-	int			i;
-
-	csr_write_4(sc, SF_GEN_ETH_CTL, 0);
-	SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
-	DELAY(1000);
-	SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
-
-	SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
-
-	for (i = 0; i < SF_TIMEOUT; i++) {
-		DELAY(10);
-		if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
-			break;
-	}
-
-	if (i == SF_TIMEOUT)
-		printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);
-
-	/* Wait a little while for the chip to get its brains in order. */
-	DELAY(1000);
-	return;
-}
-
-/*
- * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
- * IDs against our list and return a device name if we find a match.
- * We also check the subsystem ID so that we can identify exactly which
- * NIC has been found, if possible.
- */
-int sf_probe(parent, match, aux)
-	struct device		*parent;
-	void			*match;
-	void			*aux;
-{
-	struct pci_attach_args	*pa = (struct pci_attach_args *)aux;
-
-	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADP &&
-	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADP_AIC6915)
-		return(1);
-
-	return(0);
-}
-
-/*
- * Attach the interface. Allocate softc structures, do ifmedia
- * setup and ethernet/BPF attach.
- */
-void sf_attach(parent, self, aux)
-	struct device		*parent, *self;
-	void			*aux;
-{
-	int			i;
-	const char		*intrstr = NULL;
-	u_int32_t		command;
-	struct sf_softc		*sc = (struct sf_softc *)self;
-	struct pci_attach_args	*pa = aux;
-	pci_chipset_tag_t	pc = pa->pa_pc;
-	pci_intr_handle_t	ih;
-	struct ifnet		*ifp;
-	bus_size_t		size;
-
-	/*
-	 * Handle power management nonsense.
-	 */
-	command = pci_conf_read(pc, pa->pa_tag, SF_PCI_CAPID) & 0x000000FF;
-	if (command == 0x01) {
-
-		command = pci_conf_read(pc, pa->pa_tag, SF_PCI_PWRMGMTCTRL);
-		if (command & SF_PSTATE_MASK) {
-			u_int32_t		iobase, membase, irq;
-
-			/* Save important PCI config data. */
-			iobase = pci_conf_read(pc, pa->pa_tag, SF_PCI_LOIO);
-			membase = pci_conf_read(pc, pa->pa_tag, SF_PCI_LOMEM);
-			irq = pci_conf_read(pc, pa->pa_tag, SF_PCI_INTLINE);
-
-			/* Reset the power state. */
-			printf("%s: chip is in D%d power mode -- setting to D0\n",
-				sc->sc_dev.dv_xname, command & SF_PSTATE_MASK);
-			command &= 0xFFFFFFFC;
-			pci_conf_write(pc, pa->pa_tag, SF_PCI_PWRMGMTCTRL, command);
-
-			/* Restore PCI config data. */
-			pci_conf_write(pc, pa->pa_tag, SF_PCI_LOIO, iobase);
-			pci_conf_write(pc, pa->pa_tag, SF_PCI_LOMEM, membase);
-			pci_conf_write(pc, pa->pa_tag, SF_PCI_INTLINE, irq);
-		}
-	}
-
-	/*
-	 * Map control/status registers.
-	 */
-
-#ifdef SF_USEIOSPACE
-	if (pci_mapreg_map(pa, SF_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
-	    &sc->sf_btag, &sc->sf_bhandle, NULL, &size, 0)) {
-		printf(": can't map I/O space\n");
-		return;
-	}
-#else
-	if (pci_mapreg_map(pa, SF_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
-	    &sc->sf_btag, &sc->sf_bhandle, NULL, &size, 0)){
-		printf(": can't map mem space\n");
-		return;
-	}
-#endif
-
-	/* Allocate interrupt */
-	if (pci_intr_map(pa, &ih)) {
-		printf(": couldn't map interrupt\n");
-		goto fail_1;
-	}
-	intrstr = pci_intr_string(pc, ih);
-	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sf_intr, sc,
-	    self->dv_xname);
-	if (sc->sc_ih == NULL) {
-		printf(": couldn't establish interrupt");
-		if (intrstr != NULL)
-			printf(" at %s", intrstr);
-		printf("\n");
-		goto fail_1;
-	}
-	printf(": %s", intrstr);
-
-	/* Reset the adapter. */
-	sf_reset(sc);
-
-	/*
-	 * Get station address from the EEPROM.
-	 */
-	for (i = 0; i < ETHER_ADDR_LEN; i++)
-		sc->arpcom.ac_enaddr[i] =
-		    sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
-
-	printf(", address %s\n", ether_sprintf(sc->arpcom.ac_enaddr));
-
-	/* Allocate the descriptor queues. */
-	sc->sf_ldata_ptr = malloc(sizeof(struct sf_list_data) + 8,
-				M_DEVBUF, M_NOWAIT);
-	if (sc->sf_ldata_ptr == NULL) {
-		printf(": no memory for list buffers!\n");
-		goto fail_2;
-	}
-
-	sc->sf_ldata = (struct sf_list_data *)sc->sf_ldata_ptr;
-	bzero(sc->sf_ldata, sizeof(struct sf_list_data));
-
-	ifp = &sc->arpcom.ac_if;
-	ifp->if_softc = sc;
-	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
-	ifp->if_ioctl = sf_ioctl;
-	ifp->if_start = sf_start;
-	ifp->if_watchdog = sf_watchdog;
-	ifp->if_baudrate = 10000000;
-	IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
-	IFQ_SET_READY(&ifp->if_snd);
-	bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
-
-	/*
-	 * Initialize our media structures and probe the MII.
-	 */
-	sc->sc_mii.mii_ifp = ifp;
-	sc->sc_mii.mii_readreg = sf_miibus_readreg;
-	sc->sc_mii.mii_writereg = sf_miibus_writereg;
-	sc->sc_mii.mii_statchg = sf_miibus_statchg;
-	ifmedia_init(&sc->sc_mii.mii_media, 0, sf_ifmedia_upd, sf_ifmedia_sts);
-	mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY,
-	    0);
-	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
-		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
-		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
-	} else
-		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
-
-	/*
-	 * Call MI attach routines.
-	 */
-	if_attach(ifp);
-	ether_ifattach(ifp);
-
-	shutdownhook_establish(sf_shutdown, sc);
-	return;
-
-fail_2:
-	pci_intr_disestablish(pc, sc->sc_ih);
-
-fail_1:
-	bus_space_unmap(sc->sf_btag, sc->sf_bhandle, size);
-}
-
-int sf_init_rx_ring(sc)
-	struct sf_softc		*sc;
-{
-	struct sf_list_data	*ld;
-	int			i;
-
-	ld = sc->sf_ldata;
-
-	bzero((char *)ld->sf_rx_dlist_big,
-	    sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
-	bzero((char *)ld->sf_rx_clist,
-	    sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
-
-	for (i = 0; i < SF_RX_DLIST_CNT; i++) {
-		if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
-			return(ENOBUFS);
-	}
-
-	return(0);
-}
-
-void sf_init_tx_ring(sc)
-	struct sf_softc		*sc;
-{
-	struct sf_list_data	*ld;
-	int			i;
-
-	ld = sc->sf_ldata;
-
-	bzero((char *)ld->sf_tx_dlist,
-	    sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
-	bzero((char *)ld->sf_tx_clist,
-	    sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
-
-	for (i = 0; i < SF_TX_DLIST_CNT; i++)
-		ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
-	for (i = 0; i < SF_TX_CLIST_CNT; i++)
-		ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
-
-	ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
-	sc->sf_tx_cnt = 0;
-
-	return;
-}
-
-int sf_newbuf(sc, c, m)
-	struct sf_softc		*sc;
-	struct sf_rx_bufdesc_type0	*c;
-	struct mbuf		*m;
-{
-	struct mbuf		*m_new = NULL;
-
-	if (m == NULL) {
-		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
-		if (m_new == NULL)
-			return(ENOBUFS);
-
-		MCLGET(m_new, M_DONTWAIT);
-		if (!(m_new->m_flags & M_EXT)) {
-			m_freem(m_new);
-			return(ENOBUFS);
-		}
-		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
-	} else {
-		m_new = m;
-		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
-		m_new->m_data = m_new->m_ext.ext_buf;
-	}
-
-	m_adj(m_new, sizeof(u_int64_t));
-
-	c->sf_mbuf = m_new;
-	c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, vaddr_t)));
-	c->sf_valid = 1;
-
-	return(0);
-}
-
-/*
- * The starfire is programmed to use 'normal' mode for packet reception,
- * which means we use the consumer/producer model for both the buffer
- * descriptor queue and the completion descriptor queue. The only problem
- * with this is that it involves a lot of register accesses: we have to
- * read the RX completion consumer and producer indexes and the RX buffer
- * producer index, plus the RX completion consumer and RX buffer producer
- * indexes have to be updated. It would have been easier if Adaptec had
- * put each index in a separate register, especially given that the damn
- * NIC has a 512K register space.
- *
- * In spite of all the lovely features that Adaptec crammed into the 6915,
- * it is marred by one truly stupid design flaw, which is that receive
- * buffer addresses must be aligned on a longword boundary. This forces
- * the packet payload to be unaligned, which is suboptimal on the x86 and
- * completely unuseable on the Alpha. Our only recourse is to copy received
- * packets into properly aligned buffers before handing them off.
- */
-
-void sf_rxeof(sc)
-	struct sf_softc		*sc;
-{
-	struct mbuf		*m;
-	struct ifnet		*ifp;
-	struct sf_rx_bufdesc_type0	*desc;
-	struct sf_rx_cmpdesc_type3	*cur_rx;
-	u_int32_t		rxcons, rxprod;
-	int			cmpprodidx, cmpconsidx, bufprodidx;
-
-	ifp = &sc->arpcom.ac_if;
-
-	rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
-	rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
-	cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
-	cmpconsidx = SF_IDX_LO(rxcons);
-	bufprodidx = SF_IDX_LO(rxprod);
-
-	while (cmpconsidx != cmpprodidx) {
-		struct mbuf		*m0;
-
-		cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
-		desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
-		m = desc->sf_mbuf;
-		SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
-		SF_INC(bufprodidx, SF_RX_DLIST_CNT);
-
-		if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
-			ifp->if_ierrors++;
-			sf_newbuf(sc, desc, m);
-			continue;
-		}
-
-		m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
-		    cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
-		sf_newbuf(sc, desc, m);
-		if (m0 == NULL) {
-			ifp->if_ierrors++;
-			continue;
-		}
-		m_adj(m0, ETHER_ALIGN);
-		m = m0;
-
-		ifp->if_ipackets++;
-
-#if NBPFILTER > 0
-		if (ifp->if_bpf)
-			bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
-#endif
-
-		/* pass it on. */
-		ether_input_mbuf(ifp, m);
-	}
-
-	csr_write_4(sc, SF_CQ_CONSIDX,
-	    (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
-	csr_write_4(sc, SF_RXDQ_PTR_Q1,
-	    (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
-
-	return;
-}
-
-/*
- * Read the transmit status from the completion queue and release
- * mbufs. Note that the buffer descriptor index in the completion
- * descriptor is an offset from the start of the transmit buffer
- * descriptor list in bytes. This is important because the manual
- * gives the impression that it should match the producer/consumer
- * index, which is the offset in 8 byte blocks.
- */
-void sf_txeof(sc)
-	struct sf_softc		*sc;
-{
-	int			txcons, cmpprodidx, cmpconsidx;
-	struct sf_tx_cmpdesc_type1 *cur_cmp;
-	struct sf_tx_bufdesc_type0 *cur_tx;
-	struct ifnet		*ifp;
-
-	ifp = &sc->arpcom.ac_if;
-
-	txcons = csr_read_4(sc, SF_CQ_CONSIDX);
-	cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
-	cmpconsidx = SF_IDX_HI(txcons);
-
-	while (cmpconsidx != cmpprodidx) {
-		cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
-		cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
-
-		if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
-			ifp->if_opackets++;
-		else {
-			if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
-				sf_txthresh_adjust(sc);
-			ifp->if_oerrors++;
-		}
-
-		sc->sf_tx_cnt--;
-		if (cur_tx->sf_mbuf != NULL) {
-			m_freem(cur_tx->sf_mbuf);
-			cur_tx->sf_mbuf = NULL;
-		} else
-			break;
-		SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
-	}
-
-	ifp->if_timer = 0;
-	ifp->if_flags &= ~IFF_OACTIVE;
-
-	csr_write_4(sc, SF_CQ_CONSIDX,
-	    (txcons & ~SF_CQ_CONSIDX_TXQ) |
-	    ((cmpconsidx << 16) & 0xFFFF0000));
-
-	return;
-}
-
-void
-sf_txthresh_adjust(sc)
-	struct sf_softc *sc;
-{
-	u_int32_t txfctl;
-	u_int8_t txthresh;
-
-	txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
-	txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
-	if (txthresh < 0xFF) {
-		txthresh++;
-		txfctl &= ~SF_TXFRMCTL_TXTHRESH;
-		txfctl |= txthresh;
-#ifdef SF_DEBUG
-		printf("%s: tx underrun, increasing tx threshold to %d bytes\n",
-		    sc->sc_dev.dv_xname, txthresh * 4);
-#endif
-		csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
-	}
-
-	return;
-}
-
-int sf_intr(arg)
-	void			*arg;
-{
-	struct sf_softc		*sc;
-	struct ifnet		*ifp;
-	u_int32_t		status;
-	int			claimed = 0;
-
-	sc = arg;
-	ifp = &sc->arpcom.ac_if;
-
-	if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
-		return claimed;
-
-	/* Disable interrupts. */
-	csr_write_4(sc, SF_IMR, 0x00000000);
-
-	for (;;) {
-		status = csr_read_4(sc, SF_ISR);
-		if (status)
-			csr_write_4(sc, SF_ISR, status);
-
-		if (!(status & SF_INTRS))
-			break;
-
-		claimed = 1;
-
-		if (status & SF_ISR_RXDQ1_DMADONE)
-			sf_rxeof(sc);
-
-		if (status & SF_ISR_TX_TXDONE ||
-		    status & SF_ISR_TX_DMADONE ||
-		    status & SF_ISR_TX_QUEUEDONE ||
-		    status & SF_ISR_TX_LOFIFO)
-			sf_txeof(sc);
-
-		if (status & SF_ISR_TX_LOFIFO)
-			sf_txthresh_adjust(sc);
-
-		if (status & SF_ISR_ABNORMALINTR) {
-			if (status & SF_ISR_STATSOFLOW) {
-				timeout_del(&sc->sc_stats_tmo);
-				sf_stats_update(sc);
-			} else
-				sf_init(sc);
-		}
-	}
-
-	/* Re-enable interrupts. */
-	csr_write_4(sc, SF_IMR, SF_INTRS);
-
-	if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
-		sf_start(ifp);
-
-	return claimed;
-}
-
-void sf_init(xsc)
-	void			*xsc;
-{
-	struct sf_softc		*sc = xsc;
-	struct ifnet		*ifp = &sc->arpcom.ac_if;
-	struct mii_data		*mii;
-	int			i, s;
-
-	s = splnet();
-
-	mii = &sc->sc_mii;
-
-	sf_stop(sc);
-	sf_reset(sc);
-
-	/* Init all the receive filter registers */
-	for (i = SF_RXFILT_PERFECT_BASE;
-	    i < (SF_RXFILT_HASH_MAX + 1); i += 4)
-		csr_write_4(sc, i, 0);
-
-	/* Empty stats counter registers. */
-	for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
-		csr_write_4(sc, SF_STATS_BASE +
-		    (i + sizeof(u_int32_t)), 0);
-
-	/* Init our MAC address */
-	csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
-	csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
-	sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
-
-	if (sf_init_rx_ring(sc) == ENOBUFS) {
-		printf("%s: initialization failed: no "
-		    "memory for rx buffers\n", sc->sc_dev.dv_xname);
-		splx(s);
-		return;
-	}
-
-	sf_init_tx_ring(sc);
-
-	csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
-
-	/* If we want promiscuous mode, set the allframes bit. */
-	if (ifp->if_flags & IFF_PROMISC) {
-		SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
-	} else {
-		SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
-	}
-
-	if (ifp->if_flags & IFF_BROADCAST) {
-		SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
-	} else {
-		SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
-	}
-
-	/*
-	 * Load the multicast filter.
-	 */
-	sf_setmulti(sc);
-
-	/* Init the completion queue indexes */
-	csr_write_4(sc, SF_CQ_CONSIDX, 0);
-	csr_write_4(sc, SF_CQ_PRODIDX, 0);
-
-	/* Init the RX completion queue */
-	csr_write_4(sc, SF_RXCQ_CTL_1,
-	    vtophys((vaddr_t)sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
-	SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
-
-	/* Init RX DMA control. */
-	SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
-
-	/* Init the RX buffer descriptor queue. */
-	csr_write_4(sc, SF_RXDQ_ADDR_Q1,
-	    vtophys((vaddr_t)sc->sf_ldata->sf_rx_dlist_big));
-	csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
-	csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
-
-	/* Init the TX completion queue */
-	csr_write_4(sc, SF_TXCQ_CTL,
-	    vtophys((vaddr_t)sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
-
-	/* Init the TX buffer descriptor queue. */
-	csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
-		vtophys((vaddr_t)sc->sf_ldata->sf_tx_dlist));
-	SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
-	csr_write_4(sc, SF_TXDQ_CTL,
-	    SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
-	SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
-
-	/* Enable autopadding of short TX frames. */
-	SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
-
-	/* Enable interrupts. */
-	csr_write_4(sc, SF_IMR, SF_INTRS);
-	SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
-
-	/* Enable the RX and TX engines. */
-	SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
-	SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
-
-	sf_ifmedia_upd(ifp);
-
-	ifp->if_flags |= IFF_RUNNING;
-	ifp->if_flags &= ~IFF_OACTIVE;
-
-	splx(s);
-
-	timeout_set(&sc->sc_stats_tmo, sf_stats_update, sc);
-	timeout_add(&sc->sc_stats_tmo, hz);
-
-	return;
-}
-
-int sf_encap(sc, c, m_head)
-	struct sf_softc		*sc;
-	struct sf_tx_bufdesc_type0 *c;
-	struct mbuf		*m_head;
-{
-	int			frag = 0;
-	struct sf_frag		*f = NULL;
-	struct mbuf		*m;
-
-	m = m_head;
-
-	for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
-		if (m->m_len != 0) {
-			if (frag == SF_MAXFRAGS)
-				break;
-			f = &c->sf_frags[frag];
-			if (frag == 0)
-				f->sf_pktlen = m_head->m_pkthdr.len;
-			f->sf_fraglen = m->m_len;
-			f->sf_addr = vtophys(mtod(m, vaddr_t));
-			frag++;
-		}
-	}
-
-	if (m != NULL) {
-		struct mbuf		*m_new = NULL;
-
-		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
-		if (m_new == NULL) {
-			printf("%s: no memory for tx list\n",
-			    sc->sc_dev.dv_xname);
-			return(1);
-		}
-
-		if (m_head->m_pkthdr.len > MHLEN) {
-			MCLGET(m_new, M_DONTWAIT);
-			if (!(m_new->m_flags & M_EXT)) {
-				m_freem(m_new);
-				printf("%s: no memory for tx list\n",
-				    sc->sc_dev.dv_xname);
-				return(1);
-			}
-		}
-		m_copydata(m_head, 0, m_head->m_pkthdr.len,
-		    mtod(m_new, caddr_t));
-		m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
-		m_freem(m_head);
-		m_head = m_new;
-		f = &c->sf_frags[0];
-		f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
-		f->sf_addr = vtophys(mtod(m_head, vaddr_t));
-		frag = 1;
-	}
-
-	c->sf_mbuf = m_head;
-	c->sf_id = SF_TX_BUFDESC_ID;
-	c->sf_fragcnt = frag;
-	c->sf_intr = 1;
-	c->sf_caltcp = 0;
-	c->sf_crcen = 1;
-
-	return(0);
-}
-
-void sf_start(ifp)
-	struct ifnet		*ifp;
-{
-	struct sf_softc		*sc;
-	struct sf_tx_bufdesc_type0 *cur_tx = NULL;
-	struct mbuf		*m_head = NULL;
-	int			i, txprod;
-
-	sc = ifp->if_softc;
-
-	if (!sc->sf_link && ifp->if_snd.ifq_len < 10)
-		return;
-
-	if (ifp->if_flags & IFF_OACTIVE)
-		return;
-
-	txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
-	i = SF_IDX_HI(txprod) >> 4;
-
-	if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
-		printf("%s: TX ring full, resetting\n", sc->sc_dev.dv_xname);
-		sf_init(sc);
-		txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
-		i = SF_IDX_HI(txprod) >> 4;
-	}
-
-	while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
-		if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
-			ifp->if_flags |= IFF_OACTIVE;
-			cur_tx = NULL;
-			break;
-		}
-		IFQ_DEQUEUE(&ifp->if_snd, m_head);
-		if (m_head == NULL)
-			break;
-
-		cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
-		if (sf_encap(sc, cur_tx, m_head)) {
-			m_freem(m_head);
-			continue;
-		}
-
-#if NBPFILTER > 0
-		/*
-		 * If there's a BPF listener, bounce a copy of this frame
-		 * to him.
-		 */
-		if (ifp->if_bpf)
-			bpf_mtap(ifp->if_bpf, cur_tx->sf_mbuf,
-			    BPF_DIRECTION_OUT);
-#endif
-
-		SF_INC(i, SF_TX_DLIST_CNT);
-		sc->sf_tx_cnt++;
-		/*
-		 * Don't let the TX DMA queue get too full.
-		 */
-		if (sc->sf_tx_cnt > 64)
-			break;
-	}
-
-	if (cur_tx == NULL)
-		return;
-
-	/* Transmit */
-	csr_write_4(sc, SF_TXDQ_PRODIDX,
-	    (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
-	    ((i << 20) & 0xFFFF0000));
-
-	ifp->if_timer = 5;
-
-	return;
-}
-
-void sf_stop(sc)
-	struct sf_softc		*sc;
-{
-	int			i;
-	struct ifnet		*ifp;
-
-	ifp = &sc->arpcom.ac_if;
-
-	timeout_del(&sc->sc_stats_tmo);
-
-	ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
-
-	csr_write_4(sc, SF_GEN_ETH_CTL, 0);
-	csr_write_4(sc, SF_CQ_CONSIDX, 0);
-	csr_write_4(sc, SF_CQ_PRODIDX, 0);
-	csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
-	csr_write_4(sc, SF_RXDQ_CTL_1, 0);
-	csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
-	csr_write_4(sc, SF_TXCQ_CTL, 0);
-	csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
-	csr_write_4(sc, SF_TXDQ_CTL, 0);
-	sf_reset(sc);
-
-	sc->sf_link = 0;
-
-	for (i = 0; i < SF_RX_DLIST_CNT; i++) {
-		if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
-			m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
-			sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
-		}
-	}
-
-	for (i = 0; i < SF_TX_DLIST_CNT; i++) {
-		if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
-			m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
-			sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
-		}
-	}
-
-	return;
-}
-
-/*
- * Note: it is important that this function not be interrupted. We
- * use a two-stage register access scheme: if we are interrupted in
- * between setting the indirect address register and reading from the
- * indirect data register, the contents of the address register could
- * be changed out from under us.
- */     
-void sf_stats_update(xsc)
-	void			*xsc;
-{
-	struct sf_softc		*sc;
-	struct ifnet		*ifp;
-	struct mii_data		*mii;
-	struct sf_stats		stats;
-	u_int32_t		*ptr;
-	int			i, s;
-
-	s = splnet();
-
-	sc = xsc;
-	ifp = &sc->arpcom.ac_if;
-	mii = &sc->sc_mii;
-
-	ptr = (u_int32_t *)&stats;
-	for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
-		ptr[i] = csr_read_4(sc, SF_STATS_BASE +
-		    (i + sizeof(u_int32_t)));
-
-	for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
-		csr_write_4(sc, SF_STATS_BASE +
-		    (i + sizeof(u_int32_t)), 0);
-
-	ifp->if_collisions += stats.sf_tx_single_colls +
-	    stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
-
-	mii_tick(mii);
-	if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE &&
-	    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
-		sc->sf_link++;
-		if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
-			sf_start(ifp);
-	}
-
-	splx(s);
-
-	timeout_add(&sc->sc_stats_tmo, hz);
-
-	return;
-}
-
-void sf_watchdog(ifp)
-	struct ifnet		*ifp;
-{
-	struct sf_softc		*sc;
-
-	sc = ifp->if_softc;
-
-	ifp->if_oerrors++;
-	printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
-
-	sf_stop(sc);
-	sf_reset(sc);
-	sf_init(sc);
-
-	if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
-		sf_start(ifp);
-
-	return;
-}
-
-void sf_shutdown(v)
-	void			*v;
-{
-	struct sf_softc		*sc = (struct sf_softc *)v;
-	
-	sf_stop(sc);
-}
-
-struct cfattach sf_ca = {
-	sizeof(struct sf_softc), sf_probe, sf_attach
-};
-
-struct cfdriver sf_cd = {
-	0, "sf", DV_IFNET
-};
-
diff --git a/sys/dev/pci/if_sf_pci.c b/sys/dev/pci/if_sf_pci.c
new file mode 100644
index 00000000000..483b3963402
--- /dev/null
+++ b/sys/dev/pci/if_sf_pci.c
@@ -0,0 +1,289 @@
+/*	$OpenBSD: if_sf_pci.c,v 1.1 2006/12/06 20:07:52 martin Exp $	*/
+/*	$NetBSD: if_sf_pci.c,v 1.10 2006/06/17 23:34:27 christos Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * PCI bus front-end for the Adaptec AIC-6915 (``Starfire'')
+ * 10/100 Ethernet controller.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/ioctl.h>
+#include <sys/errno.h>
+#include <sys/device.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_types.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <net/if_media.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/mii/miivar.h>
+
+#include <dev/ic/aic6915.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+struct sf_pci_softc {
+	struct sf_softc sc_starfire;	/* read Starfire softc */
+
+	/* PCI-specific goo. */
+	void	*sc_ih;			/* interrupt handle */
+};
+
+static int	sf_pci_match(struct device *, void *, void *);
+static void	sf_pci_attach(struct device *, struct device *, void *);
+
+struct cfattach sf_pci_ca = {
+        sizeof(struct sf_pci_softc), sf_pci_match, sf_pci_attach
+};
+
+struct sf_pci_product {
+	uint32_t	spp_vendor;	/* PCI vendor ID */
+	uint32_t	spp_product;	/* PCI product ID */
+	const char	*spp_name;	/* product name */
+	const struct sf_pci_product *spp_subsys; /* subsystm IDs */
+};
+
+static const struct sf_pci_product sf_subsys_adaptec[] = {
+	/* ANA-62011 (rev 0) Single port 10/100 64-bit */
+	{ PCI_VENDOR_ADP,			0x0008,
+	  "ANA-62011 (rev 0) 10/100 Ethernet",	NULL },
+
+	/* ANA-62011 (rev 1) Single port 10/100 64-bit */
+	{ PCI_VENDOR_ADP,			0x0009,
+	  "ANA-62011 (rev 1) 10/100 Ethernet",	NULL },
+
+	/* ANA-62022 Dual port 10/100 64-bit */
+	{ PCI_VENDOR_ADP,			0x0010,
+	  "ANA-62022 10/100 Ethernet",		NULL },
+
+	/* ANA-62044 (rev 0) Quad port 10/100 64-bit */
+	{ PCI_VENDOR_ADP,			0x0018,
+	  "ANA-62044 (rev 0) 10/100 Ethernet",	NULL },
+
+	/* ANA-62044 (rev 1) Quad port 10/100 64-bit */
+	{ PCI_VENDOR_ADP,			0x0019,
+	  "ANA-62044 (rev 1) 10/100 Ethernet",	NULL },
+
+	/* ANA-62020 Single port 100baseFX 64-bit */
+	{ PCI_VENDOR_ADP,			0x0020,
+	  "ANA-62020 100baseFX Ethernet",	NULL },
+
+	/* ANA-69011 Single port 10/100 32-bit */
+	{ PCI_VENDOR_ADP,			0x0028,
+	  "ANA-69011 10/100 Ethernet",		NULL },
+
+	{ 0, 					0,
+	  NULL,					NULL },
+};
+
+static const struct sf_pci_product sf_pci_products[] = {
+	{ PCI_VENDOR_ADP,			PCI_PRODUCT_ADP_AIC6915,
+	  "AIC-6915 10/100 Ethernet",		sf_subsys_adaptec },
+
+	{ 0,					0,
+	  NULL,					NULL },
+};
+
+static const struct sf_pci_product *
+sf_pci_lookup(const struct pci_attach_args *pa)
+{
+	const struct sf_pci_product *spp, *subspp;
+	pcireg_t subsysid;
+
+	for (spp = sf_pci_products; spp->spp_name != NULL; spp++) {
+		if (PCI_VENDOR(pa->pa_id) == spp->spp_vendor &&
+		    PCI_PRODUCT(pa->pa_id) == spp->spp_product) {
+			subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag,
+			    PCI_SUBSYS_ID_REG);
+			for (subspp = spp->spp_subsys;
+			     subspp->spp_name != NULL; subspp++) {
+				if (PCI_VENDOR(subsysid) ==
+					subspp->spp_vendor ||
+				    PCI_PRODUCT(subsysid) ==
+					subspp->spp_product) {
+					return (subspp);
+				}
+			}
+			return (spp);
+		}
+	}
+
+	return (NULL);
+}
+
+static int
+sf_pci_match(struct device *parent, void *match, void *aux)
+{
+	struct pci_attach_args *pa = aux;
+
+	if (sf_pci_lookup(pa) != NULL)
+		return (1);
+
+	return (0);
+}
+
+static void
+sf_pci_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct sf_pci_softc *psc = (void *) self;
+	struct sf_softc *sc = &psc->sc_starfire;
+	struct pci_attach_args *pa = aux;
+	pci_intr_handle_t ih;
+	const char *intrstr = NULL;
+	const struct sf_pci_product *spp;
+	bus_space_tag_t iot, memt;
+	bus_space_handle_t ioh, memh;
+	pcireg_t reg;
+	int pmreg, ioh_valid, memh_valid;
+
+	spp = sf_pci_lookup(pa);
+	if (spp == NULL) {
+		printf("\n");
+		panic("sf_pci_attach: impossible");
+	}
+
+	printf(": %s, rev. %d", spp->spp_name, PCI_REVISION(pa->pa_class));
+
+	if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT,
+	    &pmreg, 0)) {
+		reg = pci_conf_read(pa->pa_pc, pa->pa_tag, pmreg + PCI_PMCSR);
+		switch (reg & PCI_PMCSR_STATE_MASK) {
+		case PCI_PMCSR_STATE_D1:
+		case PCI_PMCSR_STATE_D2:
+			printf(": waking up from power state D%d\n%s",
+			    reg & PCI_PMCSR_STATE_MASK, sc->sc_dev.dv_xname);
+			pci_conf_write(pa->pa_pc, pa->pa_tag, pmreg + PCI_PMCSR,
+			    (reg & ~PCI_PMCSR_STATE_MASK) |
+			    PCI_PMCSR_STATE_D0);
+			break;
+
+		case PCI_PMCSR_STATE_D3:
+			printf("%s: unable to wake up from power state D3\n",
+			    sc->sc_dev.dv_xname);
+			pci_conf_write(pa->pa_pc, pa->pa_tag, pmreg + PCI_PMCSR,
+			    (reg & ~PCI_PMCSR_STATE_MASK) |
+			    PCI_PMCSR_STATE_D0);
+			return;
+		}
+	}
+
+	/*
+	 * Map the device.
+	 */
+	reg = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SF_PCI_MEMBA);
+	switch (reg) {
+	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
+	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
+		memh_valid = (pci_mapreg_map(pa, SF_PCI_MEMBA,
+		    reg, 0, &memt, &memh, NULL, NULL, 0) == 0);
+		break;
+	default:
+		memh_valid = 0;
+	}
+
+	ioh_valid = (pci_mapreg_map(pa,
+	    (reg == (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT)) ?
+		SF_PCI_IOBA : SF_PCI_IOBA - 0x04,
+	    PCI_MAPREG_TYPE_IO, 0,
+	    &iot, &ioh, NULL, NULL, 0) == 0);
+
+	if (memh_valid) {
+		sc->sc_st = memt;
+		sc->sc_sh = memh;
+		sc->sc_iomapped = 0;
+	} else if (ioh_valid) {
+		sc->sc_st = iot;
+		sc->sc_sh = ioh;
+		sc->sc_iomapped = 1;
+	} else {
+		printf("%s: unable to map device registers\n",
+		    sc->sc_dev.dv_xname);
+		return;
+	}
+
+	sc->sc_dmat = pa->pa_dmat;
+
+	/* Make sure bus mastering is enabled. */
+	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
+	    pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
+	    PCI_COMMAND_MASTER_ENABLE);
+
+	/*
+	 * Map and establish our interrupt.
+	 */
+	if (pci_intr_map(pa, &ih)) {
+		printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname);
+		return;
+	}
+	intrstr = pci_intr_string(pa->pa_pc, ih);
+	psc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET, sf_intr, sc,
+	    self->dv_xname);
+	if (psc->sc_ih == NULL) {
+		printf("%s: unable to establish interrupt",
+		    sc->sc_dev.dv_xname);
+		if (intrstr != NULL)
+			printf(" at %s", intrstr);
+		return;
+	}
+	printf(": %s", intrstr);
+
+	/*
+	 * Finish off the attach.
+	 */
+	sf_attach(sc);
+}
diff --git a/sys/dev/pci/if_sfreg.h b/sys/dev/pci/if_sfreg.h
deleted file mode 100644
index 889d29fc4a9..00000000000
--- a/sys/dev/pci/if_sfreg.h
+++ /dev/null
@@ -1,1057 +0,0 @@
-/*	$OpenBSD: if_sfreg.h,v 1.9 2005/12/17 07:31:27 miod Exp $	*/
-/*
- * Copyright (c) 1997, 1998, 1999
- *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Bill Paul.
- * 4. Neither the name of the author nor the names of any co-contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD: src/sys/pci/if_sfreg.h,v 1.6 1999/12/05 20:02:45 wpaul Exp $
- */
-
-/*
- * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K
- * register space. These registers can be accessed in the following way:
- * - PCI config registers are always accessible through PCI config space
- * - Full 512K space mapped into memory using PCI memory mapped access
- * - 256-byte I/O space mapped through PCI I/O access
- * - Full 512K space mapped through indirect I/O using PCI I/O access
- * It's possible to use either memory mapped mode or I/O mode to access
- * the registers, but memory mapped is usually the easiest. All registers
- * are 32 bits wide and must be accessed using 32-bit operations.
- */
-
-/*
- * Adaptec PCI vendor ID.
- */
-#define AD_VENDORID		0x9004
-
-/*
- * AIC-6915 PCI device ID.
- */
-#define AD_DEVICEID_STARFIRE	0x6915
-
-/*
- * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify
- * the exact kind of NIC on which the ASIC is mounted. Currently there
- * are six different variations. Note: the Adaptec manual lists code 0x28
- * for two different NICs: the 62044 and the 69011/TX. This is a typo:
- * the code for the 62044 is really 0x18.
- */
-#define AD_SUBSYSID_62011_REV0	0x0008	/* single port 10/100baseTX 64-bit */
-#define AD_SUBSYSID_62011_REV1	0x0009	/* single port 10/100baseTX 64-bit */
-#define AD_SUBSYSID_62022	0x0010	/* dual port 10/100baseTX 64-bit */
-#define AD_SUBSYSID_62044	0x0018	/* quad port 10/100baseTX 64-bit */
-#define AD_SUBSYSID_62020	0x0020	/* single port 10/100baseFX 64-bit */
-#define AD_SUBSYSID_69011	0x0028	/* single port 10/100baseTX 32-bit */
-
-/*
- * Starfire internal register space map. The entire register space
- * is available using PCI memory mapped mode. The SF_RMAP_INTREG
- * space is available using PCI I/O mode. The entire space can be
- * accessed using indirect I/O using the indirect I/O addr and
- * indirect I/O data registers located within the SF_RMAP_INTREG space.
- */
-#define SF_RMAP_ROMADDR_BASE	0x00000	/* Expansion ROM space */
-#define SF_RMAP_ROMADDR_MAX	0x3FFFF
-
-#define SF_RMAP_EXGPIO_BASE	0x40000 /* External general purpose regs */
-#define SF_RMAP_EXGPIO_MAX	0x3FFFF
-
-#define SF_RMAP_INTREG_BASE	0x50000 /* Internal functional registers */
-#define SF_RMAP_INTREG_MAX	0x500FF
-#define SF_RMAP_GENREG_BASE	0x50100 /* General purpose registers */
-#define SF_RMAP_GENREG_MAX	0x5FFFF
-
-#define SF_RMAP_FIFO_BASE	0x60000
-#define SF_RMAP_FIFO_MAX	0x6FFFF
-
-#define SF_RMAP_STS_BASE	0x70000
-#define SF_RMAP_STS_MAX		0x70083
-
-#define SF_RMAP_RSVD_BASE	0x70084
-#define SF_RMAP_RSVD_MAX	0x7FFFF
-
-/*
- * PCI config header registers, 0x0000 to 0x003F
- */
-#define SF_PCI_VENDOR_ID	0x0000
-#define SF_PCI_DEVICE_ID	0x0002
-#define SF_PCI_COMMAND		0x0004
-#define SF_PCI_STATUS		0x0006
-#define SF_PCI_REVID		0x0008
-#define SF_PCI_CLASSCODE	0x0009
-#define SF_PCI_CACHELEN		0x000C
-#define SF_PCI_LATENCY_TIMER	0x000D
-#define SF_PCI_HEADER_TYPE	0x000E
-#define SF_PCI_LOMEM		0x0010
-#define SF_PCI_LOIO		0x0014
-#define SF_PCI_SUBVEN_ID	0x002C
-#define SF_PCI_SYBSYS_ID	0x002E
-#define SF_PCI_BIOSROM		0x0030
-#define SF_PCI_INTLINE		0x003C
-#define SF_PCI_INTPIN		0x003D
-#define SF_PCI_MINGNT		0x003E
-#define SF_PCI_MINLAT		0x003F
-
-/*
- * PCI registers, 0x0040 to 0x006F
- */
-#define SF_PCI_DEVCFG		0x0040
-#define SF_BACCTL		0x0044
-#define SF_PCI_MON1		0x0048
-#define SF_PCI_MON2		0x004C
-#define SF_PCI_CAPID		0x0050 /* 8 bits */
-#define SF_PCI_NEXTPTR		0x0051 /* 8 bits */
-#define SF_PCI_PWRMGMTCAP	0x0052 /* 16 bits */
-#define SF_PCI_PWRMGMTCTRL	0x0054 /* 16 bits */
-#define SF_PCI_PME_EVENT	0x0058
-#define SF_PCI_EECTL		0x0060
-#define SF_PCI_COMPLIANCE	0x0064
-#define SF_INDIRECTIO_ADDR	0x0068
-#define SF_INDIRECTIO_DATA	0x006C
-
-#define SF_PCIDEVCFG_RESET	0x00000001
-#define SF_PCIDEVCFG_FORCE64	0x00000002
-#define SF_PCIDEVCFG_SYSTEM64	0x00000004
-#define SF_PCIDEVCFG_RSVD0	0x00000008
-#define SF_PCIDEVCFG_INCR_INB	0x00000010
-#define SF_PCIDEVCFG_ABTONPERR	0x00000020
-#define SF_PCIDEVCFG_STPONPERR	0x00000040
-#define SF_PCIDEVCFG_MR_ENB	0x00000080
-#define SF_PCIDEVCFG_FIFOTHR	0x00000F00
-#define SF_PCIDEVCFG_STPONCA	0x00001000
-#define SF_PCIDEVCFG_PCIMEN	0x00002000	/* enable PCI bus master */
-#define SF_PCIDEVCFG_LATSTP	0x00004000
-#define SF_PCIDEVCFG_BYTE_ENB	0x00008000
-#define SF_PCIDEVCFG_EECSWIDTH	0x00070000
-#define SF_PCIDEVCFG_STPMWCA	0x00080000
-#define SF_PCIDEVCFG_REGCSWIDTH	0x00700000
-#define SF_PCIDEVCFG_INTR_ENB	0x00800000
-#define SF_PCIDEVCFG_DPR_ENB	0x01000000
-#define SF_PCIDEVCFG_RSVD1	0x02000000
-#define SF_PCIDEVCFG_RSVD2	0x04000000
-#define SF_PCIDEVCFG_STA_ENB	0x08000000
-#define SF_PCIDEVCFG_RTA_ENB	0x10000000
-#define SF_PCIDEVCFG_RMA_ENB	0x20000000
-#define SF_PCIDEVCFG_SSE_ENB	0x40000000
-#define SF_PCIDEVCFG_DPE_ENB	0x80000000
-
-#define SF_BACCTL_BACDMA_ENB	0x00000001
-#define SF_BACCTL_PREFER_RXDMA	0x00000002
-#define SF_BACCTL_PREFER_TXDMA	0x00000004
-#define SF_BACCTL_SINGLE_DMA	0x00000008
-#define SF_BACCTL_SWAPMODE_DATA	0x00000030
-#define SF_BACCTL_SWAPMODE_DESC	0x000000C0
-
-#define SF_SWAPMODE_LE		0x00000000
-#define SF_SWAPMODE_BE		0x00000010
-
-#define SF_PSTATE_MASK		0x0003
-#define SF_PSTATE_D0		0x0000
-#define SF_PSTATE_D1		0x0001
-#define SF_PSTATE_D2		0x0002
-#define SF_PSTATE_D3		0x0003
-#define SF_PME_EN		0x0010
-#define SF_PME_STATUS		0x8000
-
-
-/*
- * Ethernet registers 0x0070 to 0x00FF
- */
-#define SF_GEN_ETH_CTL		0x0070
-#define SF_TIMER_CTL		0x0074
-#define SF_CURTIME		0x0078
-#define SF_ISR			0x0080
-#define SF_ISR_SHADOW		0x0084
-#define SF_IMR			0x0088
-#define SF_GPIO			0x008C
-#define SF_TXDQ_CTL		0x0090
-#define SF_TXDQ_ADDR_HIPRIO	0x0094
-#define SF_TXDQ_ADDR_LOPRIO	0x0098
-#define SF_TXDQ_ADDR_HIADDR	0x009C
-#define SF_TXDQ_PRODIDX		0x00A0
-#define SF_TXDQ_CONSIDX		0x00A4
-#define SF_TXDMA_STS1		0x00A8
-#define SF_TXDMA_STS2		0x00AC
-#define SF_TX_FRAMCTL		0x00B0
-#define SF_TXCQ_ADDR_HI		0x00B4
-#define SF_TXCQ_CTL		0x00B8
-#define SF_RXCQ_CTL_1		0x00BC
-#define SF_RXCQ_CTL_2		0x00C0
-#define SF_CQ_CONSIDX		0x00C4
-#define SF_CQ_PRODIDX		0x00C8
-#define SF_CQ_RXQ2		0x00CC
-#define SF_RXDMA_CTL		0x00D0
-#define SF_RXDQ_CTL_1		0x00D4
-#define SF_RXDQ_CTL_2		0x00D8
-#define SF_RXDQ_ADDR_HIADDR	0x00DC
-#define SF_RXDQ_ADDR_Q1		0x00E0
-#define SF_RXDQ_ADDR_Q2		0x00E4
-#define SF_RXDQ_PTR_Q1		0x00E8
-#define SF_RXDQ_PTR_Q2		0x00EC
-#define SF_RXDMA_STS		0x00F0
-#define SF_RXFILT		0x00F4
-#define SF_RX_FRAMETEST_OUT	0x00F8
-
-/* Ethernet control register */
-#define SF_ETHCTL_RX_ENB	0x00000001
-#define SF_ETHCTL_TX_ENB	0x00000002
-#define SF_ETHCTL_RXDMA_ENB	0x00000004
-#define SF_ETHCTL_TXDMA_ENB	0x00000008
-#define SF_ETHCTL_RXGFP_ENB	0x00000010
-#define SF_ETHCTL_TXGFP_ENB	0x00000020
-#define SF_ETHCTL_SOFTINTR	0x00000800
-
-/* Timer control register */
-#define SF_TIMER_IMASK_INTERVAL	0x0000001F
-#define SF_TIMER_IMASK_MODE	0x00000060
-#define SF_TIMER_SMALLFRAME_BYP	0x00000100
-#define SF_TIMER_SMALLRX_FRAME	0x00000600
-#define SF_TIMER_TIMES_TEN	0x00000800
-#define SF_TIMER_RXHIPRIO_BYP	0x00001000
-#define SF_TIMER_TX_DMADONE_DLY	0x00002000
-#define SF_TIMER_TX_QDONE_DLY	0x00004000
-#define SF_TIMER_TX_FRDONE_DLY	0x00008000
-#define SF_TIMER_GENTIMER	0x00FF0000
-#define SF_TIMER_ONESHOT	0x01000000
-#define SF_TIMER_GENTIMER_RES	0x02000000
-#define SF_TIMER_TIMEST_RES	0x04000000
-#define SF_TIMER_RXQ2DONE_DLY	0x10000000
-#define SF_TIMER_EARLYRX2_DLY	0x20000000
-#define SF_TIMER_RXQ1DONE_DLY	0x40000000
-#define SF_TIMER_EARLYRX1_DLY	0x80000000
-
-/* Interrupt status register */
-#define SF_ISR_PCIINT_ASSERTED	0x00000001
-#define SF_ISR_GFP_TX		0x00000002
-#define SF_ISR_GFP_RX		0x00000004
-#define SF_ISR_TX_BADID_HIPRIO	0x00000008
-#define SF_ISR_TX_BADID_LOPRIO	0x00000010
-#define SF_ISR_NO_TX_CSUM	0x00000020
-#define SF_ISR_RXDQ2_NOBUFS	0x00000040
-#define SF_ISR_RXGFP_NORESP	0x00000080
-#define SF_ISR_RXDQ1_DMADONE	0x00000100
-#define SF_ISR_RXDQ2_DMADONE	0x00000200
-#define SF_ISR_RXDQ1_EARLY	0x00000400
-#define SF_ISR_RXDQ2_EARLY	0x00000800
-#define SF_ISR_TX_QUEUEDONE	0x00001000
-#define SF_ISR_TX_DMADONE	0x00002000
-#define SF_ISR_TX_TXDONE	0x00004000
-#define SF_ISR_NORMALINTR	0x00008000
-#define SF_ISR_RXDQ1_NOBUFS	0x00010000
-#define SF_ISR_RXCQ2_NOBUFS	0x00020000
-#define SF_ISR_TX_LOFIFO	0x00040000
-#define SF_ISR_DMAERR		0x00080000
-#define SF_ISR_PCIINT		0x00100000
-#define SF_ISR_TXCQ_NOBUFS	0x00200000
-#define SF_ISR_RXCQ1_NOBUFS	0x00400000
-#define SF_ISR_SOFTINTR		0x00800000
-#define SF_ISR_GENTIMER		0x01000000
-#define SF_ISR_ABNORMALINTR	0x02000000
-#define SF_ISR_RSVD0		0x04000000
-#define SF_ISR_STATSOFLOW	0x08000000
-#define SF_ISR_GPIO		0xF0000000
-
-/*
- * Shadow interrupt status register. Unlike the normal IRQ register,
- * reading bits here does not automatically cause them to reset.
- */
-#define SF_SISR_PCIINT_ASSERTED	0x00000001
-#define SF_SISR_GFP_TX		0x00000002
-#define SF_SISR_GFP_RX		0x00000004
-#define SF_SISR_TX_BADID_HIPRIO	0x00000008
-#define SF_SISR_TX_BADID_LOPRIO	0x00000010
-#define SF_SISR_NO_TX_CSUM	0x00000020
-#define SF_SISR_RXDQ2_NOBUFS	0x00000040
-#define SF_SISR_RXGFP_NORESP	0x00000080
-#define SF_SISR_RXDQ1_DMADONE	0x00000100
-#define SF_SISR_RXDQ2_DMADONE	0x00000200
-#define SF_SISR_RXDQ1_EARLY	0x00000400
-#define SF_SISR_RXDQ2_EARLY	0x00000800
-#define SF_SISR_TX_QUEUEDONE	0x00001000
-#define SF_SISR_TX_DMADONE	0x00002000
-#define SF_SISR_TX_TXDONE	0x00004000
-#define SF_SISR_NORMALINTR	0x00008000
-#define SF_SISR_RXDQ1_NOBUFS	0x00010000
-#define SF_SISR_RXCQ2_NOBUFS	0x00020000
-#define SF_SISR_TX_LOFIFO	0x00040000
-#define SF_SISR_DMAERR		0x00080000
-#define SF_SISR_PCIINT		0x00100000
-#define SF_SISR_TXCQ_NOBUFS	0x00200000
-#define SF_SISR_RXCQ1_NOBUFS	0x00400000
-#define SF_SISR_SOFTINTR	0x00800000
-#define SF_SISR_GENTIMER	0x01000000
-#define SF_SISR_ABNORMALINTR	0x02000000
-#define SF_SISR_RSVD0		0x04000000
-#define SF_SISR_STATSOFLOW	0x08000000
-#define SF_SISR_GPIO		0xF0000000
-
-/* Interrupt mask register */
-#define SF_IMR_PCIINT_ASSERTED	0x00000001
-#define SF_IMR_GFP_TX		0x00000002
-#define SF_IMR_GFP_RX		0x00000004
-#define SF_IMR_TX_BADID_HIPRIO	0x00000008
-#define SF_IMR_TX_BADID_LOPRIO	0x00000010
-#define SF_IMR_NO_TX_CSUM	0x00000020
-#define SF_IMR_RXDQ2_NOBUFS	0x00000040
-#define SF_IMR_RXGFP_NORESP	0x00000080
-#define SF_IMR_RXDQ1_DMADONE	0x00000100
-#define SF_IMR_RXDQ2_DMADONE	0x00000200
-#define SF_IMR_RXDQ1_EARLY	0x00000400
-#define SF_IMR_RXDQ2_EARLY	0x00000800
-#define SF_IMR_TX_QUEUEDONE	0x00001000
-#define SF_IMR_TX_DMADONE	0x00002000
-#define SF_IMR_TX_TXDONE	0x00004000
-#define SF_IMR_NORMALINTR	0x00008000
-#define SF_IMR_RXDQ1_NOBUFS	0x00010000
-#define SF_IMR_RXCQ2_NOBUFS	0x00020000
-#define SF_IMR_TX_LOFIFO	0x00040000
-#define SF_IMR_DMAERR		0x00080000
-#define SF_IMR_PCIINT		0x00100000
-#define SF_IMR_TXCQ_NOBUFS	0x00200000
-#define SF_IMR_RXCQ1_NOBUFS	0x00400000
-#define SF_IMR_SOFTINTR		0x00800000
-#define SF_IMR_GENTIMER		0x01000000
-#define SF_IMR_ABNORMALINTR	0x02000000
-#define SF_IMR_RSVD0		0x04000000
-#define SF_IMR_STATSOFLOW	0x08000000
-#define SF_IMR_GPIO		0xF0000000
-
-#define SF_INTRS	\
-	(SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE|	\
-	 SF_IMR_TX_TXDONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE|	\
-	 SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS|	\
-	 SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW|	\
-	 SF_IMR_TX_LOFIFO)
-
-/* TX descriptor queue control registers */
-#define SF_TXDQCTL_DESCTYPE	0x00000007
-#define SF_TXDQCTL_NODMACMP	0x00000008
-#define SF_TXDQCTL_MINSPACE	0x00000070
-#define SF_TXDQCTL_64BITADDR	0x00000080
-#define SF_TXDQCTL_BURSTLEN	0x00003F00
-#define SF_TXDQCTL_SKIPLEN	0x001F0000
-#define SF_TXDQCTL_HIPRIOTHRESH	0xFF000000
-
-#define SF_TXBUFDESC_TYPE0	0x00000000
-#define SF_TXBUFDESC_TYPE1	0x00000001
-#define SF_TXBUFDESC_TYPE2	0x00000002
-#define SF_TXBUFDESC_TYPE3	0x00000003
-#define SF_TXBUFDESC_TYPE4	0x00000004
-
-#define SF_TXMINSPACE_UNLIMIT	0x00000000
-#define SF_TXMINSPACE_32BYTES	0x00000010
-#define SF_TXMINSPACE_64BYTES	0x00000020
-#define SF_TXMINSPACE_128BYTES	0x00000030
-#define SF_TXMINSPACE_256BYTES	0x00000040
-
-#define SF_TXSKIPLEN_0BYTES	0x00000000
-#define SF_TXSKIPLEN_8BYTES	0x00010000
-#define SF_TXSKIPLEN_16BYTES	0x00020000
-#define SF_TXSKIPLEN_24BYTES	0x00030000
-#define SF_TXSKIPLEN_32BYTES	0x00040000
-
-/* TX frame control register */
-#define SF_TXFRMCTL_TXTHRESH	0x000000FF
-#define SF_TXFRMCTL_CPLAFTERTX	0x00000100
-#define SF_TXFRMCRL_DEBUG	0x0000FE00
-#define SF_TXFRMCTL_STATUS	0x01FF0000
-#define SF_TXFRMCTL_MAC_TXIF	0xFE000000
-
-/* TX completion queue control register */
-#define SF_TXCQ_THRESH		0x0000000F
-#define SF_TXCQ_COMMON		0x00000010
-#define SF_TXCQ_SIZE		0x00000020
-#define SF_TXCQ_WRITEENB	0x00000040
-#define SF_TXCQ_USE_64BIT	0x00000080
-#define SF_TXCQ_ADDR		0xFFFFFF00
-
-/* RX completion queue control register */
-#define SF_RXCQ_THRESH		0x0000000F
-#define SF_RXCQ_TYPE		0x00000030
-#define SF_RXCQ_WRITEENB	0x00000040
-#define SF_RXCQ_USE_64BIT	0x00000080
-#define SF_RXCQ_ADDR		0xFFFFFF00
-
-#define SF_RXCQTYPE_0		0x00000000
-#define SF_RXCQTYPE_1		0x00000010
-#define SF_RXCQTYPE_2		0x00000020
-#define SF_RXCQTYPE_3		0x00000030
-
-/* TX descriptor queue producer index register */
-#define SF_TXDQ_PRODIDX_LOPRIO	0x000007FF
-#define SF_TXDQ_PRODIDX_HIPRIO	0x07FF0000
-
-/* TX descriptor queue consumer index register */
-#define SF_TXDQ_CONSIDX_LOPRIO	0x000007FF
-#define SF_TXDQ_CONSIDX_HIPRIO	0x07FF0000
-
-/* Completion queue consumer index register */
-#define SF_CQ_CONSIDX_RXQ1	0x000003FF
-#define SF_CQ_CONSIDX_RXTHRMODE	0x00008000
-#define SF_CQ_CONSIDX_TXQ	0x03FF0000
-#define SF_CQ_CONSIDX_TXTHRMODE	0x80000000
-
-/* Completion queue producer index register */
-#define SF_CQ_PRODIDX_RXQ1	0x000003FF
-#define SF_CQ_PRODIDX_TXQ	0x03FF0000
-
-/* RX completion queue 2 consumer/producer index register */
-#define SF_CQ_RXQ2_CONSIDX	0x000003FF
-#define SF_CQ_RXQ2_RXTHRMODE	0x00008000
-#define SF_CQ_RXQ2_PRODIDX	0x03FF0000
-
-#define SF_CQ_RXTHRMODE_INT_ON	0x00008000
-#define SF_CQ_RXTHRMODE_INT_OFF	0x00000000
-#define SF_CQ_TXTHRMODE_INT_ON	0x80000000
-#define SF_CQ_TXTHRMODE_INT_OFF	0x00000000
-
-#define SF_IDX_LO(x)		((x) & 0x000007FF)
-#define SF_IDX_HI(x)		(((x) >> 16) & 0x000007FF)
-
-/* RX DMA control register */
-#define SF_RXDMA_BURSTSIZE	0x0000007F
-#define SF_RXDMA_FPTESTMODE	0x00000080
-#define SF_RXDMA_HIPRIOTHRESH	0x00000F00
-#define SF_RXDMA_RXEARLYTHRESH	0x0001F000
-#define SF_RXDMA_DMACRC		0x00040000
-#define SF_RXDMA_USEBKUPQUEUE	0x00080000
-#define SF_RXDMA_QUEUEMODE	0x00700000
-#define SF_RXDMA_RXCQ2_ON	0x00800000
-#define SF_RXDMA_CSUMMODE	0x03000000
-#define SF_RXDMA_DMAPAUSEPKTS	0x04000000
-#define SF_RXDMA_DMACTLPKTS	0x08000000
-#define SF_RXDMA_DMACRXERRPKTS	0x10000000
-#define SF_RXDMA_DMABADPKTS	0x20000000
-#define SF_RXDMA_DMARUNTS	0x40000000
-#define SF_RXDMA_REPORTBADPKTS	0x80000000
-
-#define SF_RXDQMODE_Q1ONLY	0x00100000
-#define SF_RXDQMODE_Q2_ON_FP	0x00200000
-#define SF_RXDQMODE_Q2_ON_SHORT	0x00300000
-#define SF_RXDQMODE_Q2_ON_PRIO	0x00400000
-#define SF_RXDQMODE_SPLITHDR	0x00500000
-
-#define SF_RXCSUMMODE_IGNORE	0x00000000
-#define SF_RXCSUMMODE_REJECT_BAD_TCP	0x01000000
-#define SF_RXCSUMMODE_REJECT_BAD_TCPUDP	0x02000000
-#define SF_RXCSUMMODE_RSVD	0x03000000
-
-/* RX descriptor queue control registers */
-#define SF_RXDQCTL_MINDESCTHR	0x0000007F
-#define SF_RXDQCTL_Q1_WE	0x00000080
-#define SF_RXDQCTL_DESCSPACE	0x00000700
-#define SF_RXDQCTL_64BITDADDR	0x00000800
-#define SF_RXDQCTL_64BITBADDR	0x00001000
-#define SF_RXDQCTL_VARIABLE	0x00002000
-#define SF_RXDQCTL_ENTRIES	0x00004000
-#define SF_RXDQCTL_PREFETCH	0x00008000
-#define SF_RXDQCTL_BUFLEN	0xFFFF0000
-
-#define SF_DESCSPACE_4BYTES	0x00000000
-#define SF_DESCSPACE_8BYTES	0x00000100
-#define SF_DESCSPACE_16BYTES	0x00000200
-#define SF_DESCSPACE_32BYTES	0x00000300
-#define SF_DESCSPACE_64BYTES	0x00000400
-#define SF_DESCSPACE_128_BYTES	0x00000500
-
-/* RX buffer consumer/producer index registers */
-#define SF_RXDQ_PRODIDX		0x000007FF
-#define SF_RXDQ_CONSIDX		0x07FF0000
-
-/* RX filter control register */
-#define SF_RXFILT_PROMISC	0x00000001
-#define SF_RXFILT_ALLMULTI	0x00000002
-#define SF_RXFILT_BROAD		0x00000004
-#define SF_RXFILT_HASHPRIO	0x00000008
-#define SF_RXFILT_HASHMODE	0x00000030
-#define SF_RXFILT_PERFMODE	0x000000C0
-#define SF_RXFILT_VLANMODE	0x00000300
-#define SF_RXFILT_WAKEMODE	0x00000C00
-#define SF_RXFILT_MULTI_NOBROAD	0x00001000
-#define SF_RXFILT_MIN_VLANPRIO	0x0000E000
-#define SF_RXFILT_PEFECTPRIO	0xFFFF0000
-
-/* Hash filtering mode */
-#define SF_HASHMODE_OFF		0x00000000
-#define SF_HASHMODE_WITHVLAN	0x00000010
-#define SF_HASHMODE_ANYVLAN	0x00000020
-#define SF_HASHMODE_ANY		0x00000030
-
-/* Perfect filtering mode */
-#define SF_PERFMODE_OFF		0x00000000
-#define SF_PERFMODE_NORMAL	0x00000040
-#define SF_PERFMODE_INVERSE	0x00000080
-#define SF_PERFMODE_VLAN	0x000000C0
-
-/* VLAN mode */
-#define SF_VLANMODE_OFF		0x00000000
-#define SF_VLANMODE_NOSTRIP	0x00000100
-#define SF_VLANMODE_STRIP	0x00000200
-#define SF_VLANMODE_RSVD	0x00000300
-
-/* Wakeup mode */
-#define SF_WAKEMODE_OFF		0x00000000
-#define SF_WAKEMODE_FILTER	0x00000400
-#define SF_WAKEMODE_FP		0x00000800
-#define SF_WAKEMODE_HIPRIO	0x00000C00
-
-/*
- * Extra PCI registers 0x0100 to 0x0FFF
- */
-#define SF_PCI_TARGSTAT		0x0100
-#define SF_PCI_MASTSTAT1	0x0104
-#define SF_PCI_MASTSTAT2	0x0108
-#define SF_PCI_DMAHOSTADDR_LO	0x010C
-#define SF_BAC_DMADIAG0		0x0110
-#define SF_BAC_DMADIAG1		0x0114
-#define SF_BAC_DMADIAG2		0x0118
-#define SF_BAC_DMADIAG3		0x011C
-#define SF_PAR0			0x0120
-#define SF_PAR1			0x0124
-#define SF_PCICB_FUNCEVENT	0x0130
-#define SF_PCICB_FUNCEVENT_MASK	0x0134
-#define SF_PCICB_FUNCSTATE	0x0138
-#define SF_PCICB_FUNCFORCE	0x013C
-
-/*
- * Serial EEPROM registers 0x1000 to 0x1FFF
- * Presumeably the EEPROM is mapped into this 8K window.
- */
-#define SF_EEADDR_BASE		0x1000
-#define SF_EEADDR_MAX		0x1FFF
-
-#define SF_EE_NODEADDR		14
-
-/*
- * MII registers registers 0x2000 to 0x3FFF
- * There are 32 sets of 32 registers, one set for each possible
- * PHY address. Each 32 bit register is split into a 16-bit data
- * port and a couple of status bits.
- */
-
-#define SF_MIIADDR_BASE		0x2000
-#define SF_MIIADDR_MAX		0x3FFF
-#define SF_MII_BLOCKS		32
-
-#define SF_MII_DATAVALID	0x80000000
-#define SF_MII_BUSY		0x40000000
-#define SF_MII_DATAPORT		0x0000FFFF
-
-#define SF_PHY_REG(phy, reg)						\
-	(SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) +	\
-	(reg * sizeof(u_int32_t)))
-
-/*
- * Ethernet extra registers 0x4000 to 0x4FFF
- */
-#define SF_TESTMODE		0x4000
-#define SF_RX_FRAMEPROC_CTL	0x4004
-#define SF_TX_FRAMEPROC_CTL	0x4008
-
-/*
- * MAC registers 0x5000 to 0x5FFF
- */
-#define SF_MACCFG_1		0x5000
-#define SF_MACCFG_2		0x5004
-#define SF_BKTOBKIPG		0x5008
-#define SF_NONBKTOBKIPG		0x500C
-#define SF_COLRETRY		0x5010
-#define SF_MAXLEN		0x5014
-#define SF_TXNIBBLECNT		0x5018
-#define SF_TXBYTECNT		0x501C
-#define SF_RETXCNT		0x5020
-#define SF_RANDNUM		0x5024
-#define SF_RANDNUM_MASK		0x5028
-#define SF_TOTALTXCNT		0x5034
-#define SF_RXBYTECNT		0x5040
-#define SF_TXPAUSETIMER		0x5060
-#define SF_VLANTYPE		0x5064
-#define SF_MIISTATUS		0x5070
-
-#define SF_MACCFG1_HUGEFRAMES	0x00000001
-#define SF_MACCFG1_FULLDUPLEX	0x00000002
-#define SF_MACCFG1_AUTOPAD	0x00000004
-#define SF_MACCFG1_HDJAM	0x00000008
-#define SF_MACCFG1_DELAYCRC	0x00000010
-#define SF_MACCFG1_NOBACKOFF	0x00000020
-#define SF_MACCFG1_LENGTHCHECK	0x00000040
-#define SF_MACCFG1_PUREPREAMBLE	0x00000080
-#define SF_MACCFG1_PASSALLRX	0x00000100
-#define SF_MACCFG1_PREAM_DETCNT	0x00000200
-#define SF_MACCFG1_RX_FLOWENB	0x00000400
-#define SF_MACCFG1_TX_FLOWENB	0x00000800
-#define SF_MACCFG1_TESTMODE	0x00003000
-#define SF_MACCFG1_MIILOOPBK	0x00004000
-#define SF_MACCFG1_SOFTRESET	0x00008000
-
-/*
- * These are the recommended IPG nibble counter settings
- * specified in the Adaptec manual for full duplex and
- * half duplex operation.
- */
-#define SF_IPGT_FDX		0x15
-#define SF_IPGT_HDX		0x11
-
-/*
- * RX filter registers 0x6000 to 0x6FFF
- */
-#define SF_RXFILT_PERFECT_BASE	0x6000
-#define SF_RXFILT_PERFECT_MAX	0x60FF
-#define SF_RXFILT_PERFECT_SKIP	0x0010
-#define SF_RXFILT_PERFECT_CNT	0x0010
-
-#define SF_RXFILT_HASH_BASE	0x6100
-#define SF_RXFILT_HASH_MAX	0x62FF
-#define SF_RXFILT_HASH_SKIP	0x0010
-#define SF_RXFILT_HASH_CNT	0x001F
-#define SF_RXFILT_HASH_ADDROFF	0x0000
-#define SF_RXFILT_HASH_PRIOOFF	0x0004
-#define SF_RXFILT_HASH_VLANOFF	0x0008
-
-/*
- * Statistics registers 0x7000 to 0x7FFF
- */
-#define SF_STATS_BASE		0x7000
-#define SF_STATS_END		0x7FFF
-
-/*
- * TX frame processor instruction space 0x8000 to 0x9FFF
- */
-
-/*
- * RX frame processor instruction space 0xA000 to 0xBFFF
- */
-
-/*
- * Ethernet FIFO access space 0xC000 to 0xDFFF
- */
-
-/*
- * Reserved 0xE000 to 0xFFFF
- */
-
-/*
- * Descriptor data structures.
- */
-
-
-/* Receive descriptor formats. */
-#define SF_RX_MINSPACING	8
-#define SF_RX_DLIST_CNT		256
-#define SF_RX_CLIST_CNT		1024
-#define SF_RX_HOSTADDR(x)	(((x) >> 2) & 0x3FFFFFFF)
-
-/*
- * RX buffer descriptor type 0, 32-bit addressing. Note that we
- * program the RX buffer queue control register(s) to allow a
- * descriptor spacing of 16 bytes, which leaves room after each
- * descriptor to store a pointer to the mbuf for each buffer.
- */
-struct sf_rx_bufdesc_type0 {
-	u_int32_t		sf_valid:1,
-				sf_end:1,
-				sf_addrlo:30;
-	u_int32_t		sf_pad0;
-#ifdef __i386__
-	u_int32_t		sf_pad1;
-#endif
-	struct mbuf		*sf_mbuf;
-};
-
-/*
- * RX buffer descriptor type 0, 64-bit addressing.
- */
-struct sf_rx_bufdesc_type1 {
-	u_int32_t		sf_valid:1,
-				sf_end:1,
-				sf_addrlo:30;
-	u_int32_t		sf_addrhi;
-#ifdef __i386__
-	u_int32_t		sf_pad;
-#endif
-	struct mbuf		*sf_mbuf;
-};
-
-/*
- * RX completion descriptor, type 0 (short).
- */
-struct sf_rx_cmpdesc_type0 {
-	u_int32_t		sf_len:16,
-				sf_endidx:11,
-				sf_status1:3,
-				sf_id:2;
-};
-
-/*
- * RX completion descriptor, type 1 (basic). Includes vlan ID
- * if this is a vlan-addressed packet, plus extended status.
- */
-struct sf_rx_cmpdesc_type1 {
-	u_int32_t		sf_len:16,
-				sf_endidx:11,
-				sf_status1:3,
-				sf_id:2;
-	u_int16_t		sf_status2;
-	u_int16_t		sf_vlanid;
-};
-
-/*
- * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP
- * checksum instead of vlan tag, plus extended status.
- */
-struct sf_rx_cmpdesc_type2 {
-	u_int32_t		sf_len:16,
-				sf_endidx:11,
-				sf_status1:3,
-				sf_id:2;
-	u_int16_t		sf_status2;
-	u_int16_t		sf_cksum;
-};
-
-/*
- * RX completion descriptor type 3 (full). Includes timestamp, partial
- * TCP/IP checksum, vlan tag plus priority, two extended status fields.
- */
-struct sf_rx_cmpdesc_type3 {
-	u_int32_t		sf_len:16,
-				sf_endidx:11,
-				sf_status1:3,
-				sf_id:2;
-	u_int32_t		sf_startidx:10,
-				sf_status3:6,
-				sf_status2:16;
-	u_int16_t		sf_cksum;
-	u_int16_t		sf_vlanid_prio;
-	u_int32_t		sf_timestamp;
-};
-
-#define SF_RXSTAT1_QUEUE	0x1
-#define SF_RXSTAT1_FIFOFULL	0x2
-#define SF_RXSTAT1_OK		0x4
-
-					/* 0=unknown,5=unsupported */
-#define SF_RXSTAT2_FRAMETYPE	0x0007	/* 1=IPv4,2=IPv2,3=IPX,4=ICMP */
-#define SF_RXSTAT2_UDP		0x0008
-#define SF_RXSTAT2_TCP		0x0010
-#define SF_RXSTAT2_FRAG		0x0020
-#define SF_RXSTAT2_PCSUM_OK	0x0040	/* partial checksum ok */
-#define SF_RXSTAT2_CSUM_BAD	0x0080	/* TCP/IP checksum bad */
-#define SF_RXSTAT2_CSUM_OK	0x0100	/* TCP/IP checksum ok */
-#define SF_RXSTAT2_VLAN		0x0200
-#define SF_RXSTAT2_BADRXCODE	0x0400
-#define SF_RXSTAT2_DRIBBLE	0x0800
-#define SF_RXSTAT2_ISL_CRCERR	0x1000
-#define SF_RXSTAT2_CRCERR	0x2000
-#define SF_RXSTAT2_HASH		0x4000
-#define SF_RXSTAT2_PERFECT	0x8000
-
-#define SF_RXSTAT3_TRAILER	0x01
-#define SF_RXSTAT3_HEADER	0x02
-#define SF_RXSTAT3_CONTROL	0x04
-#define SF_RXSTAT3_PAUSE	0x08
-#define SF_RXSTAT3_ISL		0x10
-
-/*
- * Transmit descriptor formats.
- * Each transmit descriptor type allows for a skip field at the
- * start of each structure. The size of the skip field can vary,
- * however we always set it for 8 bytes, which is enough to hold
- * a pointer (32 bits on x86, 64-bits on alpha) that we can use
- * to hold the address of the head of the mbuf chain for the
- * frame or fragment associated with the descriptor. This saves
- * us from having to create a separate pointer array to hold
- * the mbuf addresses.
- */
-#define SF_TX_BUFDESC_ID		0xB
-#define SF_MAXFRAGS			14
-#define SF_TX_MINSPACING		128
-#define SF_TX_DLIST_CNT			128
-#define SF_TX_DLIST_SIZE		16384
-#define SF_TX_SKIPLEN			1
-#define SF_TX_CLIST_CNT			1024
-
-struct sf_frag {
-	u_int32_t		sf_addr;
-	u_int16_t		sf_fraglen;
-	u_int16_t		sf_pktlen;
-};
-
-struct sf_frag_msdos {
-	u_int16_t		sf_pktlen;
-	u_int16_t		sf_fraglen;
-	u_int32_t		sf_addr;
-};
-
-/*
- * TX frame descriptor type 0, 32-bit addressing. One descriptor can
- * be used to map multiple packet fragments. We use this format since
- * BSD networking fragments packet data across mbuf chains. Note that
- * the number of fragments can be variable depending on how the descriptor
- * spacing is specified in the TX descriptor queue control register.
- * We always use a spacing of 128 bytes, and a skipfield length of 8
- * bytes: this means 16 bytes for the descriptor, including the skipfield,
- * with 121 bytes left for fragment maps. Each fragment requires 8 bytes,
- * which allows for 14 fragments per descriptor. The total size of the
- * transmit buffer queue is limited to 16384 bytes, so with a spacing of
- * 128 bytes per descriptor, we have room for 128 descriptors in the queue.
- */
-struct sf_tx_bufdesc_type0 {
-#ifdef __i386__
-	u_int32_t		sf_pad;
-#endif
-	struct mbuf		*sf_mbuf;
-	u_int32_t		sf_rsvd0:24,
-				sf_crcen:1,
-				sf_caltcp:1,
-				sf_end:1,
-				sf_intr:1,
-				sf_id:4;
-	u_int8_t		sf_fragcnt;
-	u_int8_t		sf_rsvd2;
-	u_int16_t		sf_rsvd1;
-	struct sf_frag		sf_frags[14];
-};
-
-/*
- * TX buffer descriptor type 1, 32-bit addressing. Each descriptor
- * maps a single fragment.
- */
-struct sf_tx_bufdesc_type1 {
-#ifdef __i386__
-	u_int32_t		sf_pad;
-#endif
-	struct mbuf		*sf_mbuf;
-	u_int32_t		sf_fraglen:16,
-				sf_fragcnt:8,
-				sf_crcen:1,
-				sf_caltcp:1,
-				sf_end:1,
-				sf_intr:1,
-				sf_id:4;
-	u_int32_t		sf_addr;
-};
-
-/*
- * TX buffer descriptor type 2, 64-bit addressing. Each descriptor
- * maps a single fragment.
- */
-struct sf_tx_bufdesc_type2 {
-#ifdef __i386__
-	u_int32_t		sf_pad;
-#endif
-	struct mbuf		*sf_mbuf;
-	u_int32_t		sf_fraglen:16,
-				sf_fragcnt:8,
-				sf_crcen:1,
-				sf_caltcp:1,
-				sf_end:1,
-				sf_intr:1,
-				sf_id:4;
-	u_int32_t		sf_addrlo;
-	u_int32_t		sf_addrhi;
-};
-
-/* TX buffer descriptor type 3 is not defined. */
-
-/*
- * TX frame descriptor type 4, 32-bit addressing. This is a special
- * case of the type 0 descriptor, identical except that the fragment
- * address and length fields are ordered differently. This is done
- * to optimize copies in MS-DOS and OS/2 drivers.
- */
-struct sf_tx_bufdesc_type4 {
-#ifdef __i386__
-	u_int32_t		sf_pad;
-#endif
-	struct mbuf		*sf_mbuf;
-	u_int32_t		sf_rsvd0:24,
-				sf_crcen:1,
-				sf_caltcp:1,
-				sf_end:1,
-				sf_intr:1,
-				sf_id:4;
-	u_int8_t		sf_fragcnt;
-	u_int8_t		sf_rsvd2;
-	u_int16_t		sf_rsvd1;
-	struct sf_frag_msdos	sf_frags[14];
-};
-
-/*
- * Transmit completion queue descriptor formats.
- */
-
-/*
- * Transmit DMA completion descriptor, type 0.
- */
-#define SF_TXCMPTYPE_DMA	0x4
-struct sf_tx_cmpdesc_type0 {
-	u_int32_t		sf_index:15,
-				sf_priority:1,
-				sf_timestamp:13,
-				sf_type:3;
-};
-
-/*
- * Transmit completion descriptor, type 1.
- */
-#define SF_TXCMPTYPE_TX		0x5
-struct sf_tx_cmpdesc_type1 {
-	u_int32_t		sf_index:15,
-				sf_priority:1,
-				sf_txstat:13,
-				sf_type:3;
-};
-
-#define SF_TXSTAT_CRCERR	0x0001
-#define SF_TXSTAT_LENCHECKERR	0x0002
-#define SF_TXSTAT_LENRANGEERR	0x0004
-#define SF_TXSTAT_TX_OK		0x0008
-#define SF_TXSTAT_TX_DEFERED	0x0010
-#define SF_TXSTAT_EXCESS_DEFER	0x0020
-#define SF_TXSTAT_EXCESS_COLL	0x0040
-#define SF_TXSTAT_LATE_COLL	0x0080
-#define SF_TXSTAT_TOOBIG	0x0100
-#define SF_TXSTAT_TX_UNDERRUN	0x0200
-#define SF_TXSTAT_CTLFRAME_OK	0x0400
-#define SF_TXSTAT_PAUSEFRAME_OK	0x0800
-#define SF_TXSTAT_PAUSED	0x1000
-
-/* Statistics counters. */
-struct sf_stats {
-	u_int32_t		sf_tx_frames;
-	u_int32_t		sf_tx_single_colls;
-	u_int32_t		sf_tx_multi_colls;
-	u_int32_t		sf_tx_crcerrs;
-	u_int32_t		sf_tx_bytes;
-	u_int32_t		sf_tx_defered;
-	u_int32_t		sf_tx_late_colls;
-	u_int32_t		sf_tx_pause_frames;
-	u_int32_t		sf_tx_control_frames;
-	u_int32_t		sf_tx_excess_colls;
-	u_int32_t		sf_tx_excess_defer;
-	u_int32_t		sf_tx_mcast_frames;
-	u_int32_t		sf_tx_bcast_frames;
-	u_int32_t		sf_tx_frames_lost;
-	u_int32_t		sf_rx_rx_frames;
-	u_int32_t		sf_rx_crcerrs;
-	u_int32_t		sf_rx_alignerrs;
-	u_int32_t		sf_rx_bytes;
-	u_int32_t		sf_rx_control_frames;
-	u_int32_t		sf_rx_unsup_control_frames;
-	u_int32_t		sf_rx_giants;
-	u_int32_t		sf_rx_runts;
-	u_int32_t		sf_rx_jabbererrs;
-	u_int32_t		sf_rx_pkts_64;
-	u_int32_t		sf_rx_pkts_65_127;
-	u_int32_t		sf_rx_pkts_128_255;
-	u_int32_t		sf_rx_pkts_256_511;
-	u_int32_t		sf_rx_pkts_512_1023;
-	u_int32_t		sf_rx_pkts_1024_1518;
-	u_int32_t		sf_rx_frames_lost;
-	u_int16_t		sf_tx_underruns;
-	u_int16_t		sf_pad;
-};
-
-/*
- * register space access macros
- */
-#define CSR_WRITE_4(sc, reg, val)	\
-	bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val)
-
-#define CSR_READ_4(sc, reg)		\
-	bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg)
-
-#define CSR_READ_1(sc, reg)		\
-	bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg)
-
-
-struct sf_type {
-	u_int16_t		sf_vid;
-	u_int16_t		sf_did;
-	char			*sf_name;
-};
-
-#define SF_INC(x, y)	(x) = (x + 1) % y
-
-/*
- * Note: alignment is important here: each list must be aligned to
- * a 256-byte boundary. It turns out that each ring is some multiple
- * of 4K in length, so we can stack them all on top of each other
- * and just worry about aligning the whole mess. There's one transmit
- * buffer ring and two receive buffer rings: one RX ring is for small
- * packets and the other is for large packets. Each buffer ring also
- * has a companion completion queue.
- */
-struct sf_list_data {
-	struct sf_tx_bufdesc_type0	sf_tx_dlist[SF_TX_DLIST_CNT];
-	struct sf_tx_cmpdesc_type1	sf_tx_clist[SF_TX_CLIST_CNT];
-	struct sf_rx_bufdesc_type0	sf_rx_dlist_big[SF_RX_DLIST_CNT];
-#ifdef notdef
-	/*
-	 * Unfortunately, because the Starfire doesn't allow arbitrary
-	 * byte alignment, we have to copy packets in the RX handler in
-	 * order to align the payload correctly. This means that we
-	 * don't gain anything by having separate large and small descriptor
-	 * lists, so for now we don't bother with the small one.
-	 */
-	struct sf_rx_bufdesc_type0	sf_rx_dlist_small[SF_RX_DLIST_CNT];
-#endif
-	struct sf_rx_cmpdesc_type3	sf_rx_clist[SF_RX_CLIST_CNT];
-};
-
-struct sf_softc {
-	struct device		sc_dev;		/* generic device structure */
-	void			*sc_ih;		/* interrupt handler cookie */
-	struct arpcom		arpcom;		/* interface info */
-	struct ifmedia		ifmedia;	/* media info */
-	struct timeout		sc_stats_tmo;
-	mii_data_t		sc_mii;		/* mii bus */
-	bus_space_handle_t	sf_bhandle;	/* bus space handle */
-	bus_space_tag_t		sf_btag;	/* bus space tag */
-	void			*sf_intrhand;	/* interrupt handler cookie */
-	struct sf_type		*sf_info;	/* Starfire adapter info */
-	struct sf_type		*sf_pinfo;
-	u_int8_t		sf_type;
-	u_int8_t		sf_phy_addr;
-	u_int8_t		sf_want_auto;
-	u_int8_t		sf_autoneg;
-	u_int8_t		sf_tx_pend;
-	struct sf_list_data	*sf_ldata;
-	caddr_t			sf_ldata_ptr;
-	int			sf_tx_cnt;
-	u_int8_t		sf_link;
-	int			sf_if_flags;
-};
-
-#define SF_TIMEOUT	1000
-
-#ifdef __alpha__
-#undef vtophys
-#define vtophys(va)		alpha_XXX_dmamap((vaddr_t)va)
-#endif