Add support for the Marvell PHY that's on the Intel GigE cards.

5 files changed, 737 insertions, 3 deletions

diff --git a/sys/dev/mii/eephy.c b/sys/dev/mii/eephy.c
new file mode 100644
index 00000000000..df06ca45b14
--- /dev/null
+++ b/sys/dev/mii/eephy.c
@@ -0,0 +1,435 @@
+/* $OpenBSD: eephy.c,v 1.1 2001/04/13 00:25:02 mjacob Exp $ */
+/*
+ * Principal Author: Parag Patel
+ * Copyright (c) 2001
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Additonal Copyright (c) 2001 by Traakan Software under same licence.
+ * Secondary Author: Matthew Jacob
+ */
+
+/*
+ * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
+
+#include <dev/mii/eephyreg.h>
+
+
+int	eephy_service(struct mii_softc *, struct mii_data *, int);
+void	eephy_status(struct mii_softc *);
+int	eephymatch(struct device *, void *, void *);
+void	eephyattach(struct device *, struct device *, void *);
+
+struct cfattach eephy_ca = {
+	sizeof (struct mii_softc), eephymatch, eephyattach,
+	mii_phy_detach, mii_phy_activate
+};
+
+struct cfdriver eephy_cd = {
+	NULL, "eephy", DV_DULL
+};
+
+int eephy_service(struct mii_softc *, struct mii_data *, int);
+void eephy_status(struct mii_softc *);
+static int	eephy_mii_phy_auto(struct mii_softc *, int);
+extern void	mii_phy_auto_timeout(void *);
+static void eephy_reset(struct mii_softc *);
+
+
+int
+eephymatch(struct device *parent, void *match, void *aux)
+{
+	struct mii_attach_args *ma = aux;
+	u_int32_t id;
+
+	id = ((ma->mii_id1 << 16) | ma->mii_id2) & E1000_ID_MASK;
+	if (id == E1000_ID_88E1000 || id == E1000_ID_88E1000S) {
+		return(10);
+	}
+	return(0);
+}
+
+void
+eephyattach(struct device *parent, struct device *self, void *aux)
+{
+	struct mii_softc *sc = (struct mii_softc *)self;
+	struct mii_attach_args *ma = aux;
+	struct mii_data *mii = ma->mii_data;
+	char *sep;
+
+	sep = "";
+	printf(": %s\n", MII_STR_MARVELL_E1000);
+
+	sc->mii_inst = mii->mii_instance;
+	sc->mii_phy = ma->mii_phyno;
+	sc->mii_service = eephy_service;
+	sc->mii_status = eephy_status;
+	sc->mii_pdata = mii;
+	sc->mii_flags = mii->mii_flags;
+
+	eephy_reset(sc);
+
+	sc->mii_flags |= MIIF_NOISOLATE;
+
+#define	ADD(m, c)	ifmedia_add(&mii->mii_media, (m), (c), NULL)
+#define PRINT(s)	printf("%s%s", sep, s); sep = ", "
+
+	printf("%s: ", sc->mii_dev.dv_xname);
+	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, IFM_FDX, sc->mii_inst),
+			E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX);
+	PRINT("1000baseTX-FDX");
+	/*
+	TODO - apparently 1000BT-simplex not supported?
+	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, 0, sc->mii_inst),
+			E1000_CR_SPEED_1000);
+	PRINT("1000baseTX");
+	*/
+	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
+			E1000_CR_SPEED_100 | E1000_CR_FULL_DUPLEX);
+	PRINT("100baseTX-FDX");
+	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
+			E1000_CR_SPEED_100);
+	PRINT("100baseTX");
+	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
+			E1000_CR_SPEED_10 | E1000_CR_FULL_DUPLEX);
+	PRINT("10baseTX-FDX");
+	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
+			E1000_CR_SPEED_10);
+	PRINT("10baseTX");
+	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
+	PRINT("auto");
+
+	printf("\n");
+#undef ADD
+#undef PRINT
+
+}
+
+static void
+eephy_reset(struct mii_softc *sc)
+{
+	u_int32_t reg;
+	int i;
+
+	/* initialize custom E1000 registers to magic values */
+	reg = PHY_READ(sc, E1000_SCR);
+	reg &= ~E1000_SCR_AUTO_X_MODE;
+	PHY_WRITE(sc, E1000_SCR, reg);
+
+	/* normal PHY reset */
+	/*mii_phy_reset(sc);*/
+	reg = PHY_READ(sc, E1000_CR);
+	reg |= E1000_CR_RESET;
+	PHY_WRITE(sc, E1000_CR, reg);
+
+	for (i = 0; i < 500; i++) {
+		DELAY(1);
+		reg = PHY_READ(sc, E1000_CR);
+		if (!(reg & E1000_CR_RESET))
+			break;
+	}
+
+	/* set more custom E1000 registers to magic values */
+	reg = PHY_READ(sc, E1000_SCR);
+	reg |= E1000_SCR_ASSERT_CRS_ON_TX;
+	PHY_WRITE(sc, E1000_SCR, reg);
+
+	reg = PHY_READ(sc, E1000_ESCR);
+	reg |= E1000_ESCR_TX_CLK_25;
+	PHY_WRITE(sc, E1000_ESCR, reg);
+
+	/* even more magic to reset DSP? */
+	PHY_WRITE(sc, 29, 0x1d);
+	PHY_WRITE(sc, 30, 0xc1);
+	PHY_WRITE(sc, 30, 0x00);
+}
+
+int
+eephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
+{
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+	int reg;
+
+	if ((sc->mii_dev.dv_flags & DVF_ACTIVE) == 0)
+		return (ENXIO);
+
+	switch (cmd) {
+	case MII_POLLSTAT:
+		/*
+		 * If we're not polling our PHY instance, just return.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+			return (0);
+		break;
+
+	case MII_MEDIACHG:
+		/*
+		 * If the media indicates a different PHY instance,
+		 * isolate ourselves.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
+			reg = PHY_READ(sc, E1000_CR);
+			PHY_WRITE(sc, E1000_CR, reg | E1000_CR_ISOLATE);
+			return (0);
+		}
+
+		/*
+		 * If the interface is not up, don't do anything.
+		 */
+		if ((mii->mii_ifp->if_flags & IFF_UP) == 0) {
+			break;
+		}
+
+		switch (IFM_SUBTYPE(ife->ifm_media)) {
+		case IFM_AUTO:
+			/*
+			 * If we're already in auto mode, just return.
+			 */
+			if (sc->mii_flags & MIIF_DOINGAUTO) {
+				return (0);
+			}
+			eephy_reset(sc);
+			(void)eephy_mii_phy_auto(sc, 1);
+			break;
+
+		case IFM_1000_TX:
+			if (sc->mii_flags & MIIF_DOINGAUTO)
+				return (0);
+
+			eephy_reset(sc);
+
+			/* TODO - any other way to force 1000BT? */
+			(void)eephy_mii_phy_auto(sc, 1);
+			break;
+
+		case IFM_100_TX:
+			eephy_reset(sc);
+
+			if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
+				PHY_WRITE(sc, E1000_CR,
+				    E1000_CR_FULL_DUPLEX | E1000_CR_SPEED_100);
+				PHY_WRITE(sc, E1000_AR, E1000_AR_100TX_FD);
+			} else {
+				PHY_WRITE(sc, E1000_CR, E1000_CR_SPEED_100);
+				PHY_WRITE(sc, E1000_AR, E1000_AR_100TX);
+			}
+			break;
+
+		case IFM_10_T:
+			eephy_reset(sc);
+
+			if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
+				PHY_WRITE(sc, E1000_CR,
+				    E1000_CR_FULL_DUPLEX | E1000_CR_SPEED_10);
+				PHY_WRITE(sc, E1000_AR, E1000_AR_10T_FD);
+			} else {
+				PHY_WRITE(sc, E1000_CR, E1000_CR_SPEED_10);
+				PHY_WRITE(sc, E1000_AR, E1000_AR_10T);
+			}
+
+			break;
+
+		default:
+			return (EINVAL);
+		}
+
+		break;
+
+	case MII_TICK:
+		/*
+		 * If we're not currently selected, just return.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
+			return (0);
+		}
+
+		/*
+		 * Only used for autonegotiation.
+		 */
+		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
+			return (0);
+		}
+
+		/*
+		 * Is the interface even up?
+		 */
+		if ((mii->mii_ifp->if_flags & IFF_UP) == 0) {
+			return (0);
+		}
+
+		/*
+		 * Only retry autonegotiation every 5 seconds.
+		 */
+		if (++(sc->mii_ticks) != 5) {
+			return (0);
+		}
+		sc->mii_ticks = 0;
+
+		/*
+		 * Check to see if we have link.  If we do, we don't
+		 * need to restart the autonegotiation process.  Read
+		 * the BMSR twice in case it's latched.
+		 */
+		reg = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
+
+		if (reg & E1000_SR_LINK_STATUS)
+			break;
+
+		eephy_reset(sc);
+
+		if (eephy_mii_phy_auto(sc, 0) == EJUSTRETURN) {
+			return(0);
+		}
+
+		break;
+	}
+
+	/* Update the media status. */
+	eephy_status(sc);
+
+	/* Callback if something changed. */
+	mii_phy_update(sc, cmd);
+
+	return (0);
+}
+
+void
+eephy_status(struct mii_softc *sc)
+{
+	struct mii_data *mii = sc->mii_pdata;
+	int bmsr, bmcr, esr, ssr, isr, ar, lpar;
+
+	if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+		return;
+
+	mii->mii_media_status = IFM_AVALID;
+	mii->mii_media_active = IFM_ETHER;
+
+	bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
+	esr = PHY_READ(sc, E1000_ESR);
+	bmcr = PHY_READ(sc, E1000_CR);
+	ssr = PHY_READ(sc, E1000_SSR);
+	isr = PHY_READ(sc, E1000_ISR);
+	ar = PHY_READ(sc, E1000_AR);
+	lpar = PHY_READ(sc, E1000_LPAR);
+
+	if (bmsr & E1000_SR_LINK_STATUS)
+		mii->mii_media_status |= IFM_ACTIVE;
+
+	if (bmcr & E1000_CR_LOOPBACK)
+		mii->mii_media_active |= IFM_LOOP;
+
+	if ((sc->mii_flags & MIIF_DOINGAUTO) &&
+	    (!(bmsr & E1000_SR_AUTO_NEG_COMPLETE) || !(ssr & E1000_SSR_LINK) ||
+	    !(ssr & E1000_SSR_SPD_DPLX_RESOLVED))) {
+		/* Erg, still trying, I guess... */
+		mii->mii_media_active |= IFM_NONE;
+		return;
+	}
+
+	if (ssr & E1000_SSR_1000MBS)
+		mii->mii_media_active |= IFM_1000_TX;
+	else if (ssr & E1000_SSR_100MBS)
+		mii->mii_media_active |= IFM_100_TX;
+	else
+		mii->mii_media_active |= IFM_10_T;
+
+	if (ssr & E1000_SSR_DUPLEX)
+		mii->mii_media_active |= IFM_FDX;
+	else
+		mii->mii_media_active |= IFM_HDX;
+
+	/* FLAG0==rx-flow-control FLAG1==tx-flow-control */
+	if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) {
+		mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
+	} else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
+	    (lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
+		mii->mii_media_active |= IFM_FLAG1;
+	} else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
+	    !(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
+		mii->mii_media_active |= IFM_FLAG0;
+	}
+}
+
+static int
+eephy_mii_phy_auto(struct mii_softc *sc, int waitfor)
+{
+	int bmsr, i;
+
+	if ((sc->mii_flags & MIIF_DOINGAUTO) == 0) {
+		PHY_WRITE(sc, E1000_AR, E1000_AR_10T | E1000_AR_10T_FD |
+		    E1000_AR_100TX | E1000_AR_100TX_FD | 
+		    E1000_AR_PAUSE | E1000_AR_ASM_DIR);
+		PHY_WRITE(sc, E1000_1GCR, E1000_1GCR_1000T_FD);
+		PHY_WRITE(sc, E1000_CR,
+		    E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
+	}
+
+	if (waitfor) {
+		/* Wait 500ms for it to complete. */
+		for (i = 0; i < 500; i++) {
+			bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
+
+			if (bmsr & E1000_SR_AUTO_NEG_COMPLETE) {
+				return (0);
+			}
+			DELAY(1000);
+		}
+
+		/*
+		 * Don't need to worry about clearing MIIF_DOINGAUTO.
+		 * If that's set, a timeout is pending, and it will
+		 * clear the flag. [do it anyway]
+		 */
+		return (EIO);
+	}
+
+	/*
+	 * Just let it finish asynchronously.  This is for the benefit of
+	 * the tick handler driving autonegotiation.  Don't want 500ms
+	 * delays all the time while the system is running!
+	 */
+	if ((sc->mii_flags & MIIF_DOINGAUTO) == 0) {
+		sc->mii_flags |= MIIF_DOINGAUTO;
+		sc->mii_ticks = 0;
+		timeout_set(&sc->mii_phy_timo, mii_phy_auto_timeout, sc);
+		timeout_add(&sc->mii_phy_timo, hz >> 1);
+	}
+	return (EJUSTRETURN);
+}
diff --git a/sys/dev/mii/eephyreg.h b/sys/dev/mii/eephyreg.h
new file mode 100644
index 00000000000..1684b3317b6
--- /dev/null
+++ b/sys/dev/mii/eephyreg.h
@@ -0,0 +1,286 @@
+/* $OpenBSD: eephyreg.h,v 1.1 2001/04/13 00:25:02 mjacob Exp $ */
+/*
+ * Principal Author: Parag Patel
+ * Copyright (c) 2001
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Additonal Copyright (c) 2001 by Traakan Software under same licence.
+ * Secondary Author: Matthew Jacob
+ */
+
+/*
+ * Derived by information released by Intel under the following license:
+ *
+ * Copyright (c) 1999 - 2001, Intel Corporation 
+ * 
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions are met:
+ * 
+ *  1. Redistributions of source code must retain the above copyright notice, 
+ *     this list of conditions and the following disclaimer.
+ * 
+ *  2. Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ * 
+ *  3. Neither the name of Intel Corporation nor the names of its contributors 
+ *     may be used to endorse or promote products derived from this software 
+ *     without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/*
+ * Marvell E1000 PHY registers
+ */
+
+#define E1000_MAX_REG_ADDRESS		0x1F
+
+#define E1000_CR			0x00	/* control register */
+#define E1000_CR_SPEED_SELECT_MSB	0x0040
+#define E1000_CR_COLL_TEST_ENABLE	0x0080
+#define E1000_CR_FULL_DUPLEX		0x0100
+#define E1000_CR_RESTART_AUTO_NEG	0x0200
+#define E1000_CR_ISOLATE		0x0400
+#define E1000_CR_POWER_DOWN		0x0800
+#define E1000_CR_AUTO_NEG_ENABLE	0x1000
+#define E1000_CR_SPEED_SELECT_LSB	0x2000
+#define E1000_CR_LOOPBACK		0x4000
+#define E1000_CR_RESET			0x8000
+
+#define E1000_CR_SPEED_1000		0x0040
+#define E1000_CR_SPEED_100		0x2000
+#define E1000_CR_SPEED_10		0x0000
+
+#define E1000_SR			0x01	/* status register */
+#define E1000_SR_EXTENDED		0x0001
+#define E1000_SR_JABBER_DETECT		0x0002
+#define E1000_SR_LINK_STATUS		0x0004
+#define E1000_SR_AUTO_NEG		0x0008
+#define E1000_SR_REMOTE_FAULT		0x0010
+#define E1000_SR_AUTO_NEG_COMPLETE	0x0020
+#define E1000_SR_PREAMBLE_SUPPRESS	0x0040
+#define E1000_SR_EXTENDED_STATUS	0x0100
+#define E1000_SR_100T2			0x0200
+#define E1000_SR_100T2_FD		0x0400
+#define E1000_SR_10T			0x0800
+#define E1000_SR_10T_FD			0x1000
+#define E1000_SR_100TX			0x2000
+#define E1000_SR_100TX_FD		0x4000
+#define E1000_SR_100T4			0x8000
+
+#define E1000_ID1			0x02	/* ID register 1 */
+#define E1000_ID2			0x03	/* ID register 2 */
+#define E1000_ID_88E1000		0x01410C50
+#define E1000_ID_88E1000S		0x01410C40
+#define E1000_ID_MASK			0xFFFFFFF0
+
+#define E1000_AR			0x04	/* autonegotiation advertise reg */
+#define E1000_AR_SELECTOR_FIELD		0x0001
+#define E1000_AR_10T			0x0020
+#define E1000_AR_10T_FD			0x0040
+#define E1000_AR_100TX			0x0080
+#define E1000_AR_100TX_FD		0x0100
+#define E1000_AR_100T4			0x0200
+#define E1000_AR_PAUSE			0x0400
+#define E1000_AR_ASM_DIR		0x0800
+#define E1000_AR_REMOTE_FAULT		0x2000
+#define E1000_AR_NEXT_PAGE		0x8000
+#define E1000_AR_SPEED_MASK		0x01E0
+
+#define E1000_LPAR			0x05	/* autoneg link partner abilities reg */
+#define E1000_LPAR_SELECTOR_FIELD	0x0001
+#define E1000_LPAR_10T			0x0020
+#define E1000_LPAR_10T_FD		0x0040
+#define E1000_LPAR_100TX		0x0080
+#define E1000_LPAR_100TX_FD		0x0100
+#define E1000_LPAR_100T4		0x0200
+#define E1000_LPAR_PAUSE		0x0400
+#define E1000_LPAR_ASM_DIR		0x0800
+#define E1000_LPAR_REMOTE_FAULT		0x2000
+#define E1000_LPAR_ACKNOWLEDGE		0x4000
+#define E1000_LPAR_NEXT_PAGE		0x8000
+
+#define E1000_ER			0x06	/* autoneg expansion reg */
+#define E1000_ER_LP_NWAY		0x0001
+#define E1000_ER_PAGE_RXD		0x0002
+#define E1000_ER_NEXT_PAGE		0x0004
+#define E1000_ER_LP_NEXT_PAGE		0x0008
+#define E1000_ER_PAR_DETECT_FAULT	0x0100
+
+#define E1000_NPTX			0x07	/* autoneg next page TX */
+#define E1000_NPTX_MSG_CODE_FIELD	0x0001
+#define E1000_NPTX_TOGGLE		0x0800
+#define E1000_NPTX_ACKNOWLDGE2		0x1000
+#define E1000_NPTX_MSG_PAGE		0x2000
+#define E1000_NPTX_NEXT_PAGE		0x8000
+
+#define E1000_RNPR			0x08	/* autoneg link-partner (?) next page */
+#define E1000_RNPR_MSG_CODE_FIELD	0x0001
+#define E1000_RNPR_TOGGLE		0x0800
+#define E1000_RNPR_ACKNOWLDGE2		0x1000
+#define E1000_RNPR_MSG_PAGE		0x2000
+#define E1000_RNPR_ACKNOWLDGE		0x4000
+#define E1000_RNPR_NEXT_PAGE		0x8000
+
+#define E1000_1GCR			0x09	/* 1000T (1G) control reg */
+#define E1000_1GCR_ASYM_PAUSE		0x0080
+#define E1000_1GCR_1000T		0x0100
+#define E1000_1GCR_1000T_FD		0x0200
+#define E1000_1GCR_REPEATER_DTE		0x0400
+#define E1000_1GCR_MS_VALUE		0x0800
+#define E1000_1GCR_MS_ENABLE		0x1000
+#define E1000_1GCR_TEST_MODE_NORMAL	0x0000
+#define E1000_1GCR_TEST_MODE_1		0x2000
+#define E1000_1GCR_TEST_MODE_2		0x4000
+#define E1000_1GCR_TEST_MODE_3		0x6000
+#define E1000_1GCR_TEST_MODE_4		0x8000
+#define E1000_1GCR_SPEED_MASK		0x0300
+
+#define E1000_1GSR			0x0A	/* 1000T (1G) status reg */
+#define E1000_1GSR_IDLE_ERROR_CNT	0x0000
+#define E1000_1GSR_ASYM_PAUSE_DIR	0x0100
+#define E1000_1GSR_LP			0x0400
+#define E1000_1GSR_LP_FD		0x0800
+#define E1000_1GSR_REMOTE_RX_STATUS	0x1000
+#define E1000_1GSR_LOCAL_RX_STATUS	0x2000
+#define E1000_1GSR_MS_CONFIG_RES	0x4000
+#define E1000_1GSR_MS_CONFIG_FAULT	0x8000
+
+#define E1000_ESR			0x0F	/* IEEE extended status reg */
+#define E1000_ESR_1000T			0x1000
+#define E1000_ESR_1000T_FD		0x2000
+#define E1000_ESR_1000X			0x4000
+#define E1000_ESR_1000X_FD		0x8000
+
+#define E1000_TX_POLARITY_MASK		0x0100
+#define E1000_TX_NORMAL_POLARITY	0
+
+#define E1000_AUTO_POLARITY_DISABLE	0x0010
+
+#define E1000_SCR			0x10	/* special control register */
+#define E1000_SCR_JABBER_DISABLE	0x0001
+#define E1000_SCR_POLARITY_REVERSAL	0x0002
+#define E1000_SCR_SQE_TEST		0x0004
+#define E1000_SCR_INT_FIFO_DISABLE	0x0008
+#define E1000_SCR_CLK125_DISABLE	0x0010
+#define E1000_SCR_MDI_MANUAL_MODE	0x0000
+#define E1000_SCR_MDIX_MANUAL_MODE	0x0020
+#define E1000_SCR_AUTO_X_1000T		0x0040
+#define E1000_SCR_AUTO_X_MODE		0x0060
+#define E1000_SCR_10BT_EXT_ENABLE	0x0080
+#define E1000_SCR_MII_5BIT_ENABLE	0x0100
+#define E1000_SCR_SCRAMBLER_DISABLE	0x0200
+#define E1000_SCR_FORCE_LINK_GOOD	0x0400
+#define E1000_SCR_ASSERT_CRS_ON_TX	0x0800
+#define E1000_SCR_RX_FIFO_DEPTH_6	0x0000
+#define E1000_SCR_RX_FIFO_DEPTH_8	0x1000
+#define E1000_SCR_RX_FIFO_DEPTH_10	0x2000
+#define E1000_SCR_RX_FIFO_DEPTH_12	0x3000
+#define E1000_SCR_TX_FIFO_DEPTH_6	0x0000
+#define E1000_SCR_TX_FIFO_DEPTH_8	0x4000
+#define E1000_SCR_TX_FIFO_DEPTH_10	0x8000
+#define E1000_SCR_TX_FIFO_DEPTH_12	0xC000
+
+#define E1000_SSR			0x11	/* special status register */
+#define E1000_SSR_JABBER		0x0001
+#define E1000_SSR_REV_POLARITY		0x0002
+#define E1000_SSR_MDIX			0x0020
+#define E1000_SSR_LINK			0x0400
+#define E1000_SSR_SPD_DPLX_RESOLVED	0x0800
+#define E1000_SSR_PAGE_RCVD		0x1000
+#define E1000_SSR_DUPLEX		0x2000
+#define E1000_SSR_SPEED			0xC000
+#define E1000_SSR_10MBS			0x0000
+#define E1000_SSR_100MBS		0x4000
+#define E1000_SSR_1000MBS		0x8000
+
+#define E1000_IER			0x12	/* interrupt enable reg */
+#define E1000_IER_JABBER		0x0001
+#define E1000_IER_POLARITY_CHANGE	0x0002
+#define E1000_IER_MDIX_CHANGE		0x0040
+#define E1000_IER_FIFO_OVER_UNDERUN	0x0080
+#define E1000_IER_FALSE_CARRIER		0x0100
+#define E1000_IER_SYMBOL_ERROR		0x0200
+#define E1000_IER_LINK_STAT_CHANGE	0x0400
+#define E1000_IER_AUTO_NEG_COMPLETE	0x0800
+#define E1000_IER_PAGE_RECEIVED		0x1000
+#define E1000_IER_DUPLEX_CHANGED	0x2000
+#define E1000_IER_SPEED_CHANGED		0x4000
+#define E1000_IER_AUTO_NEG_ERR		0x8000
+
+#define E1000_ISR			0x13	/* interrupt status reg */
+#define E1000_ISR_JABBER		0x0001
+#define E1000_ISR_POLARITY_CHANGE	0x0002
+#define E1000_ISR_MDIX_CHANGE		0x0040
+#define E1000_ISR_FIFO_OVER_UNDERUN	0x0080
+#define E1000_ISR_FALSE_CARRIER		0x0100
+#define E1000_ISR_SYMBOL_ERROR		0x0200
+#define E1000_ISR_LINK_STAT_CHANGE	0x0400
+#define E1000_ISR_AUTO_NEG_COMPLETE	0x0800
+#define E1000_ISR_PAGE_RECEIVED		0x1000
+#define E1000_ISR_DUPLEX_CHANGED	0x2000
+#define E1000_ISR_SPEED_CHANGED		0x4000
+#define E1000_ISR_AUTO_NEG_ERR		0x8000
+
+#define E1000_ESCR			0x14	/* extended special control reg */
+#define E1000_ESCR_FIBER_LOOPBACK	0x4000
+#define E1000_ESCR_DOWN_NO_IDLE		0x8000
+#define E1000_ESCR_TX_CLK_2_5		0x0060
+#define E1000_ESCR_TX_CLK_25		0x0070
+#define E1000_ESCR_TX_CLK_0		0x0000
+
+#define E1000_RECR			0x15	/* RX error counter reg */
+
+#define E1000_LCR			0x18	/* LED control reg */
+#define E1000_LCR_LED_TX		0x0001
+#define E1000_LCR_LED_RX		0x0002
+#define E1000_LCR_LED_DUPLEX		0x0004
+#define E1000_LCR_LINK			0x0008
+#define E1000_LCR_BLINK_42MS		0x0000
+#define E1000_LCR_BLINK_84MS		0x0100
+#define E1000_LCR_BLINK_170MS		0x0200
+#define E1000_LCR_BLINK_340MS		0x0300
+#define E1000_LCR_BLINK_670MS		0x0400
+#define E1000_LCR_PULSE_OFF		0x0000
+#define E1000_LCR_PULSE_21_42MS		0x1000
+#define E1000_LCR_PULSE_42_84MS		0x2000
+#define E1000_LCR_PULSE_84_170MS	0x3000
+#define E1000_LCR_PULSE_170_340MS	0x4000
+#define E1000_LCR_PULSE_340_670MS	0x5000
+#define E1000_LCR_PULSE_670_13S		0x6000
+#define E1000_LCR_PULSE_13_26S		0x7000
diff --git a/sys/dev/mii/files.mii b/sys/dev/mii/files.mii
index a343edead21..3db8a4112f6 100644
--- a/sys/dev/mii/files.mii
+++ b/sys/dev/mii/files.mii
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.mii,v 1.15 2001/04/11 06:47:31 deraadt Exp $
+#	$OpenBSD: files.mii,v 1.16 2001/04/13 00:25:02 mjacob Exp $
 #	$NetBSD: files.mii,v 1.13 1998/11/05 00:36:48 thorpej Exp $
 
 file    dev/mii/mii.c				mii
@@ -37,6 +37,10 @@ device iophy: mii_phy
 attach iophy at mii
 file dev/mii/iophy.c				iophy
 
+device eephy: mii_phy, ukphy_subr
+attach eephy at mii
+file dev/mii/eephy.c				eephy
+
 device exphy: mii_phy, ukphy_subr
 attach exphy at mii
 file dev/mii/exphy.c				exphy
diff --git a/sys/dev/mii/miidevs b/sys/dev/mii/miidevs
index 2b5d8d6e786..81b2ef3654b 100644
--- a/sys/dev/mii/miidevs
+++ b/sys/dev/mii/miidevs
@@ -1,4 +1,4 @@
-$OpenBSD: miidevs,v 1.17 2001/04/11 05:45:58 deraadt Exp $
+$OpenBSD: miidevs,v 1.18 2001/04/13 00:25:02 mjacob Exp $
 /* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */
 
 /*-
@@ -47,6 +47,7 @@ oui AMD				0x00001a	Advanced Micro Devices
 oui BROADCOM			0x001018	Broadcom Corporation
 oui ENABLESEMI			0x0010dd	Enable Semiconductor
 oui DAVICOM			0x00606e	Davicom Semiconductor
+oui MARVELL			0x005043	Marvell Semiconductor
 oui ICS				0x00a0be	Integrated Circuit Systems
 oui INTEL			0x00aa00	Intel
 oui LEVEL1			0x00207b	Level 1
@@ -106,6 +107,9 @@ model BROADCOM BCM5411		0x0007 BCM5411 1000baseTX PHY
 /* Davicom Semiconductor PHYs */
 model xxDAVICOM DM9101		0x0000 DM9101 10/100 media interface
 
+/* Marvell Semiconductor PHYs */
+model MARVELL E1000		0x0000 Marvell Semiconductor 88E1000* Gigabit
+
 /* Contrived vendor/model for dcphy */
 model xxDEC xxDC		0x0001 DC
 
diff --git a/sys/dev/mii/miidevs.h b/sys/dev/mii/miidevs.h
index 2e77cff4214..59272dfbebf 100644
--- a/sys/dev/mii/miidevs.h
+++ b/sys/dev/mii/miidevs.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: miidevs.h,v 1.19 2001/04/11 05:46:12 deraadt Exp $	*/
+/*	$OpenBSD: miidevs.h,v 1.20 2001/04/13 00:25:02 mjacob Exp $	*/
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
@@ -54,6 +54,7 @@
 #define	MII_OUI_BROADCOM	0x001018	/* Broadcom Corporation */
 #define	MII_OUI_ENABLESEMI	0x0010dd	/* Enable Semiconductor */
 #define	MII_OUI_DAVICOM	0x00606e	/* Davicom Semiconductor */
+#define	MII_OUI_MARVELL	0x005043	/* Marvell Semiconductor */
 #define	MII_OUI_ICS	0x00a0be	/* Integrated Circuit Systems */
 #define	MII_OUI_INTEL	0x00aa00	/* Intel */
 #define	MII_OUI_LEVEL1	0x00207b	/* Level 1 */
@@ -123,6 +124,10 @@
 #define	MII_MODEL_xxDAVICOM_DM9101	0x0000
 #define	MII_STR_xxDAVICOM_DM9101	"DM9101 10/100 media interface"
 
+/* Marvell Semiconductor PHYs */
+#define	MII_MODEL_MARVELL_E1000	0x0000
+#define	MII_STR_MARVELL_E1000	"Marvell Semiconductor 88E1000* Gigabit"
+
 /* Contrived vendor/model for dcphy */
 #define	MII_MODEL_xxDEC_xxDC	0x0001
 #define	MII_STR_xxDEC_xxDC	"DC"