Import of binutils, gas, ld & gprof from Cygnus 960904 tree

46 files changed, 3309 insertions, 0 deletions

diff --git a/gnu/usr.bin/binutils/binutils/config.h-vms b/gnu/usr.bin/binutils/binutils/config.h-vms
new file mode 100644
index 00000000000..5c42f6b4a40
--- /dev/null
+++ b/gnu/usr.bin/binutils/binutils/config.h-vms
@@ -0,0 +1,46 @@
+/* config.h.  Generated automatically by configure.  */
+/* config.in.  Generated automatically from configure.in by autoheader.  */
+
+/* Is the type time_t defined in <time.h>?  */
+#define HAVE_TIME_T_IN_TIME_H 1
+
+/* Is the type time_t defined in <sys/types.h>?  */
+#define HAVE_TIME_T_IN_TYPES_H 1
+
+/* Does <utime.h> define struct utimbuf?  */
+#define HAVE_GOOD_UTIME_H 1
+
+/* Whether fprintf must be declared even if <stdio.h> is included.  */
+#define NEED_DECLARATION_FPRINTF 1
+
+/* Do we need to use the b modifier when opening binary files?  */
+/* #undef USE_BINARY_FOPEN */
+
+/* Define if you have the sbrk function.  */
+/* #undef HAVE_SBRK */
+
+/* Define if you have the utimes function.  */
+#define HAVE_UTIMES 1
+
+/* Define if you have the <fcntl.h> header file.  */
+#define HAVE_FCNTL_H 1
+
+/* Define if you have the <stdlib.h> header file.  */
+#define HAVE_STDLIB_H 1
+
+/* Define if you have the <string.h> header file.  */
+#define HAVE_STRING_H 1
+
+/* Define if you have the <strings.h> header file.  */
+#define HAVE_STRINGS_H 1
+
+/* Define if you have the <sys/file.h> header file.  */
+#define HAVE_SYS_FILE_H 1
+
+/* Define if you have the <unistd.h> header file.  */
+#define HAVE_UNISTD_H 1
+
+#if __GNUC__
+#define _bfd_generic_get_section_contents_in_window _bfd_generic_get_win_section_cont
+#define _elf_section_from_bfd_section _bfd_elf_sec_from_bfd_sec
+#endif
diff --git a/gnu/usr.bin/binutils/binutils/makefile.vms b/gnu/usr.bin/binutils/binutils/makefile.vms
new file mode 100644
index 00000000000..a3b0d60985e
--- /dev/null
+++ b/gnu/usr.bin/binutils/binutils/makefile.vms
@@ -0,0 +1,67 @@
+#
+# Makefile for binutils under openVMS/AXP
+#
+# For use with gnu-make for vms
+#
+# Created by Klaus Kämpf, kkaempf@progis.de
+#
+#
+
+CC=gcc
+
+ifeq ($(CC),gcc)
+CFLAGS=/include=([],[-.include],[-.bfd])$(DEFS)
+DEFS=/define=("unlink=remove")
+LIBS=,GNU_CC:[000000]LIBGCC2/lib,GNU_CC:[000000]LIBGCCLIB/lib,sys$$library:vaxcrtl.olb/lib,GNU_CC:[000000]crt0.obj
+else
+CFLAGS=/noopt/debug/include=([],[-.include],[-.bfd])$(DEFS)/warnings=disable=(missingreturn,implicitfunc)
+DEFS=/define=("const=","unlink=remove",\
+"_bfd_generic_get_section_contents_in_window"="_bfd_generic_get_win_section_cont",\
+"_bfd_elf_section_from_bfd_section"="_bfd_elf_sec_from_bfd_sec")
+LIBS=,sys$$library:vaxcrtl.olb/lib
+endif
+
+BFDLIB = [-.bfd]libbfd.olb/lib
+BFDLIB_DEP = [-.bfd]libbfd.olb
+LIBIBERTY_DEP = [-.libiberty]libiberty.olb
+LIBIBERTY = [-.libiberty]libiberty.olb/lib
+OPCODES_DEP = [-.opcodes]libopcodes.olb
+OPCODES = [-.opcodes]libopcodes.olb/lib
+
+DEBUG_OBJS = rddbg.obj,debug.obj,stabs.obj,ieee.obj,rdcoff.obj
+
+WRITE_DEBUG_OBJS = $(DEBUG_OBJS),wrstabs.obj
+
+BULIBS = []bucomm.obj,version.obj,filemode.obj
+
+ADDL_DEPS = $(BULIBS),$(BFDLIB_DEP),$(LIBIBERTY_DEP)
+ADDL_LIBS = $(BULIBS),$(BFDLIB),$(LIBIBERTY)
+
+SIZEOBJS = $(ADDL_DEPS),size.obj
+
+STRINGSOBJS = $(ADDL_DEPS),strings.obj
+
+NMOBJS = $(ADDL_DEPS),nm.obj
+
+OBJDUMPOBJS = $(ADDL_DEPS),objdump.obj,prdbg.obj,$(DEBUG_OBJS),$(OPCODES_DEP)
+
+all: config.h size.exe strings.exe objdump.exe nm.exe
+
+size.exe: $(SIZEOBJS)
+	link/exe=$@ size.obj,$(ADDL_LIBS)$(LIBS)
+
+strings.exe: $(STRINGSOBJS)
+	link/exe=$@ strings.obj,$(ADDL_LIBS)$(LIBS)
+
+nm.exe: $(NMOBJS)
+	link/exe=$@ nm.obj,$(ADDL_LIBS)$(LIBS)
+
+objdump.exe: $(OBJDUMPOBJS)
+	link/exe=$@ objdump.obj,prdbg.obj,$(DEBUG_OBJS),$(BFDLIB),$(OPCODES),$(ADDL_LIBS)$(LIBS)
+
+
+version.obj: version.c
+	$(CC) $(CFLAGS)/define=(VERSION="""960723""") $<
+
+config.h: config.h-vms
+	$(CP) $< $@
diff --git a/gnu/usr.bin/binutils/gas/config/te-riscix.h b/gnu/usr.bin/binutils/gas/config/te-riscix.h
new file mode 100644
index 00000000000..7c7253ebcbe
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/config/te-riscix.h
@@ -0,0 +1,6 @@
+#define TE_RISCIX
+
+#define LOCAL_LABELS_DOLLAR 1
+#define LOCAL_LABELS_FB 1
+
+#include "obj-format.h"
diff --git a/gnu/usr.bin/binutils/gas/config/vms-a-conf.h b/gnu/usr.bin/binutils/gas/config/vms-a-conf.h
new file mode 100644
index 00000000000..688fc6890ca
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/config/vms-a-conf.h
@@ -0,0 +1,129 @@
+/* vms-alpha-conf.h.  Generated manually from conf.in,
+   and used by config-gas-alpha.com when constructing config.h.  */
+
+/* Define if using alloca.c.  */
+#ifdef __GNUC__
+#undef C_ALLOCA
+#else
+#define C_ALLOCA
+#endif
+
+/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
+   This function is required for alloca.c support on those systems.  */
+#undef CRAY_STACKSEG_END
+
+/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
+#undef HAVE_ALLOCA_H
+
+/* Define as __inline if that's what the C compiler calls it.  */
+#ifdef __GNUC__
+#undef inline
+#else
+#define inline
+#endif
+
+/* If using the C implementation of alloca, define if you know the
+   direction of stack growth for your system; otherwise it will be
+   automatically deduced at run-time.
+	STACK_DIRECTION > 0 => grows toward higher addresses
+	STACK_DIRECTION < 0 => grows toward lower addresses
+	STACK_DIRECTION = 0 => direction of growth unknown
+ */
+#define STACK_DIRECTION (-1)
+
+/* Should gas use high-level BFD interfaces?  */
+#define BFD_ASSEMBLER
+
+/* Some assert/preprocessor combinations are incapable of handling
+   certain kinds of constructs in the argument of assert.  For example,
+   quoted strings (if requoting isn't done right) or newlines.  */
+#ifdef __GNUC__
+#undef BROKEN_ASSERT
+#else
+#define BROKEN_ASSERT
+#endif
+
+/* If we aren't doing cross-assembling, some operations can be optimized,
+   since byte orders and value sizes don't need to be adjusted.  */
+#undef CROSS_COMPILE
+
+/* Some gas code wants to know these parameters.  */
+#define TARGET_ALIAS	"alpha-vms"
+#define TARGET_CPU	"alpha"
+#define TARGET_CANONICAL	"alpha-dec-vms"
+#define TARGET_OS	"openVMS/Alpha"
+#define TARGET_VENDOR	"dec"
+
+/* Sometimes the system header files don't declare malloc and realloc.  */
+#undef NEED_DECLARATION_MALLOC
+
+/* Sometimes the system header files don't declare free.  */
+#undef NEED_DECLARATION_FREE
+
+/* Sometimes errno.h doesn't declare errno itself.  */
+#undef NEED_DECLARATION_ERRNO
+
+#undef MANY_SEGMENTS
+
+/* Needed only for sparc configuration */
+#undef sparcv9
+
+/* Define if you have the remove function.  */
+#define HAVE_REMOVE
+
+/* Define if you have the unlink function.  */
+#undef HAVE_UNLINK
+
+/* Define if you have the <errno.h> header file.  */
+#define HAVE_ERRNO_H
+
+/* Define if you have the <memory.h> header file.  */
+#undef HAVE_MEMORY_H
+
+/* Define if you have the <stdarg.h> header file.  */
+#define HAVE_STDARG_H
+
+/* Define if you have the <stdlib.h> header file.  */
+#define HAVE_STDLIB_H
+
+/* Define if you have the <string.h> header file.  */
+#define HAVE_STRING_H
+
+/* Define if you have the <strings.h> header file.  */
+#undef HAVE_STRINGS_H
+
+/* Define if you have the <sys/types.h> header file.  */
+#ifdef __GNUC__
+#define HAVE_SYS_TYPES_H
+#else
+#undef HAVE_SYS_TYPES_H
+#endif
+
+/* Define if you have the <unistd.h> header file.  */
+#define HAVE_UNISTD_H	/* config-gas.com will make one if necessary */
+
+/* Define if you have the <varargs.h> header file.  */
+#undef HAVE_VARARGS_H
+
+/* VMS-specific:  we need to set up EXIT_xxx here because the default
+   values in as.h are inappropriate for VMS, but we also want to prevent
+   as.h's inclusion of <stdlib.h> from triggering redefinition warnings.
+   <stdlib.h> guards itself against multiple inclusion, so including it
+   here turns as.h's later #include into a no-op.  (We can't simply use
+   #ifndef HAVE_STDLIB_H here, because the <stdlib.h> in several older
+   gcc-vms distributions neglects to define these two required macros.)  */
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#if __DECC
+#undef EXIT_SUCCESS
+#undef EXIT_FAILURE
+#define EXIT_SUCCESS 1			/* SS$_NORMAL, STS$K_SUCCESS */
+#define EXIT_FAILURE 0x10000002		/* (STS$K_ERROR | STS$M_INHIB_MSG) */
+#endif
+
+#include <unixlib.h>
+#if __DECC
+extern int strcasecmp ();
+extern int strncasecmp ();
+#endif
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/all/cofftag.d b/gnu/usr.bin/binutils/gas/testsuite/gas/all/cofftag.d
new file mode 100644
index 00000000000..59898b621ed
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/all/cofftag.d
@@ -0,0 +1,25 @@
+#objdump: -t
+#name: cofftag
+
+.*:     file format .*
+
+SYMBOL TABLE:
+\[  0\]\(sec -2\)\(fl 0x00\)\(ty   0\)\(scl 103\) \(nx 1\) 0x0+0000 foo.c
+File 
+\[  2\]\(sec  1\)\(fl 0x00\)\(ty   0\)\(scl   6\) \(nx 0\) 0x0+0000 gcc2_compiled.
+\[  3\]\(sec  1\)\(fl 0x00\)\(ty   0\)\(scl   6\) \(nx 0\) 0x0+0000 ___gnu_compiled_c
+\[  4\]\(sec -2\)\(fl 0x00\)\(ty   a\)\(scl  15\) \(nx 1\) 0x0+0000 _token
+AUX lnno 0 size 0x4 tagndx 0 endndx 10
+\[  6\]\(sec -1\)\(fl 0x00\)\(ty   b\)\(scl  16\) \(nx 0\) 0x0+0000 _operator
+\[  7\]\(sec -1\)\(fl 0x00\)\(ty   b\)\(scl  16\) \(nx 0\) 0x0+0001 _flags
+\[  8\]\(sec -1\)\(fl 0x00\)\(ty   0\)\(scl 102\) \(nx 1\) 0x0+0004 .eos
+AUX lnno 0 size 0x4 tagndx 4
+\[ 10\]\(sec  1\)\(fl 0x00\)\(ty   0\)\(scl   3\) \(nx 1\) 0x[0-9a-f]+ .text
+AUX scnlen 0x[0-9a-f]+ nreloc 0 nlnno 0
+\[ 12\]\(sec  2\)\(fl 0x00\)\(ty   0\)\(scl   3\) \(nx 1\) 0x[0-9a-f]+ .data
+AUX scnlen 0x[0-9a-f]+ nreloc 0 nlnno 0
+\[ 14\]\(sec  3\)\(fl 0x00\)\(ty   0\)\(scl   3\) \(nx 1\) 0x[0-9a-f]+ .bss
+AUX scnlen 0x[0-9a-f]+ nreloc 0 nlnno 0
+\[ 16\]\(sec  2\)\(fl 0x00\)\(ty   2\)\(scl   2\) \(nx 0\) 0x0+0000 _token
+\[ 17\]\(sec  2\)\(fl 0x00\)\(ty   a\)\(scl   2\) \(nx 1\) 0x[0-9a-f]+ _what
+AUX lnno 0 size 0x4 tagndx 4
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/all/cofftag.s b/gnu/usr.bin/binutils/gas/testsuite/gas/all/cofftag.s
new file mode 100644
index 00000000000..432aa9a8f9f
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/all/cofftag.s
@@ -0,0 +1,57 @@
+/* This file was compiled from this C source:
+	char token =0;
+	enum token {
+	        operator,
+	        flags
+	};
+	 
+	enum token what= operator;
+ */
+
+	.file	"foo.c"
+gcc2_compiled.:
+___gnu_compiled_c:
+.globl _token
+.data
+_token:
+	.byte 0
+.text
+	.def	_token
+	.scl	15
+	.type	012
+	.size	4
+	.endef
+	.def	_operator
+	.val	0
+	.scl	16
+	.type	013
+	.endef
+	.def	_flags
+	.val	1
+	.scl	16
+	.type	013
+	.endef
+	.def	.eos
+	.val	4
+	.scl	102
+	.tag	_token
+	.size	4
+	.endef
+.globl _what
+.data
+	.align 2
+_what:
+	.long 0
+.text
+	.def	_token
+	.val	_token
+	.scl	2
+	.type	02
+	.endef
+	.def	_what
+	.val	_what
+	.scl	2
+	.tag	_token
+	.size	4
+	.type	012
+	.endef
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/arm/arch4t.s b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/arch4t.s
new file mode 100644
index 00000000000..8d28f7f3ec1
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/arch4t.s
@@ -0,0 +1,21 @@
+.text
+.align 0
+	
+	bx	r0
+	bxeq	r1
+
+foo:	
+	ldrh	r3, foo
+	ldrsh	r4, [r5]
+	ldrsb	r4, [r1, r3]
+	ldrsh	r1, [r4, r4]!
+	ldreqsb	r1, [r5, -r3]
+	ldrneh	r2, [r6], r7
+	ldrccsh r2, [r7], +r8
+	ldrsb	r2, [r3, #255]
+	ldrsh	r1, [r4, #-250]
+	ldrsb	r1, [r5, #+240]
+
+	strh	r2, bar
+	strneh	r3, [r3]
+bar:
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/arm/arm7t.d b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/arm7t.d
new file mode 100644
index 00000000000..92613f9dabf
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/arm7t.d
@@ -0,0 +1,68 @@
+#objdump: -dr
+#name: ARM arm7t
+#as: -marm7t -EL
+
+# Test the halfword and signextend memory transfers:
+
+.*: +file format .*arm.*little
+
+Disassembly of section .text:
+00000000 <[^>]*> e1d100b0	ldrh	r0, \[r1\]
+00000004 <[^>]*> e1f100b0	ldrh	r0, \[r1\]!
+00000008 <[^>]*> e19100b2	ldrh	r0, \[r1, r2\]
+0000000c <[^>]*> e1b100b2	ldrh	r0, \[r1, r2\]!
+00000010 <[^>]*> e1d100bc	ldrh	r0, \[r1, #c\]
+00000014 <[^>]*> e1f100bc	ldrh	r0, \[r1, #c\]!
+00000018 <[^>]*> e15100bc	ldrh	r0, \[r1, -#c\]
+0000001c <[^>]*> e09100b2	ldrh	r0, \[r1\], r2
+00000020 <[^>]*> e3a00cff	mov	r0, #ff00
+00000024 <[^>]*> e1df0bb4	ldrh	r0, 000000e0 <\$\$lit_1>
+00000028 <[^>]*> e1df0abc	ldrh	r0, 000000dc <.L2>
+0000002c <[^>]*> e1c100b0	strh	r0, \[r1\]
+00000030 <[^>]*> e1e100b0	strh	r0, \[r1\]!
+00000034 <[^>]*> e18100b2	strh	r0, \[r1, r2\]
+00000038 <[^>]*> e1a100b2	strh	r0, \[r1, r2\]!
+0000003c <[^>]*> e1c100bc	strh	r0, \[r1, #c\]
+00000040 <[^>]*> e1e100bc	strh	r0, \[r1, #c\]!
+00000044 <[^>]*> e14100bc	strh	r0, \[r1, -#c\]
+00000048 <[^>]*> e08100b2	strh	r0, \[r1\], r2
+0000004c <[^>]*> e1cf08b8	strh	r0, 000000dc <.L2>
+00000050 <[^>]*> e1d100d0	ldrsb	r0, \[r1\]
+00000054 <[^>]*> e1f100d0	ldrsb	r0, \[r1\]!
+00000058 <[^>]*> e19100d2	ldrsb	r0, \[r1, r2\]
+0000005c <[^>]*> e1b100d2	ldrsb	r0, \[r1, r2\]!
+00000060 <[^>]*> e1d100dc	ldrsb	r0, \[r1, #c\]
+00000064 <[^>]*> e1f100dc	ldrsb	r0, \[r1, #c\]!
+00000068 <[^>]*> e15100dc	ldrsb	r0, \[r1, -#c\]
+0000006c <[^>]*> e09100d2	ldrsb	r0, \[r1\], r2
+00000070 <[^>]*> e3a000de	mov	r0, #de
+00000074 <[^>]*> e1df06d0	ldrsb	r0, 000000dc <.L2>
+00000078 <[^>]*> e1d100f0	ldrsh	r0, \[r1\]
+0000007c <[^>]*> e1f100f0	ldrsh	r0, \[r1\]!
+00000080 <[^>]*> e19100f2	ldrsh	r0, \[r1, r2\]
+00000084 <[^>]*> e1b100f2	ldrsh	r0, \[r1, r2\]!
+00000088 <[^>]*> e1d100fc	ldrsh	r0, \[r1, #c\]
+0000008c <[^>]*> e1f100fc	ldrsh	r0, \[r1, #c\]!
+00000090 <[^>]*> e15100fc	ldrsh	r0, \[r1, -#c\]
+00000094 <[^>]*> e09100f2	ldrsh	r0, \[r1\], r2
+00000098 <[^>]*> e3a00cff	mov	r0, #ff00
+0000009c <[^>]*> e1df03fc	ldrsh	r0, 000000e0 <\$\$lit_1>
+000000a0 <[^>]*> e1df03f4	ldrsh	r0, 000000dc <.L2>
+000000a4 <[^>]*> e19100b2	ldrh	r0, \[r1, r2\]
+000000a8 <[^>]*> 119100b2	ldrneh	r0, \[r1, r2\]
+000000ac <[^>]*> 819100b2	ldrhih	r0, \[r1, r2\]
+000000b0 <[^>]*> b19100b2	ldrlth	r0, \[r1, r2\]
+000000b4 <[^>]*> e19100f2	ldrsh	r0, \[r1, r2\]
+000000b8 <[^>]*> 119100f2	ldrnesh	r0, \[r1, r2\]
+000000bc <[^>]*> 819100f2	ldrhish	r0, \[r1, r2\]
+000000c0 <[^>]*> b19100f2	ldrltsh	r0, \[r1, r2\]
+000000c4 <[^>]*> e19100d2	ldrsb	r0, \[r1, r2\]
+000000c8 <[^>]*> 119100d2	ldrnesb	r0, \[r1, r2\]
+000000cc <[^>]*> 819100d2	ldrhisb	r0, \[r1, r2\]
+000000d0 <[^>]*> b19100d2	ldrltsb	r0, \[r1, r2\]
+000000d4 <[^>]*> e1df00f4	ldrsh	r0, 000000e0 <\$\$lit_1>
+000000d8 <[^>]*> e1df00f4	ldrsh	r0, 000000e4 <\$\$lit_1\+4>
+...
+[		]*RELOC: 000000dc 32 .LC0
+000000e0 <[^>]*> 0000c0de	.*
+000000e4 <[^>]*> 0000dead	.*
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/arm/arm7t.s b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/arm7t.s
new file mode 100644
index 00000000000..656e90e0330
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/arm7t.s
@@ -0,0 +1,79 @@
+	.section	.rdata
+	.align	0
+.LC0:
+	.ascii	"some data\000"
+
+	.text
+	.align	0
+
+loadhalfwords:
+	ldrh	r0, [r1]
+	ldrh	r0, [r1]!
+	ldrh	r0, [r1, r2]
+	ldrh	r0, [r1, r2]!
+	ldrh	r0, [r1,#0x0C]
+	ldrh	r0, [r1,#0x0C]!
+	ldrh	r0, [r1,#-0x0C]
+	ldrh	r0, [r1], r2
+	ldrh	r0, =0xFF00
+	ldrh	r0, =0xC0DE
+	ldrh	r0, .L2
+
+storehalfwords:
+	strh	r0, [r1]
+	strh	r0, [r1]!
+	strh	r0, [r1, r2]
+	strh	r0, [r1, r2]!
+	strh	r0, [r1,#0x0C]
+	strh	r0, [r1,#0x0C]!
+	strh	r0, [r1,#-0x0C]
+	strh	r0, [r1], r2
+	strh	r0, .L2
+
+loadsignedbytes:
+	ldrsb	r0, [r1]
+	ldrsb	r0, [r1]!
+	ldrsb	r0, [r1, r2]
+	ldrsb	r0, [r1, r2]!
+	ldrsb	r0, [r1,#0x0C]
+	ldrsb	r0, [r1,#0x0C]!
+	ldrsb	r0, [r1,#-0x0C]
+	ldrsb	r0, [r1], r2
+	ldrsb	r0, =0xDE
+	ldrsb	r0, .L2
+
+loadsignedhalfwords:
+	ldrsh	r0, [r1]
+	ldrsh	r0, [r1]!
+	ldrsh	r0, [r1, r2]
+	ldrsh	r0, [r1, r2]!
+	ldrsh	r0, [r1, #0x0C]
+	ldrsh	r0, [r1, #0x0C]!
+	ldrsh	r0, [r1, #-0x0C]
+	ldrsh	r0, [r1], r2
+	ldrsh	r0, =0xFF00
+	ldrsh	r0, =0xC0DE
+	ldrsh	r0, .L2
+	
+misc:
+	ldralh	r0, [r1, r2]
+	ldrneh	r0, [r1, r2]
+	ldrhih	r0, [r1, r2]
+	ldrlth	r0, [r1, r2]
+
+	ldralsh	r0, [r1, r2]
+	ldrnesh	r0, [r1, r2]
+	ldrhish	r0, [r1, r2]
+	ldrltsh	r0, [r1, r2]
+
+	ldralsb	r0, [r1, r2]
+	ldrnesb	r0, [r1, r2]
+	ldrhisb	r0, [r1, r2]
+	ldrltsb	r0, [r1, r2]
+
+	ldrsh	r0, =0xC0DE
+	ldrsh	r0, =0xDEAD
+
+	.align
+.L2:
+	.word	.LC0
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/arm/immed.s b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/immed.s
new file mode 100644
index 00000000000..5d2092be18b
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/immed.s
@@ -0,0 +1,11 @@
+@	Tests for complex immediate expressions - none of these need 
+@	relocations
+	.text
+bar:
+	mov	r0, #0
+	mov	r0, #(. - bar - 8)
+	ldr	r0, bar
+	ldr	r0, [pc, # (bar - . -8)]
+	.space 4096
+	mov	r0, #(. - bar - 8) & 0xff
+	ldr	r0, [pc, # (bar - . -8) & 0xff]
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/arm/inst.d b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/inst.d
new file mode 100644
index 00000000000..23c7f21f382
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/inst.d
@@ -0,0 +1,168 @@
+#objdump: -dr
+#name: ARM basic instructions
+#as: -marm2 -EL
+
+# Test the standard ARM instructions:
+
+.*: +file format .*arm.*little
+
+Disassembly of section .text:
+00000000 <[^>]*> e3a00000	mov	r0, #0
+00000004 <[^>]*> e1a01002	mov	r1, r2
+00000008 <[^>]*> e1a03184	mov	r3, r4, lsl #3
+0000000c <[^>]*> e1a05736	mov	r5, r6, lsr r7
+00000010 <[^>]*> e1a08a59	mov	r8, r9, asr sl
+00000014 <[^>]*> e1a0bd1c	mov	fp, ip, lsl sp
+00000018 <[^>]*> e1a0e06f	mov	lr, pc, rrx
+0000001c <[^>]*> e1a01002	mov	r1, r2
+00000020 <[^>]*> 01a02003	moveq	r2, r3
+00000024 <[^>]*> 11a04005	movne	r4, r5
+00000028 <[^>]*> b1a06007	movlt	r6, r7
+0000002c <[^>]*> a1a08009	movge	r8, r9
+00000030 <[^>]*> d1a0a00b	movle	sl, fp
+00000034 <[^>]*> c1a0c00d	movgt	ip, sp
+00000038 <[^>]*> 31a01002	movcc	r1, r2
+0000003c <[^>]*> 21a01003	movcs	r1, r3
+00000040 <[^>]*> 41a03006	movmi	r3, r6
+00000044 <[^>]*> 51a07009	movpl	r7, r9
+00000048 <[^>]*> 61a01008	movvs	r1, r8
+0000004c <[^>]*> 71a09fa1	movvc	r9, r1, lsr #1f
+00000050 <[^>]*> 81a0800f	movhi	r8, pc
+00000054 <[^>]*> 91a0f00e	movls	pc, lr
+00000058 <[^>]*> 21a09008	movcs	r9, r8
+0000005c <[^>]*> 31a01003	movcc	r1, r3
+00000060 <[^>]*> e1b00008	movs	r0, r8
+00000064 <[^>]*> 31b00007	movccs	r0, r7
+00000068 <[^>]*> e281000a	add	r0, r1, #a
+0000006c <[^>]*> e0832004	add	r2, r3, r4
+00000070 <[^>]*> e0865287	add	r5, r6, r7, lsl #5
+00000074 <[^>]*> e0821113	add	r1, r2, r3, lsl r1
+00000078 <[^>]*> e201000a	and	r0, r1, #a
+0000007c <[^>]*> e0032004	and	r2, r3, r4
+00000080 <[^>]*> e0065287	and	r5, r6, r7, lsl #5
+00000084 <[^>]*> e0021113	and	r1, r2, r3, lsl r1
+00000088 <[^>]*> e221000a	eor	r0, r1, #a
+0000008c <[^>]*> e0232004	eor	r2, r3, r4
+00000090 <[^>]*> e0265287	eor	r5, r6, r7, lsl #5
+00000094 <[^>]*> e0221113	eor	r1, r2, r3, lsl r1
+00000098 <[^>]*> e241000a	sub	r0, r1, #a
+0000009c <[^>]*> e0432004	sub	r2, r3, r4
+000000a0 <[^>]*> e0465287	sub	r5, r6, r7, lsl #5
+000000a4 <[^>]*> e0421113	sub	r1, r2, r3, lsl r1
+000000a8 <[^>]*> e2a1000a	adc	r0, r1, #a
+000000ac <[^>]*> e0a32004	adc	r2, r3, r4
+000000b0 <[^>]*> e0a65287	adc	r5, r6, r7, lsl #5
+000000b4 <[^>]*> e0a21113	adc	r1, r2, r3, lsl r1
+000000b8 <[^>]*> e2c1000a	sbc	r0, r1, #a
+000000bc <[^>]*> e0c32004	sbc	r2, r3, r4
+000000c0 <[^>]*> e0c65287	sbc	r5, r6, r7, lsl #5
+000000c4 <[^>]*> e0c21113	sbc	r1, r2, r3, lsl r1
+000000c8 <[^>]*> e261000a	rsb	r0, r1, #a
+000000cc <[^>]*> e0632004	rsb	r2, r3, r4
+000000d0 <[^>]*> e0665287	rsb	r5, r6, r7, lsl #5
+000000d4 <[^>]*> e0621113	rsb	r1, r2, r3, lsl r1
+000000d8 <[^>]*> e2e1000a	rsc	r0, r1, #a
+000000dc <[^>]*> e0e32004	rsc	r2, r3, r4
+000000e0 <[^>]*> e0e65287	rsc	r5, r6, r7, lsl #5
+000000e4 <[^>]*> e0e21113	rsc	r1, r2, r3, lsl r1
+000000e8 <[^>]*> e381000a	orr	r0, r1, #a
+000000ec <[^>]*> e1832004	orr	r2, r3, r4
+000000f0 <[^>]*> e1865287	orr	r5, r6, r7, lsl #5
+000000f4 <[^>]*> e1821113	orr	r1, r2, r3, lsl r1
+000000f8 <[^>]*> e3c1000a	bic	r0, r1, #a
+000000fc <[^>]*> e1c32004	bic	r2, r3, r4
+00000100 <[^>]*> e1c65287	bic	r5, r6, r7, lsl #5
+00000104 <[^>]*> e1c21113	bic	r1, r2, r3, lsl r1
+00000108 <[^>]*> e3e0000a	mvn	r0, #a
+0000010c <[^>]*> e1e02004	mvn	r2, r4
+00000110 <[^>]*> e1e05287	mvn	r5, r7, lsl #5
+00000114 <[^>]*> e1e01113	mvn	r1, r3, lsl r1
+00000118 <[^>]*> e310000a	tst	r0, #a
+0000011c <[^>]*> e1120004	tst	r2, r4
+00000120 <[^>]*> e1150287	tst	r5, r7, lsl #5
+00000124 <[^>]*> e1110113	tst	r1, r3, lsl r1
+00000128 <[^>]*> e330000a	teq	r0, #a
+0000012c <[^>]*> e1320004	teq	r2, r4
+00000130 <[^>]*> e1350287	teq	r5, r7, lsl #5
+00000134 <[^>]*> e1310113	teq	r1, r3, lsl r1
+00000138 <[^>]*> e350000a	cmp	r0, #a
+0000013c <[^>]*> e1520004	cmp	r2, r4
+00000140 <[^>]*> e1550287	cmp	r5, r7, lsl #5
+00000144 <[^>]*> e1510113	cmp	r1, r3, lsl r1
+00000148 <[^>]*> e370000a	cmn	r0, #a
+0000014c <[^>]*> e1720004	cmn	r2, r4
+00000150 <[^>]*> e1750287	cmn	r5, r7, lsl #5
+00000154 <[^>]*> e1710113	cmn	r1, r3, lsl r1
+00000158 <[^>]*> e330f00a	teqp	r0, #a
+0000015c <[^>]*> e132f004	teqp	r2, r4
+00000160 <[^>]*> e135f287	teqp	r5, r7, lsl #5
+00000164 <[^>]*> e131f113	teqp	r1, r3, lsl r1
+00000168 <[^>]*> e370f00a	cmnp	r0, #a
+0000016c <[^>]*> e172f004	cmnp	r2, r4
+00000170 <[^>]*> e175f287	cmnp	r5, r7, lsl #5
+00000174 <[^>]*> e171f113	cmnp	r1, r3, lsl r1
+00000178 <[^>]*> e350f00a	cmpp	r0, #a
+0000017c <[^>]*> e152f004	cmpp	r2, r4
+00000180 <[^>]*> e155f287	cmpp	r5, r7, lsl #5
+00000184 <[^>]*> e151f113	cmpp	r1, r3, lsl r1
+00000188 <[^>]*> e310f00a	tstp	r0, #a
+0000018c <[^>]*> e112f004	tstp	r2, r4
+00000190 <[^>]*> e115f287	tstp	r5, r7, lsl #5
+00000194 <[^>]*> e111f113	tstp	r1, r3, lsl r1
+00000198 <[^>]*> e0000291	mul	r0, r1, r2
+0000019c <[^>]*> e0110392	muls	r1, r2, r3
+000001a0 <[^>]*> 10000091	mulne	r0, r1, r0
+000001a4 <[^>]*> 90190798	mullss	r9, r8, r7
+000001a8 <[^>]*> e021ba99	mla	r1, r9, sl, fp
+000001ac <[^>]*> e033c994	mlas	r3, r4, r9, ip
+000001b0 <[^>]*> b029d798	mlalt	r9, r8, r7, sp
+000001b4 <[^>]*> a034e391	mlages	r4, r1, r3, lr
+000001b8 <[^>]*> e5910000	ldr	r0, \[r1\]
+000001bc <[^>]*> e7911002	ldr	r1, \[r1, r2\]
+000001c0 <[^>]*> e7b32004	ldr	r2, \[r3, r4\]!
+000001c4 <[^>]*> e5922020	ldr	r2, \[r2, #20\]
+000001c8 <[^>]*> e7932424	ldr	r2, \[r3, r4, lsr #8\]
+000001cc <[^>]*> 07b54484	ldreq	r4, \[r5, r4, lsl #9\]!
+000001d0 <[^>]*> 14954006	ldrne	r4, \[r5\], #6
+000001d4 <[^>]*> e6b21003	ldrt	r1, \[r2\], r3
+000001d8 <[^>]*> e6942425	ldr	r2, \[r4\], r5, lsr #8
+000001dc <[^>]*> e51f0008	ldr	r0, 000001dc <[^>]*>
+000001e0 <[^>]*> e5d43000	ldrb	r3, \[r4\]
+000001e4 <[^>]*> 14f85000	ldrnebt	r5, \[r8\]
+000001e8 <[^>]*> e5810000	str	r0, \[r1\]
+000001ec <[^>]*> e7811002	str	r1, \[r1, r2\]
+000001f0 <[^>]*> e7a33004	str	r3, \[r3, r4\]!
+000001f4 <[^>]*> e5822020	str	r2, \[r2, #20\]
+000001f8 <[^>]*> e7832424	str	r2, \[r3, r4, lsr #8\]
+000001fc <[^>]*> 07a54484	streq	r4, \[r5, r4, lsl #9\]!
+00000200 <[^>]*> 14854006	strne	r4, \[r5\], #6
+00000204 <[^>]*> e6821003	str	r1, \[r2\], r3
+00000208 <[^>]*> e6a42425	strt	r2, \[r4\], r5, lsr #8
+0000020c <[^>]*> e50f1004	str	r1, 00000210 <[^>]*>
+00000210 <[^>]*> e5c71000	strb	r1, \[r7\]
+00000214 <[^>]*> e4e02000	strbt	r2, \[r0\]
+00000218 <[^>]*> e8900002	ldmia	r0, {r1}
+0000021c <[^>]*> 09920038	ldmeqib	r2, {r3, r4, r5}
+00000220 <[^>]*> e853ffff	ldmda	r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^
+00000224 <[^>]*> e93b05ff	ldmdb	fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl}
+00000228 <[^>]*> e99100f7	ldmib	r1, {r0, r1, r2, r4, r5, r6, r7}
+0000022c <[^>]*> e89201f8	ldmia	r2, {r3, r4, r5, r6, r7, r8}
+00000230 <[^>]*> e9130003	ldmdb	r3, {r0, r1}
+00000234 <[^>]*> e8740300	ldmda	r4!, {r8, r9}\^
+00000238 <[^>]*> e8800002	stmia	r0, {r1}
+0000023c <[^>]*> 09820038	stmeqib	r2, {r3, r4, r5}
+00000240 <[^>]*> e843ffff	stmda	r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^
+00000244 <[^>]*> e92a05ff	stmdb	sl!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl}
+00000248 <[^>]*> e8010007	stmda	r1, {r0, r1, r2}
+0000024c <[^>]*> e9020018	stmdb	r2, {r3, r4}
+00000250 <[^>]*> e8830003	stmia	r3, {r0, r1}
+00000254 <[^>]*> e9e40300	stmib	r4!, {r8, r9}\^
+00000258 <[^>]*> ef123456	swi	0x00123456
+0000025c <[^>]*> 2f000033	swics	0x00000033
+00000260 <[^>]*> ebfffffe	bl	00000260 <[^>]*>
+[		]*RELOC: 00000260 ARM26 _wombat
+00000264 <[^>]*> 5bffffe9	blpl	00000210 <bar>
+00000268 <[^>]*> eafffffe	b	00000268 <[^>]*>
+[		]*RELOC: 00000268 ARM26 _wibble
+0000026c <[^>]*> dafffffe	ble	0000026c <[^>]*>
+[		]*RELOC: 0000026c ARM26 testerfunc
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/arm/thumb.s b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/thumb.s
new file mode 100644
index 00000000000..095befbcde8
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/arm/thumb.s
@@ -0,0 +1,185 @@
+	.text
+	.code 16
+foo:	
+	lsl	r2, r1, #3
+	lsr	r3, r4, #31
+wibble/data:	
+	asr	r7, r0, #5
+
+	lsl	r1, r2, #0
+	lsr	r3, r4, #0
+	asr	r4, r5, #0
+
+	lsr	r6, r7, #32
+	asr	r0, r1, #32
+
+	add	r1, r2, r3
+	add	r2, r4, #2
+	sub	r3, r5, r7
+	sub	r2, r4, #7
+
+	mov	r4, #255
+	cmp	r3, #250
+	add	r6, #123
+	sub	r5, #128
+
+	and	r3, r5
+	eor	r4, r6
+	lsl	r1, r0
+	lsr	r2, r3
+	asr	r4, r6
+	adc	r5, r7
+	sbc	r0, r4
+	ror	r1, r4
+	tst	r2, r5
+	neg	r1, r1
+	cmp	r2, r3
+	cmn	r1, r4
+	orr	r0, r3
+	mul	r4, r5
+	bic	r5, r7
+	mvn	r5, r5
+
+	add	r1, r13
+	add	r12, r2
+	add	r9, r9
+	cmp	r1, r14
+	cmp	r8, r0
+	cmp	r12, r14
+	mov	r0, r9
+	mov	r9, r4
+	mov	r8, r8
+	bx	r7
+	bx	r8
+	.align 0
+	bx	pc
+
+	ldr	r3, [pc, #128]
+	ldr	r4, bar
+
+	str	r0, [r1, r2]
+	strb	r1, [r2, r4]
+	ldr	r5, [r6, r7]
+	ldrb	r2, [r4, r5]
+	
+	.align 0
+bar:	
+	strh	r1, [r2, r3]
+	ldrh	r3, [r4, r0]
+	ldsb	r1, [r6, r7]
+	ldsh	r2, [r0, r5]
+
+	str	r3, [r3, #124]
+	ldr	r1, [r4, #124]
+	ldr	r5, [r5]
+	strb	r1, [r5, #31]
+	strb	r1, [r4, #5]
+	strb	r2, [r6]
+
+	strh	r4, [r5, #62]
+	ldrh	r5, [r0, #4]
+	ldrh	r3, [r2]
+
+	str	r3, [r13, #1020]
+	ldr	r1, [r13, #44]
+	ldr	r2, [r13]
+
+	add	r7, r15, #1020
+	add	r4, r13, #512
+
+	add	r13, #268
+	add	r13, #-104
+	sub	r13, #268
+	sub	r13, #-108
+
+	push	{r0, r1, r2, r4}
+	push	{r0, r3-r7, lr}
+	pop	{r3, r4, r7}
+	pop	{r0-r7, r15}
+
+	stmia	r3!, {r0, r1, r4-r7}
+	ldmia	r0!, {r1-r7}
+
+	beq	bar
+	bne	bar
+	bcs	bar
+	bcc	bar
+	bmi	bar
+	bpl	bar
+	bvs	bar
+	bvc	bar
+	bhi	bar
+	bls	bar
+	bge	bar
+	bgt	bar
+	blt	bar
+	bgt	bar
+	ble	bar
+	bhi	bar
+	blo	bar
+	bul	bar
+
+close:
+	lsl	r4, r5, #near - close
+near:
+	add	r2, r3, #near - close
+
+	add	sp, sp, #127 << 2
+	sub	sp, sp, #127 << 2
+	add	r0, sp, #255 << 2
+	add	r0, pc, #255 << 2
+
+	add	sp, sp, #bar - foo
+	sub	sp, sp, #bar - foo
+	add	r0, sp, #bar - foo
+	add	r0, pc, #bar - foo
+
+	add	r1, #bar - foo
+	mov	r6, #bar - foo
+	cmp	r7, #bar - foo
+
+	nop
+	nop
+
+	.arm
+localbar:
+	b	localbar
+	b	wombat
+	bl	localbar
+	bl	wombat
+
+	bx	r0
+	swi	0x123456
+
+	.thumb
+
+	adr	r0, forwardonly
+
+	b	foo
+	b	wombat
+	bl	foo
+	bl	wombat
+
+	bx	r0
+
+	swi	0xff
+	.align	0
+forwardonly:
+	beq	wombat
+	bne	wombat
+	bcs	wombat
+	bcc	wombat
+	bmi	wombat
+	bpl	wombat
+	bvs	wombat
+	bvc	wombat
+	bhi	wombat
+	bls	wombat
+	bge	wombat
+	bgt	wombat
+	blt	wombat
+	bgt	wombat
+	ble	wombat
+	bhi	wombat
+	blo	wombat
+	bul	wombat
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/addsubs.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/addsubs.s
new file mode 100644
index 00000000000..b0b3699e458
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/addsubs.s
@@ -0,0 +1,25 @@
+	.h8300s
+	.text
+h8300s_add_sub:
+	add.b #16,r1l
+	add.b r1h,r1l
+	add.w #32,r1
+	add.w r1,r2
+	add.l #64,er1
+	add.l er1,er2
+	adds #1,er4
+	adds #2,er5
+	adds #4,er6
+	addx r0l,r1l
+	addx #16,r2h
+	sub.b r0l,r1l
+	sub.w #16,r1
+	sub.w r0,r1
+	sub.l #64,er1
+	sub.l er1,er2
+	subs #1,er4
+	subs #2,er5
+	subs #4,er6
+	subx r0l,r1l
+	subx #16,r2h
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops1s.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops1s.s
new file mode 100644
index 00000000000..c6599d41a9a
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops1s.s
@@ -0,0 +1,29 @@
+	.h8300s
+	.text
+h8300s_bit_ops_1:
+	band #0,r0l
+	band #0,@er0
+	band #0,@64:8
+	band #0,@128:16
+	band #0,@65536:32
+	bclr #0,r0l
+	bclr #0,@er0
+	bclr #0,@64:8
+	bclr #0,@128:16
+	bclr #0,@65536:32
+	bclr r1l,r0l
+	bclr r1l,@er0
+	bclr r1l,@64:8
+	bclr r1l,@128:16
+	bclr r1l,@65536:32
+	biand #0,r0l
+	biand #0,@er0
+	biand #0,@64:8
+	biand #0,@128:16
+	biand #0,@65536:32
+	bild #0,r0l
+	bild #0,@er0
+	bild #0,@64:8
+	bild #0,@128:16
+	bild #0,@65536:32
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops2s.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops2s.s
new file mode 100644
index 00000000000..94705201f0d
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops2s.s
@@ -0,0 +1,23 @@
+	.h8300s
+	.text
+h8300s_bit_ops_2:
+	bior #0,r0l
+	bior #0,@er0
+	bior #0,@64:8
+	bior #0,@128:16
+	bior #0,@65536:32
+	bist #0,r0l
+	bist #0,@er0
+	bist #0,@64:8
+	bist #0,@128:16
+	bist #0,@65536:32
+	bixor #0,r0l
+	bixor #0,@er0
+	bixor #0,@64:8
+	bixor #0,@128:16
+	bixor #0,@65536:32
+	bld #0,r0l
+	bld #0,@er0
+	bld #0,@64:8
+	bld #0,@128:16
+	bld #0,@65536:32
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops3s.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops3s.s
new file mode 100644
index 00000000000..7c64e06d783
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops3s.s
@@ -0,0 +1,24 @@
+	.h8300s
+	.text
+h8300s_bit_ops_3:
+	bnot #0,r0l
+	bnot #0,@er0
+	bnot #0,@64:8
+	bnot #0,@128:16
+	bnot #0,@65536:32
+	bnot r1l,r0l
+	bnot r1l,@er0
+	bnot r1l,@64:8
+	bnot r1l,@128:16
+	bnot r1l,@65536:32
+	bset #0,r0l
+	bset #0,@er0
+	bset #0,@64:8
+	bset #0,@128:16
+	bset #0,@65536:32
+	bset r1l,r0l
+	bset r1l,@er0
+	bset r1l,@64:8
+	bset r1l,@128:16
+	bset r1l,@65536:32
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops4s.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops4s.s
new file mode 100644
index 00000000000..e8f47b6dc21
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/bitops4s.s
@@ -0,0 +1,29 @@
+	.h8300s
+	.text
+h8300s_bit_ops_4:
+	bor #0,r0l
+	bor #0,@er0
+	bor #0,@64:8
+	bor #0,@128:16
+	bor #0,@65536:32
+	bst #0,r0l
+	bst #0,@er0
+	bst #0,@64:8
+	bst #0,@128:16
+	bst #0,@65536:32
+	btst #0,r0l
+	btst #0,@er0
+	btst #0,@64:8
+	btst #0,@128:16
+	btst #0,@65536:32
+	btst r1l,r0l
+	btst r1l,@er0
+	btst r1l,@64:8
+	btst r1l,@128:16
+	btst r1l,@65536:32
+	bxor #0,r0l
+	bxor #0,@er0
+	bxor #0,@64:8
+	bxor #0,@128:16
+	bxor #0,@65536:32
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/branch.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/branch.s
new file mode 100644
index 00000000000..25806153c42
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/branch.s
@@ -0,0 +1,10 @@
+	.text
+h8300_branches:
+	bsr h8300_branches
+	jmp h8300_branches
+	jmp @r0
+	jmp @@16:8
+	jsr h8300_branches
+	jsr @r0
+	jsr @@16:8
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/branchh.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/branchh.s
new file mode 100644
index 00000000000..7cbc62f3e2b
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/branchh.s
@@ -0,0 +1,12 @@
+	.h8300h
+	.text
+h8300h_branches:
+	bsr h8300h_branches:8
+	bsr h8300h_branches:16
+	jmp h8300h_branches
+	jmp @er0
+	jmp @@16:8
+	jsr h8300h_branches
+	jsr @er0
+	jsr @@16:8
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/branchs.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/branchs.s
new file mode 100644
index 00000000000..8f33e17967a
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/branchs.s
@@ -0,0 +1,12 @@
+	.h8300s
+	.text
+h8300s_branches:
+	bsr h8300s_branches:8
+	bsr h8300s_branches:16
+	jmp h8300s_branches
+	jmp @er0
+	jmp @@16:8
+	jsr h8300s_branches
+	jsr @er0
+	jsr @@16:8
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/cbranchs.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/cbranchs.s
new file mode 100644
index 00000000000..14222ea7721
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/cbranchs.s
@@ -0,0 +1,44 @@
+	.text
+	.h8300s
+h8300s_cbranch:
+	bra h8300s_cbranch:8
+	bt h8300s_cbranch:8
+	brn h8300s_cbranch:8
+	bf h8300s_cbranch:8
+	bhi h8300s_cbranch:8
+	bls h8300s_cbranch:8
+	bcc h8300s_cbranch:8
+	bhs h8300s_cbranch:8
+	bcs h8300s_cbranch:8
+	blo h8300s_cbranch:8
+	bne h8300s_cbranch:8
+	beq h8300s_cbranch:8
+	bvc h8300s_cbranch:8
+	bvs h8300s_cbranch:8
+	bpl h8300s_cbranch:8
+	bmi h8300s_cbranch:8
+	bge h8300s_cbranch:8
+	blt h8300s_cbranch:8
+	bgt h8300s_cbranch:8
+	ble h8300s_cbranch:8
+	bra h8300s_cbranch:16
+	bt h8300s_cbranch:16
+	brn h8300s_cbranch:16
+	bf h8300s_cbranch:16
+	bhi h8300s_cbranch:16
+	bls h8300s_cbranch:16
+	bcc h8300s_cbranch:16
+	bhs h8300s_cbranch:16
+	bcs h8300s_cbranch:16
+	blo h8300s_cbranch:16
+	bne h8300s_cbranch:16
+	beq h8300s_cbranch:16
+	bvc h8300s_cbranch:16
+	bvs h8300s_cbranch:16
+	bpl h8300s_cbranch:16
+	bmi h8300s_cbranch:16
+	bge h8300s_cbranch:16
+	blt h8300s_cbranch:16
+	bgt h8300s_cbranch:16
+	ble h8300s_cbranch:16
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/compares.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/compares.s
new file mode 100644
index 00000000000..e23f3fe8e94
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/compares.s
@@ -0,0 +1,10 @@
+	.h8300s
+	.text
+h8300s_cmp:
+	cmp.b #0,r0l
+	cmp.b r0h,r0l
+	cmp.w #32,r0
+	cmp.w r0,r1
+	cmp.l #64,er0
+	cmp.l er0,er1
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/decimals.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/decimals.s
new file mode 100644
index 00000000000..b7802fcf1ac
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/decimals.s
@@ -0,0 +1,6 @@
+	.h8300s
+	.text
+h8300s_decimal:
+	daa r0l
+	das r0l
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/divmuls.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/divmuls.s
new file mode 100644
index 00000000000..db60f8f49aa
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/divmuls.s
@@ -0,0 +1,12 @@
+	.h8300h
+	.text
+h8300h_div_mul:
+	divxu.b r0l,r1
+	divxu.w r0,er1
+	divxs.b r0l,r1
+	divxs.w r0,er1
+	mulxu.b r0l,r1
+	mulxu.w r0,er1
+	mulxs.b r0l,r1
+	mulxs.w r0,er1
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/extends.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/extends.s
new file mode 100644
index 00000000000..a26e9ba70a3
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/extends.s
@@ -0,0 +1,8 @@
+	.h8300s
+	.text
+h8300s_extend:
+	exts.w r0
+	exts.l er0
+	extu.w r0
+	extu.l er0
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/incdecs.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/incdecs.s
new file mode 100644
index 00000000000..2345708b023
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/incdecs.s
@@ -0,0 +1,14 @@
+	.h8300s
+	.text
+h8300s_incdec:
+	dec.b r0l
+	dec.w #1,r0
+	dec.w #2,r0
+	dec.l #1,er0
+	dec.l #2,er0
+	inc.b r0l
+	inc.w #1,r0
+	inc.w #2,r0
+	inc.l #1,er0
+	inc.l #2,er0
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/logicals.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/logicals.s
new file mode 100644
index 00000000000..c3c4cbaaf0f
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/logicals.s
@@ -0,0 +1,34 @@
+	.h8300s
+	.text
+h8300s_logical:
+	and.b #16,r1l
+	and.b r1l,r1h
+	and.w #32,r1
+	and.w r1,r1
+	and.l #64,er1
+	and.l er1,er1
+	andc #16,ccr
+	andc #16,exr
+	or.b #16,r0l
+	or.b r1l,r0l
+	or.w #32,r1
+	or.w r1,r1
+	or.l #64,er1
+	or.l er1,er1
+	orc #16,ccr
+	orc #16,exr
+	xor.b #16,r0l
+	xor.b r0l,r1l
+	xor.w #32,r1
+	xor.w r1,r1
+	xor.l #64,er1
+	xor.l er1,er1
+	xorc #16,ccr
+	xorc #16,exr
+	neg.b r0l
+	neg.w r0
+	neg.l er0
+	not.b r0l
+	not.w r0
+	not.l er0
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/macs.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/macs.s
new file mode 100644
index 00000000000..3623ea36117
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/macs.s
@@ -0,0 +1,9 @@
+	.h8300s
+	.text
+h8300s_mac:
+	clrmac
+	ldmac er0,mach
+	ldmac er1,macl
+	mac @er0+,@er1+
+	
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/miscs.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/miscs.s
new file mode 100644
index 00000000000..d37a1770c75
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/miscs.s
@@ -0,0 +1,41 @@
+	.h8300s
+	.text
+h8300s_misc:
+	eepmov.b
+ 	eepmov.w
+	ldc.b #0,ccr
+	ldc.b r0l,ccr
+	ldc.b #0,exr
+	ldc.b r0l,exr
+	ldc.w @er0,ccr
+	ldc.w @(16:16,er0),ccr
+	ldc.w @(32:32,er0),ccr
+	ldc.w @er0+,ccr
+	ldc.w @h8300s_misc:16,ccr
+	ldc.w @h8300s_misc:32,ccr
+	ldc.w @er0,exr
+	ldc.w @(16:16,er0),exr
+	ldc.w @(32:32,er0),exr
+	ldc.w @er0+,exr
+	ldc.w @h8300s_misc:16,exr
+	ldc.w @h8300s_misc:32,exr
+;	movfpe 16:16,r0l
+;	movtpe r0l,16:16
+	nop
+	rte
+	rts
+	sleep
+	stc.b ccr,r0l
+	stc.b exr,r0l
+	stc.w ccr,@er0
+	stc.w ccr,@(16:16,er0)
+	stc.w ccr,@(32:32,er0)
+	stc.w ccr,@-er0
+	stc.w ccr,@h8300s_misc:16
+	stc.w ccr,@h8300s_misc:32
+	stc.w exr,@er0
+	stc.w exr,@(16:16,er0)
+	stc.w exr,@(32:32,er0)
+	stc.w exr,@-er0
+	stc.w exr,@h8300s_misc:16
+	stc.w exr,@h8300s_misc:32
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/movbs.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/movbs.s
new file mode 100644
index 00000000000..925002c811a
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/movbs.s
@@ -0,0 +1,20 @@
+	.h8300s
+	.text
+h8300s_movb:
+	mov.b r0l,r1l
+	mov.b #16,r0l
+	mov.b @er1,r0l
+	mov.b @(16:16,er1),r0l
+	mov.b @(32:32,er1),r0l
+	mov.b @er1+,r0l
+	mov.b @16:8,r0l
+	mov.b @h8300s_movb:16,r0l
+	mov.b @h8300s_movb:32,r0l
+	mov.b r0l,@er1
+	mov.b r0l,@(16:16,er1)
+	mov.b r0l,@(32:32,er1)
+	mov.b r0l,@-er1
+	mov.b r0l,@16:8
+	mov.b r0l,@h8300s_movb:16
+	mov.b r0l,@h8300s_movb:32
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/movls.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/movls.s
new file mode 100644
index 00000000000..46437677389
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/movls.s
@@ -0,0 +1,18 @@
+	.h8300s
+	.text
+h8300s_movl:
+	mov.l er0,er1
+	mov.l #64,er0
+	mov.l @er1,er0
+	mov.l @(16:16,er1),er0
+	mov.l @(32:32,er1),er0
+	mov.l @er1+,er0
+	mov.l @h8300s_movl:16,er0
+	mov.l @h8300s_movl:32,er0
+	mov.l er0,@er1
+	mov.l er0,@(16:16,er1)
+	mov.l er0,@(32:32,er1)
+	mov.l er0,@-er1
+	mov.l er0,@h8300s_movl:16
+	mov.l er0,@h8300s_movl:32
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/movws.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/movws.s
new file mode 100644
index 00000000000..a4f21df2542
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/movws.s
@@ -0,0 +1,18 @@
+	.h8300s
+	.text
+h8300s_movw:
+	mov.w r0,r1
+	mov.w #16,r0
+	mov.w @er1,r0
+	mov.w @(16:16,er1),r0
+	mov.w @(32:32,er1),r0
+	mov.w @er1+,r0
+	mov.w @h8300s_movw:16,r0
+	mov.w @h8300s_movw:32,r0
+	mov.w r0,@er1
+	mov.w r0,@(16:16,er1)
+	mov.w r0,@(32:32,er1)
+	mov.w r0,@-er1
+	mov.w r0,@h8300s_movw:16
+	mov.w r0,@h8300s_movw:32
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/multiples.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/multiples.s
new file mode 100644
index 00000000000..52079b6d219
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/multiples.s
@@ -0,0 +1,10 @@
+	.h8300s
+	.text
+h8300s_multiple:
+	ldm.l @sp+,er0-er1
+	ldm.l @sp+,er0-er2
+	ldm.l @sp+,er0-er3
+	stm.l er0-er1,@-sp
+	stm.l er0-er2,@-sp
+	stm.l er0-er3,@-sp
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/pushpops.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/pushpops.s
new file mode 100644
index 00000000000..741df04ecc5
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/pushpops.s
@@ -0,0 +1,8 @@
+	.h8300s
+	.text
+h8300s_push_pop:
+	pop.w r0
+	pop.l er0
+	push.w r0
+	push.l er0
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/rotsh.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/rotsh.s
new file mode 100644
index 00000000000..a9aa87df95e
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/rotsh.s
@@ -0,0 +1,11 @@
+	.text
+h8300_rotate_shift:
+	rotl r0l
+	rotr r0l
+	rotxl r0l
+	rotxr r0l
+	shal r0l
+	shar r0l
+	shll r0l
+	shlr r0l
+
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/rotshh.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/rotshh.s
new file mode 100644
index 00000000000..c7abe40a28f
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/rotshh.s
@@ -0,0 +1,27 @@
+	.h8300h
+	.text
+h8300h_rotate_shift:
+	rotl.b r0l
+	rotl.w r0
+	rotl.l er0
+	rotr.b r0l
+	rotr.w r0
+	rotr.l er0
+	rotxl.b r0l
+	rotxl.w r0
+	rotxl.l er0
+	rotxr.b r0l
+	rotxr.w r0
+	rotxr.l er0
+	shal.b r0l
+	shal.w r0
+	shal.l er0
+	shar.b r0l
+	shar.w r0
+	shar.l er0
+	shll.b r0l
+	shll.w r0
+	shll.l er0
+	shlr.b r0l
+	shlr.w r0
+	shlr.l er0
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/rotshs.s b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/rotshs.s
new file mode 100644
index 00000000000..36c41cb59c5
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/h8300/rotshs.s
@@ -0,0 +1,51 @@
+	.h8300s
+	.text
+h8300s_rotate_shift:
+	rotl.b r0l
+	rotl.b #2,r0l
+	rotl.w r0
+	rotl.w #2,r0
+	rotl.l er0
+	rotl.l #2,er0
+	rotr.b r0l
+	rotr.b #2,r0l
+	rotr.w r0
+	rotr.w #2,r0
+	rotr.l er0
+	rotr.l #2,er0
+	rotxl.b r0l
+	rotxl.b #2,r0l
+	rotxl.w r0
+	rotxl.w #2,r0
+	rotxl.l er0
+	rotxl.l #2,er0
+	rotxr.b r0l
+	rotxr.b #2,r0l
+	rotxr.w r0
+	rotxr.w #2,r0
+	rotxr.l er0
+	rotxr.l #2,er0
+	shal.b r0l
+	shal.b #2,r0l
+	shal.w r0
+	shal.w #2,r0
+	shal.l er0
+	shal.l #2,er0
+	shar.b r0l
+	shar.b #2,r0l
+	shar.w r0
+	shar.w #2,r0
+	shar.l er0
+	shar.l #2,er0
+	shll.b r0l
+	shll.b #2,r0l
+	shll.w r0
+	shll.w #2,r0
+	shll.l er0
+	shll.l #2,er0
+	shlr.b r0l
+	shlr.b #2,r0l
+	shlr.w r0
+	shlr.w #2,r0
+	shlr.l er0
+	shlr.l #2,er0
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/m68k/pcrel.d b/gnu/usr.bin/binutils/gas/testsuite/gas/m68k/pcrel.d
new file mode 100644
index 00000000000..c5ced5bf2e1
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/m68k/pcrel.d
@@ -0,0 +1,88 @@
+#name: pcrel
+#objdump: -drs -j .text
+
+.*:     file format .*
+
+Contents of section .text:
+ 0000 4e714e71 4cfa0300 fffa4cfa 0300fff4  NqNqL.....L.....
+ 0010 4cfb0300 08ee41fa ffea41fa ffe641fa  L.....A...A...A.
+ 0020 ff6241fb 08de41fb 08da41fb 08d641fb  .bA...A...A...A.
+ 0030 0920ffd2 41fb0920 ffcc41fb 0930ffff  . ..A.. ..A..0..
+ 0040 ffc641fb 0930ffff ffbe4e71 61ff0000  ..A..0....Nqa...
+ 0050 00586100 0052614e 614c4e71 41f90000  .Xa..RaNaLNqA...
+ 0060 00(a6|00)41fa 004241fa 00be41fb 083a41fb  ..A..BA...A..:A.
+ 0070 083641fb 083241fb 0920002e 41fb0920  .6A..2A.. ..A.. 
+ 0080 002841fb 09300000 002241fb 09300000  .\(A..0..."A..0..
+ 0090 001a41fb 09300000 001241fb 0920000a  ..A..0....A.. ..
+ 00a0 41fb0804 4e714e71 4e7141fb 088041fb  A...NqNqNqA...A.
+ 00b0 0920ff7f 41fb0920 800041fb 0930ffff  . ..A.. ..A..0..
+ 00c0 7fff4e71 41fb087f 41fb0920 008041fb  ..NqA...A.. ..A.
+ 00d0 09207fff 41fb0930 00008000 4e7141fa  . ..A..0....NqA.
+ 00e0 800041fb 0170ffff 7fff4e71 41fa7fff  ..A..p....NqA...
+ 00f0 41fb0170 00008000 4e7141fb 0170(ffff|0000)  A..p....NqA..p..
+ 0100 (ff04|0000)41fb 0930(ffff|0000) (fefc|0000)4e71 41f90000  ..A..0....NqA...
+ 0110 0000...............................  ................
+Disassembly of section \.text:
+0+0000 <.*> nop
+0+0002 <lbl_b> nop
+0+0004 <lbl_b\+2> moveml 0+0002 <lbl_b>,%a0-%a1
+0+000a <lbl_b\+8> moveml 0+0002 <lbl_b>,%a0-%a1
+0+0010 <lbl_b\+e> moveml %pc@\(0+02 <lbl_b>,%d0:l\),%a0-%a1
+0+0016 <lbl_b\+14> lea 0+0002 <lbl_b>,%a0
+0+001a <lbl_b\+18> lea 0+0002 <lbl_b>,%a0
+0+001e <lbl_b\+1c> lea f+ff82 <.*>,%a0
+0+0022 <lbl_b\+20> lea %pc@\(0+02 <lbl_b>,%d0:l\),%a0
+0+0026 <lbl_b\+24> lea %pc@\(0+02 <lbl_b>,%d0:l\),%a0
+0+002a <lbl_b\+28> lea %pc@\(0+02 <lbl_b>,%d0:l\),%a0
+0+002e <lbl_b\+2c> lea %pc@\(0+02 <lbl_b>,%d0:l\),%a0
+0+0034 <lbl_b\+32> lea %pc@\(0+02 <lbl_b>,%d0:l\),%a0
+0+003a <lbl_b\+38> lea %pc@\(0+02 <lbl_b>,%d0:l\),%a0
+0+0042 <lbl_b\+40> lea %pc@\(0+02 <lbl_b>,%d0:l\),%a0
+0+004a <lbl_b\+48> nop
+0+004c <lbl_b\+4a> bsrl 0+00a6 <lbl_a>
+0+0052 <lbl_b\+50> bsrw 0+00a6 <lbl_a>
+0+0056 <lbl_b\+54> bsrs 0+00a6 <lbl_a>
+0+0058 <lbl_b\+56> bsrs 0+00a6 <lbl_a>
+0+005a <lbl_b\+58> nop
+0+005c <lbl_b\+5a> lea (0+00a6 <lbl_a>|0+0 <.*>),%a0
+		RELOC: 0+005e (32 \.text|R_68K_32 \.text\+0x0+00a6)
+0+0062 <lbl_b\+60> lea 0+00a6 <lbl_a>,%a0
+0+0066 <lbl_b\+64> lea 0+0126 <.*>,%a0
+0+006a <lbl_b\+68> lea %pc@\(0+a6 <lbl_a>,%d0:l\),%a0
+0+006e <lbl_b\+6c> lea %pc@\(0+a6 <lbl_a>,%d0:l\),%a0
+0+0072 <lbl_b\+70> lea %pc@\(0+a6 <lbl_a>,%d0:l\),%a0
+0+0076 <lbl_b\+74> lea %pc@\(0+a6 <lbl_a>,%d0:l\),%a0
+0+007c <lbl_b\+7a> lea %pc@\(0+a6 <lbl_a>,%d0:l\),%a0
+0+0082 <lbl_b\+80> lea %pc@\(0+a6 <lbl_a>,%d0:l\),%a0
+0+008a <lbl_b\+88> lea %pc@\(0+a6 <lbl_a>,%d0:l\),%a0
+0+0092 <lbl_b\+90> lea %pc@\(0+a6 <lbl_a>,%d0:l\),%a0
+0+009a <lbl_b\+98> lea %pc@\(0+a6 <lbl_a>,%d0:l\),%a0
+0+00a0 <lbl_b\+9e> lea %pc@\(0+a6 <lbl_a>,%d0:l\),%a0
+0+00a4 <lbl_b\+a2> nop
+0+00a6 <lbl_a> nop
+0+00a8 <lbl_a\+2> nop
+0+00aa <lbl_a\+4> lea %pc@\(0+2c <lbl_b\+2a>,%d0:l\),%a0
+0+00ae <lbl_a\+8> lea %pc@\(0+2f <lbl_b\+2d>,%d0:l\),%a0
+0+00b4 <lbl_a\+e> lea %pc@\(f+80b6 <.*>,%d0:l\),%a0
+0+00ba <lbl_a\+14> lea %pc@\(f+80bb <.*>,%d0:l\),%a0
+0+00c2 <lbl_a\+1c> nop
+0+00c4 <lbl_a\+1e> lea %pc@\(0+145 <.*>,%d0:l\),%a0
+0+00c8 <lbl_a\+22> lea %pc@\(0+14a <.*>,%d0:l\),%a0
+0+00ce <lbl_a\+28> lea %pc@\(0+80cf <.*>,%d0:l\),%a0
+0+00d4 <lbl_a\+2e> lea %pc@\(0+80d6 <.*>,%d0:l\),%a0
+0+00dc <lbl_a\+36> nop
+0+00de <lbl_a\+38> lea f+80e0 <.*>,%a0
+0+00e2 <lbl_a\+3c> lea %pc@\(f+80e3 <.*>\),%a0
+0+00ea <lbl_a\+44> nop
+0+00ec <lbl_a\+46> lea 0+80ed <.*>,%a0
+0+00f0 <lbl_a\+4a> lea %pc@\(0+80f2 <.*>\),%a0
+0+00f8 <lbl_a\+52> nop
+0+00fa <lbl_a\+54> lea %pc@\((0+0 <.*>|0+0fc <lbl_a\+56>)\),%a0
+		RELOC: 0+00fe (DISP32 undef|R_68K_PC32 undef\+0x0+02)
+0+0102 <lbl_a\+5c> lea %pc@\((0+0 <.*>|0+0104 <lbl_a\+5e>),%d0:l\),%a0
+		RELOC: 0+0106 (DISP32 undef|R_68K_PC32 undef\+0x0+02)
+0+010a <lbl_a\+64> nop
+0+010c <lbl_a\+66> lea 0+0 <.*>,%a0
+		RELOC: 0+010e (R_68K_)?32 undef
+0+0112 <lbl_a\+6c> nop
+\.\.\.
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/m68k/pcrel.s b/gnu/usr.bin/binutils/gas/testsuite/gas/m68k/pcrel.s
new file mode 100644
index 00000000000..9c5c22b90fb
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/m68k/pcrel.s
@@ -0,0 +1,59 @@
+	nop
+lbl_b:	nop
+	moveml	lbl_b,%a0-%a1
+	moveml	%pc@(lbl_b),%a0-%a1
+	moveml	%pc@(lbl_b,%d0),%a0-%a1
+	lea	lbl_b,%a0
+	lea	%pc@(lbl_b),%a0
+	lea	%pc@(lbl_b-128),%a0
+	lea	%pc@(lbl_b,%d0),%a0
+	lea	%pc@(lbl_b:b,%d0),%a0
+	lea	%pc@(lbl_b-.-2:b,%d0),%a0
+	lea	%pc@(lbl_b:w,%d0),%a0
+	lea	%pc@(lbl_b-.-2:w,%d0),%a0
+	lea	%pc@(lbl_b:l,%d0),%a0
+	lea	%pc@(lbl_b-.-2:l,%d0),%a0
+	nop
+	bsrl	lbl_a
+	bsr	lbl_a
+	bsrs	lbl_a
+	jbsr	lbl_a
+	nop
+	lea	lbl_a,%a0
+	lea	%pc@(lbl_a),%a0
+	lea	%pc@(lbl_a+128),%a0
+	lea	%pc@(lbl_a,%d0),%a0
+	lea	%pc@(lbl_a:b,%d0),%a0
+	lea	%pc@(lbl_a-.-2:b,%d0),%a0
+	lea	%pc@(lbl_a:w,%d0),%a0
+	lea	%pc@(lbl_a-.-2:w,%d0),%a0
+	lea	%pc@(lbl_a:l,%d0),%a0
+	lea	%pc@(lbl_a-.-2:l,%d0),%a0
+	lea	%pc@(18:l,%d0),%a0
+	lea	%pc@(10:w,%d0),%a0
+	lea	%pc@(4:b,%d0),%a0
+	nop
+lbl_a:	nop
+	nop
+	lea	%pc@(.-126,%d0),%a0
+	lea	%pc@(.-127,%d0),%a0
+	lea	%pc@(.-32766,%d0),%a0
+	lea	%pc@(.-32767,%d0),%a0
+	nop
+	lea	%pc@(.+129,%d0),%a0
+	lea	%pc@(.+130,%d0),%a0
+	lea	%pc@(.+32769,%d0),%a0
+	lea	%pc@(.+32770,%d0),%a0
+	nop
+	lea	%pc@(.-32766),%a0
+	lea	%pc@(.-32767),%a0
+	nop
+	lea	%pc@(.+32769),%a0
+	lea	%pc@(.+32770),%a0
+	nop
+	lea	%pc@(undef),%a0
+	lea	%pc@(undef,%d0),%a0
+	nop
+	lea	undef,%a0
+	nop
+	.long 0
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/mips/div-ilocks.d b/gnu/usr.bin/binutils/gas/testsuite/gas/mips/div-ilocks.d
new file mode 100644
index 00000000000..282fb41ed50
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/mips/div-ilocks.d
@@ -0,0 +1,117 @@
+#objdump: -dr
+#name: MIPS div
+#source: div.s
+
+# Test the div macro.
+
+.*: +file format .*mips.*
+
+No symbols in .*
+Disassembly of section .text:
+0+0000 div \$zero,\$a0,\$a1
+0+0004 div \$zero,\$a0,\$a1
+0+0008 bnez \$a1,0+0014
+...
+0+0010 break 0x7
+0+0014 li \$at,-1
+0+0018 bne \$a1,\$at,0+002c
+0+001c lui \$at,0x8000
+0+0020 bne \$a0,\$at,0+002c
+...
+0+0028 break 0x6
+0+002c mflo \$a0
+0+0030 div \$zero,\$a1,\$a2
+0+0034 bnez \$a2,0+0040
+...
+0+003c break 0x7
+0+0040 li \$at,-1
+0+0044 bne \$a2,\$at,0+0058
+0+0048 lui \$at,0x8000
+0+004c bne \$a1,\$at,0+0058
+...
+0+0054 break 0x6
+0+0058 mflo \$a0
+0+005c move \$a0,\$a0
+0+0060 move \$a0,\$a1
+0+0064 neg \$a0,\$a0
+0+0068 neg \$a0,\$a1
+0+006c li \$at,2
+0+0070 div \$zero,\$a0,\$at
+0+0074 mflo \$a0
+0+0078 li \$at,2
+0+007c div \$zero,\$a1,\$at
+0+0080 mflo \$a0
+0+0084 li \$at,0x8000
+0+0088 div \$zero,\$a0,\$at
+0+008c mflo \$a0
+0+0090 li \$at,0x8000
+0+0094 div \$zero,\$a1,\$at
+0+0098 mflo \$a0
+0+009c li \$at,-32768
+0+00a0 div \$zero,\$a0,\$at
+0+00a4 mflo \$a0
+0+00a8 li \$at,-32768
+0+00ac div \$zero,\$a1,\$at
+0+00b0 mflo \$a0
+0+00b4 lui \$at,0x1
+0+00b8 div \$zero,\$a0,\$at
+0+00bc mflo \$a0
+0+00c0 lui \$at,0x1
+0+00c4 div \$zero,\$a1,\$at
+0+00c8 mflo \$a0
+0+00cc lui \$at,0x1
+0+00d0 ori \$at,\$at,0xa5a5
+0+00d4 div \$zero,\$a0,\$at
+0+00d8 mflo \$a0
+0+00dc lui \$at,0x1
+0+00e0 ori \$at,\$at,0xa5a5
+0+00e4 div \$zero,\$a1,\$at
+0+00e8 mflo \$a0
+0+00ec divu \$zero,\$a0,\$a1
+0+00f0 divu \$zero,\$a0,\$a1
+0+00f4 bnez \$a1,0+0100
+...
+0+00fc break 0x7
+0+0100 mflo \$a0
+0+0104 divu \$zero,\$a1,\$a2
+0+0108 bnez \$a2,0+0114
+...
+0+0110 break 0x7
+0+0114 mflo \$a0
+0+0118 move \$a0,\$a0
+0+011c div \$zero,\$a1,\$a2
+0+0120 bnez \$a2,0+012c
+...
+0+0128 break 0x7
+0+012c li \$at,-1
+0+0130 bne \$a2,\$at,0+0144
+0+0134 lui \$at,0x8000
+0+0138 bne \$a1,\$at,0+0144
+...
+0+0140 break 0x6
+0+0144 mfhi \$a0
+0+0148 li \$at,2
+0+014c divu \$zero,\$a1,\$at
+0+0150 mfhi \$a0
+0+0154 ddiv \$zero,\$a1,\$a2
+0+0158 bnez \$a2,0+0164
+...
+0+0160 break 0x7
+0+0164 daddiu \$at,\$zero,-1
+0+0168 bne \$a2,\$at,0+0180
+0+016c daddiu \$at,\$zero,1
+0+0170 dsll32 \$at,\$at,0x1f
+0+0174 bne \$a1,\$at,0+0180
+...
+0+017c break 0x6
+0+0180 mflo \$a0
+0+0184 li \$at,2
+0+0188 ddivu \$zero,\$a1,\$at
+0+018c mflo \$a0
+0+0190 li \$at,0x8000
+0+0194 ddiv \$zero,\$a1,\$at
+0+0198 mfhi \$a0
+0+019c li \$at,-32768
+0+01a0 ddivu \$zero,\$a1,\$at
+0+01a4 mfhi \$a0
+...
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/mips/mul-ilocks.d b/gnu/usr.bin/binutils/gas/testsuite/gas/mips/mul-ilocks.d
new file mode 100644
index 00000000000..257e2ad4c64
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/mips/mul-ilocks.d
@@ -0,0 +1,81 @@
+#objdump: -dr
+#name: MIPS mul
+#source: mul.s
+
+# Test the mul macro.
+
+.*: +file format .*mips.*
+
+No symbols in .*
+Disassembly of section .text:
+0+0000 multu \$a0,\$a1
+0+0004 mflo \$a0
+0+0008 multu \$a1,\$a2
+0+000c mflo \$a0
+0+0010 li \$at,0
+0+0014 mult \$a1,\$at
+0+0018 mflo \$a0
+0+001c li \$at,1
+0+0020 mult \$a1,\$at
+0+0024 mflo \$a0
+0+0028 li \$at,0x8000
+0+002c mult \$a1,\$at
+0+0030 mflo \$a0
+0+0034 li \$at,-32768
+0+0038 mult \$a1,\$at
+0+003c mflo \$a0
+0+0040 lui \$at,0x1
+0+0044 mult \$a1,\$at
+0+0048 mflo \$a0
+0+004c lui \$at,0x1
+0+0050 ori \$at,\$at,0xa5a5
+0+0054 mult \$a1,\$at
+0+0058 mflo \$a0
+0+005c mult \$a0,\$a1
+0+0060 mflo \$a0
+0+0064 sra \$a0,\$a0,0x1f
+0+0068 mfhi \$at
+0+006c beq \$a0,\$at,0+78
+...
+0+0074 break 0x6
+0+0078 mflo \$a0
+0+007c mult \$a1,\$a2
+0+0080 mflo \$a0
+0+0084 sra \$a0,\$a0,0x1f
+0+0088 mfhi \$at
+0+008c beq \$a0,\$at,0+98
+...
+0+0094 break 0x6
+0+0098 mflo \$a0
+0+009c multu \$a0,\$a1
+0+00a0 mfhi \$at
+0+00a4 mflo \$a0
+0+00a8 beqz \$at,0+b4
+...
+0+00b0 break 0x6
+0+00b4 multu \$a1,\$a2
+0+00b8 mfhi \$at
+0+00bc mflo \$a0
+0+00c0 beqz \$at,0+cc
+...
+0+00c8 break 0x6
+0+00cc dmultu \$a1,\$a2
+0+00d0 mflo \$a0
+0+00d4 li \$at,1
+0+00d8 dmult \$a1,\$at
+0+00dc mflo \$a0
+0+00e0 dmult \$a1,\$a2
+0+00e4 mflo \$a0
+0+00e8 dsra32 \$a0,\$a0,0x1f
+0+00ec mfhi \$at
+0+00f0 beq \$a0,\$at,0+fc
+...
+0+00f8 break 0x6
+0+00fc mflo \$a0
+0+0100 dmultu \$a1,\$a2
+0+0104 mfhi \$at
+0+0108 mflo \$a0
+0+010c beqz \$at,0+118
+...
+0+0114 break 0x6
+...
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/sh/basic.exp b/gnu/usr.bin/binutils/gas/testsuite/gas/sh/basic.exp
new file mode 100644
index 00000000000..869246e80c5
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/sh/basic.exp
@@ -0,0 +1,87 @@
+# Copyright (C) 1995 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+# Please email any bugs, comments, and/or additions to this file to:
+# DejaGnu@cygnus.com
+
+# Written by Cygnus Support.
+
+proc do_fp {} {
+    set testname "fp.s: floating point tests (sh3e)"
+    set x 0
+
+    gas_start "fp.s" "-al"
+
+    # Check the assembled instruction against a table built by the HP assembler
+    # Any differences should be checked by hand -- with the number of problems
+    # I've seen in the HP assembler I don't completely trust it.
+    #
+    # Instead of having a variable for each match string just increment the
+    # total number of matches seen.  That's simpler when testing large numbers
+    # of instructions (as these tests to).
+    while 1 {
+	expect {
+	    -re "^ +\[0-9\]+ 0000 F008\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0002 F00A\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0004 F009\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0006 F00B\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0008 F006\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 000a F007\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 000c F10C\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 000e F08D\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0010 F09D\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0012 F100\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0014 F101\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0016 F102\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0018 F103\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 001a F10E\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 001c F104\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 001e F105\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0020 F07D\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0022 F04D\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0024 F05D\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0026 F06D\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0028 F02D\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 002a F03D\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 002c F00D\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 002e F01D\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0030 435A\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0032 4356\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0034 436A\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0036 4366\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0038 035A\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 003a 4352\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 003c 036A\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 003e 4362\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "\[^\n\]*\n"				{ }
+	    timeout				{ perror "timeout\n"; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x==32] then { pass $testname } else { fail $testname }
+}
+
+
+if [istarget sh*-*-*] then {
+    # Test the basic instruction parser.
+    do_fp
+}
diff --git a/gnu/usr.bin/binutils/gas/testsuite/gas/sh/fp.s b/gnu/usr.bin/binutils/gas/testsuite/gas/sh/fp.s
new file mode 100644
index 00000000000..3da72499f44
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/testsuite/gas/sh/fp.s
@@ -0,0 +1,45 @@
+	.file	"test.c"
+	.data
+
+! Hitachi SH cc1 (cygnus-2.7.1-950728) arguments: -O -fpeephole
+! -ffunction-cse -freg-struct-return -fdelayed-branch -fcommon -fgnu-linker
+
+gcc2_compiled.:
+___gnu_compiled_c:
+	.text
+	.align 2
+	.global	_foo
+_foo:
+	fmov.s	@r0,fr0
+	fmov.s	fr0,@r0
+	fmov.s	@r0+,fr0
+	fmov.s	fr0,@-r0
+	fmov.s	@(r0,r0),fr0
+	fmov.s	fr0,@(r0,r0)
+	fmov	fr0,fr1
+	fldi0	fr0
+	fldi1	fr0
+	fadd	fr0,fr1
+	fsub	fr0,fr1
+	fmul	fr0,fr1
+	fdiv	fr0,fr1
+	fmac	fr0,fr0,fr1
+	fcmp/eq	fr0,fr1
+	fcmp/gt	fr0,fr1
+	ftst/nan	fr0
+	fneg	fr0
+	fabs	fr0
+	fsqrt	fr0
+	float	fpul,fr0
+	ftrc	fr0,fpul
+	fsts	fpul,fr0
+	flds	fr0,fpul
+	lds	r3,fpul
+	lds.l	@r3+,fpul
+	lds	r3,fpscr
+	lds.l	@r3+,fpscr
+	sts	fpul,r3
+	sts.l	fpul,@-r3
+	sts	fpscr,r3
+	sts.l	fpscr,@-r3
+
diff --git a/gnu/usr.bin/binutils/gprof/bb_exit_func.c b/gnu/usr.bin/binutils/gprof/bb_exit_func.c
new file mode 100644
index 00000000000..813321566c7
--- /dev/null
+++ b/gnu/usr.bin/binutils/gprof/bb_exit_func.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 1994 David Mosberger-Tang.
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Library General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ *
+ * __bb_exit_func() dumps all the basic-block statistics linked into
+ * the bb_head chain to .d files.
+ */
+#include <stdio.h>
+#include <strings.h>
+#include "bfd.h"
+#include "gmon_out.h"
+
+/* structure emitted by -a */
+struct bb {
+    long		zero_word;
+    const char		*filename;
+    long		*counts;
+    long		ncounts;
+    struct bb		*next;
+    const unsigned long	*addresses;
+};
+
+struct bb *__bb_head = (struct bb *)0;
+
+
+void
+__bb_exit_func (void)
+{
+    const int version = GMON_VERSION;
+    struct gmon_hdr ghdr;
+    struct bb *ptr;
+    FILE *fp;
+    /*
+     * GEN_GMON_CNT_FILE should be defined on systems with mcleanup()
+     * functions that do not write basic-block to gmon.out.  In such
+     * cases profiling with "-pg -a" would result in a gmon.out file
+     * without basic-block info (because the file written here would
+     * be overwritten.  Thus, a separate file is generated instead.
+     * The two files can easily be combined by specifying them
+     * on gprof's command line (and possibly generating a gmon.sum
+     * file with "gprof -s").
+     */
+#ifndef GEN_GMON_CNT_FILE
+#   define OUT_NAME	"gmon.out"
+#else
+#   define OUT_NAME	"gmon.cnt"
+#endif
+    fp = fopen(OUT_NAME, "wb");
+    if (!fp) {
+	perror(OUT_NAME);
+	return;
+    } /* if */
+    memcpy(&ghdr.cookie[0], GMON_MAGIC, 4);
+    memcpy(&ghdr.version, &version, sizeof(version));
+    fwrite(&ghdr, sizeof(ghdr), 1, fp);
+
+    for (ptr = __bb_head; ptr != 0; ptr = ptr->next) {
+	u_int ncounts = ptr->ncounts;
+	u_char tag;
+	u_int i;
+
+	tag = GMON_TAG_BB_COUNT;
+	fwrite(&tag, sizeof(tag), 1, fp);
+	fwrite(&ncounts, sizeof(ncounts), 1, fp);
+
+	for (i = 0; i < ncounts; ++i) {
+	    fwrite(&ptr->addresses[i], sizeof(ptr->addresses[0]), 1, fp);
+	    fwrite(&ptr->counts[i], sizeof(ptr->counts[0]), 1, fp);
+	} /* for */
+    } /* for */
+    fclose (fp);
+} /* __bb_exit_func */
+
+			/*** end of __bb_exit_func.c ***/
diff --git a/gnu/usr.bin/binutils/opcodes/alpha-opc.c b/gnu/usr.bin/binutils/opcodes/alpha-opc.c
new file mode 100644
index 00000000000..a64598e4e5e
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/alpha-opc.c
@@ -0,0 +1,1356 @@
+/* alpha-opc.c -- Alpha AXP opcode list
+   Copyright 1996 Free Software Foundation, Inc.
+   Contributed by Richard Henderson <rth@tamu.edu>,
+   patterned after the PPC opcode handling written by Ian Lance Taylor.
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#include <stdio.h>
+#include "ansidecl.h"
+#include "opcode/alpha.h"
+
+/* This file holds the Alpha AXP opcode table.  The opcode table
+   includes almost all of the extended instruction mnemonics.  This
+   permits the disassembler to use them, and simplifies the assembler
+   logic, at the cost of increasing the table size.  The table is
+   strictly constant data, so the compiler should be able to put it in
+   the .text section.
+
+   This file also holds the operand table.  All knowledge about
+   inserting operands into instructions and vice-versa is kept in this
+   file.  */
+
+/* Local insertion and extraction functions */
+
+static unsigned insert_rba PARAMS((unsigned, int, const char **));
+static unsigned insert_rca PARAMS((unsigned, int, const char **));
+static unsigned insert_za PARAMS((unsigned, int, const char **));
+static unsigned insert_zb PARAMS((unsigned, int, const char **));
+static unsigned insert_zc PARAMS((unsigned, int, const char **));
+static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
+static unsigned insert_jhint PARAMS((unsigned, int, const char **));
+
+static int extract_rba PARAMS((unsigned, int *));
+static int extract_rca PARAMS((unsigned, int *));
+static int extract_za PARAMS((unsigned, int *));
+static int extract_zb PARAMS((unsigned, int *));
+static int extract_zc PARAMS((unsigned, int *));
+static int extract_bdisp PARAMS((unsigned, int *));
+static int extract_jhint PARAMS((unsigned, int *));
+
+
+/* The operands table  */
+
+const struct alpha_operand alpha_operands[] = 
+{
+  /* The fields are bits, shift, insert, extract, flags */
+  /* The zero index is used to indicate end-of-list */
+#define UNUSED		0
+  { 0, 0, BFD_RELOC_UNUSED, 0, 0 },
+
+  /* The plain integer register fields */
+#define RA		(UNUSED + 1)
+  { 5, 21, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR },
+#define RB		(RA + 1)
+  { 5, 16, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR },
+#define RC		(RB + 1)
+  { 5, 0, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR },
+
+  /* The plain fp register fields */
+#define FA		(RC + 1)
+  { 5, 21, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_FPR },
+#define FB		(FA + 1)
+  { 5, 16, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_FPR },
+#define FC		(FB + 1)
+  { 5, 0, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_FPR },
+
+  /* The integer registers when they are ZERO */
+#define ZA		(FC + 1)
+  { 5, 21, BFD_RELOC_UNUSED, insert_za, extract_za, AXP_OPERAND_FAKE },
+#define ZB		(ZA + 1)
+  { 5, 16, BFD_RELOC_UNUSED, insert_zb, extract_zb, AXP_OPERAND_FAKE },
+#define ZC		(ZB + 1)
+  { 5, 0, BFD_RELOC_UNUSED, insert_zc, extract_zc, AXP_OPERAND_FAKE },
+
+  /* The RB field when it needs parentheses */
+#define PRB		(ZC + 1)
+  { 5, 16, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS },
+
+  /* The RB field when it needs parentheses _and_ a preceding comma */
+#define CPRB		(PRB + 1)
+  { 5, 16, BFD_RELOC_UNUSED, 0, 0,
+    AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA },
+
+  /* The RB field when it must be the same as the RA field */
+#define RBA		(CPRB + 1)
+  { 5, 16, BFD_RELOC_UNUSED, insert_rba, extract_rba, AXP_OPERAND_FAKE },
+
+  /* The RC field when it must be the same as the RB field */
+#define RCA		(RBA + 1)
+  { 5, 0, BFD_RELOC_UNUSED, insert_rca, extract_rca, AXP_OPERAND_FAKE },
+
+  /* The RC field when it can *default* to RA */
+#define DRC1		(RCA + 1)
+  { 5, 0, BFD_RELOC_UNUSED, 0, 0,
+    AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST },
+
+  /* The RC field when it can *default* to RB */
+#define DRC2		(DRC1 + 1)
+  { 5, 0, BFD_RELOC_UNUSED, 0, 0,
+    AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND },
+
+  /* The FC field when it can *default* to RA */
+#define DFC1		(DRC2 + 1)
+  { 5, 0, BFD_RELOC_UNUSED, 0, 0,
+    AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST },
+  
+  /* The FC field when it can *default* to RB */
+#define DFC2		(DFC1 + 1)
+  { 5, 0, BFD_RELOC_UNUSED, 0, 0,
+    AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND },
+  
+  /* The unsigned 8-bit literal of Operate format insns */
+#define LIT		(DFC2 + 1)
+  { 8, 13, BFD_RELOC_UNUSED+LIT, 0, 0, AXP_OPERAND_UNSIGNED },
+
+  /* The signed 16-bit displacement of Memory format insns.  From here
+     we can't tell what relocation should be used, so don't use a default. */
+#define MDISP		(LIT + 1)
+  { 16, 0, BFD_RELOC_UNUSED+MDISP, 0, 0, AXP_OPERAND_SIGNED },
+
+  /* The signed "23-bit" aligned displacement of Branch format insns */
+#define BDISP		(MDISP + 1)
+  { 21, 0, BFD_RELOC_23_PCREL_S2, insert_bdisp, extract_bdisp,
+    AXP_OPERAND_RELATIVE },
+
+  /* The 26-bit PALcode function */
+#define PALFN		(BDISP + 1)
+  { 26, 0, BFD_RELOC_UNUSED+PALFN, 0, 0, AXP_OPERAND_UNSIGNED },
+
+  /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
+#define JMPHINT		(PALFN + 1)
+  { 14, 0, BFD_RELOC_ALPHA_HINT, insert_jhint, extract_jhint,
+    AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW },
+
+  /* The optional hint to RET/JSR_COROUTINE */
+#define RETHINT		(JMPHINT + 1)
+  { 14, 0, BFD_RELOC_UNUSED+RETHINT, 0, 0,
+    AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO },
+
+  /* The 12-bit displacement for the ev4 hw_{ld,st} (pal1b/pal1f) insns */
+#define EV4HWDISP	(RETHINT + 1)
+  { 12, 0, BFD_RELOC_UNUSED+EV4HWDISP, 0, 0, AXP_OPERAND_SIGNED },
+
+  /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
+#define EV4HWINDEX	(EV4HWDISP + 1)
+  { 5, 0, BFD_RELOC_UNUSED+EV4HWINDEX, 0, 0, AXP_OPERAND_UNSIGNED },
+
+  /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
+     that occur in DEC PALcode.  */
+#define EV4EXTHWINDEX	(EV4HWINDEX + 1)
+  { 8, 0, BFD_RELOC_UNUSED+EV4EXTHWINDEX, 0, 0, AXP_OPERAND_UNSIGNED },
+
+  /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
+#define EV5HWDISP	(EV4EXTHWINDEX + 1)
+  { 10, 0, BFD_RELOC_UNUSED+EV5HWDISP, 0, 0, AXP_OPERAND_SIGNED },
+
+  /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
+#define EV5HWINDEX	(EV5HWDISP + 1)
+  { 16, 0, BFD_RELOC_UNUSED+EV5HWINDEX, 0, 0, AXP_OPERAND_UNSIGNED },
+};
+
+const int alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
+
+/* The RB field when it is the same as the RA field in the same insn.
+   This operand is marked fake.  The insertion function just copies
+   the RA field into the RB field, and the extraction function just
+   checks that the fields are the same. */
+
+/*ARGSUSED*/
+static unsigned
+insert_rba(insn, value, errmsg)
+     unsigned insn;
+     int value;
+     const char **errmsg;
+{
+  return insn | (((insn >> 21) & 0x1f) << 16);
+}
+
+static int
+extract_rba(insn, invalid)
+     unsigned insn;
+     int *invalid;
+{
+  if (invalid != (int *) NULL
+      && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
+    *invalid = 1;
+  return 0;
+}
+
+
+/* The same for the RC field */
+
+/*ARGSUSED*/
+static unsigned
+insert_rca(insn, value, errmsg)
+     unsigned insn;
+     int value;
+     const char **errmsg;
+{
+  return insn | ((insn >> 21) & 0x1f);
+}
+
+static int
+extract_rca(insn, invalid)
+     unsigned insn;
+     int *invalid;
+{
+  if (invalid != (int *) NULL
+      && ((insn >> 21) & 0x1f) != (insn & 0x1f))
+    *invalid = 1;
+  return 0;
+}
+
+
+/* Fake arguments in which the registers must be set to ZERO */
+
+/*ARGSUSED*/
+static unsigned
+insert_za(insn, value, errmsg)
+     unsigned insn;
+     int value;
+     const char **errmsg;
+{
+  return insn | (31 << 21);
+}
+
+static int
+extract_za(insn, invalid)
+     unsigned insn;
+     int *invalid;
+{
+  if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
+    *invalid = 1;
+  return 0;
+}
+
+/*ARGSUSED*/
+static unsigned
+insert_zb(insn, value, errmsg)
+     unsigned insn;
+     int value;
+     const char **errmsg;
+{
+  return insn | (31 << 16);
+}
+
+static int
+extract_zb(insn, invalid)
+     unsigned insn;
+     int *invalid;
+{
+  if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
+    *invalid = 1;
+  return 0;
+}
+
+/*ARGSUSED*/
+static unsigned
+insert_zc(insn, value, errmsg)
+     unsigned insn;
+     int value;
+     const char **errmsg;
+{
+  return insn | 31;
+}
+
+static int
+extract_zc(insn, invalid)
+     unsigned insn;
+     int *invalid;
+{
+  if (invalid != (int *) NULL && (insn & 0x1f) != 31)
+    *invalid = 1;
+  return 0;
+}
+
+
+/* The displacement field of a Branch format insn.  */
+
+static unsigned
+insert_bdisp(insn, value, errmsg)
+     unsigned insn;
+     int value;
+     const char **errmsg;
+{
+  if (errmsg != (const char **)NULL && (value & 3))
+    *errmsg = "branch operand unaligned";
+  return insn | ((value / 4) & 0x1FFFFF);
+}
+
+/*ARGSUSED*/
+static int
+extract_bdisp(insn, invalid)
+     unsigned insn;
+     int *invalid;
+{
+  return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
+}
+
+
+/* The hint field of a JMP/JSR insn.  */
+
+static unsigned
+insert_jhint(insn, value, errmsg)
+     unsigned insn;
+     int value;
+     const char **errmsg;
+{
+  if (errmsg != (const char **)NULL && (value & 3))
+    *errmsg = "jump hint unaligned";
+  return insn | ((value / 4) & 0xFFFF);
+}
+
+/*ARGSUSED*/
+static int
+extract_jhint(insn, invalid)
+     unsigned insn;
+     int *invalid;
+{
+  return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
+}
+
+
+/* Macros used to form opcodes */
+
+/* The main opcode */
+#define OP(x)		(((x) & 0x3F) << 26)
+#define OP_MASK		0xFC000000
+
+/* Branch format instructions */
+#define BRA_(oo)	OP(oo)
+#define BRA_MASK	OP_MASK
+#define BRA(oo)		BRA_(oo), BRA_MASK
+
+/* Floating point format instructions */
+#define FP_(oo,fff)	(OP(oo) | (((fff) & 0x7FF) << 5))
+#define FP_MASK		(OP_MASK | 0xFFE0)
+#define FP(oo,fff)	FP_(oo,fff), FP_MASK
+
+/* Memory format instructions */
+#define MEM_(oo)	OP(oo)
+#define MEM_MASK	OP_MASK
+#define MEM(oo)		MEM_(oo), MEM_MASK
+
+/* Memory/Func Code format instructions */
+#define MFC_(oo,ffff)	(OP(oo) | ((ffff) & 0xFFFF))
+#define MFC_MASK	(OP_MASK | 0xFFFF)
+#define MFC(oo,ffff)	MFC_(oo,ffff), MFC_MASK
+
+/* Memory/Branch format instructions */
+#define MBR_(oo,h)	(OP(oo) | (((h) & 3) << 14))
+#define MBR_MASK	(OP_MASK | 0xC000)
+#define MBR(oo,h)	MBR_(oo,h), MBR_MASK
+
+/* Operate format instructions.  The OPRL variant specifies a
+   literal second argument. */
+#define OPR_(oo,ff)	(OP(oo) | (((ff) & 0x7F) << 5))
+#define OPRL_(oo,ff)	(OPR_((oo),(ff)) | 0x1000)
+#define OPR_MASK	(OP_MASK | 0x1FE0)
+#define OPR(oo,ff)	OPR_(oo,ff), OPR_MASK
+#define OPRL(oo,ff)	OPRL_(oo,ff), OPR_MASK
+
+/* Generic PALcode format instructions */
+#define PCD_(oo)	OP(oo)
+#define PCD_MASK	OP_MASK
+#define PCD(oo)		PCD_(oo), PCD_MASK
+
+/* Specific PALcode instructions */
+#define SPCD_(oo,ffff)	(OP(oo) | ((ffff) & 0x3FFFFFF))
+#define SPCD_MASK	0xFFFFFFFF
+#define SPCD(oo,ffff)	SPCD_(oo,ffff), SPCD_MASK
+
+/* Hardware memory (hw_{ld,st}) instructions */
+#define EV4HWMEM_(oo,f)	(OP(oo) | (((f) & 0xF) << 12))
+#define EV4HWMEM_MASK	(OP_MASK | 0xF000)
+#define EV4HWMEM(oo,f)	EV4HWMEM_(oo,f), EV4HWMEM_MASK
+
+#define EV5HWMEM_(oo,f)	(OP(oo) | (((f) & 0x3F) << 10))
+#define EV5HWMEM_MASK	(OP_MASK | 0xF800)
+#define EV5HWMEM(oo,f)	EV5HWMEM_(oo,f), EV5HWMEM_MASK
+
+/* Common combinations of flags and arguments */
+#define ALL			AXP_OPCODE_ALL
+#define EV4			AXP_OPCODE_EV4
+#define EV5			AXP_OPCODE_EV5
+#define EV56			AXP_OPCODE_EV56
+#define EV5x			EV5|EV56
+
+#define ARG_NONE		{ 0 }
+#define ARG_BRA			{ RA, BDISP }
+#define ARG_FBRA		{ FA, BDISP }
+#define ARG_FP			{ FA, FB, DFC1 }
+#define ARG_FPZ1		{ ZA, FB, DFC1 }
+#define ARG_MEM			{ RA, MDISP, PRB }
+#define ARG_FMEM		{ FA, MDISP, PRB }
+#define ARG_OPR			{ RA, RB, DRC1 }
+#define ARG_OPRL		{ RA, LIT, DRC1 }
+#define ARG_OPRZ1		{ ZA, RB, DRC1 }
+#define ARG_OPRLZ1		{ ZA, LIT, RC }
+#define ARG_PCD			{ PALFN }
+#define ARG_EV4HWMEM		{ RA, EV4HWDISP, PRB }
+#define ARG_EV4HWMPR		{ RA, RBA, EV4HWINDEX }
+#define ARG_EV5HWMEM		{ RA, EV5HWDISP, PRB }
+
+
+/* The opcode table.
+
+   The format of the opcode table is:
+ 
+   NAME OPCODE MASK { OPERANDS }
+
+   NAME		is the name of the instruction.
+
+   OPCODE	is the instruction opcode.
+
+   MASK		is the opcode mask; this is used to tell the disassembler
+            	which bits in the actual opcode must match OPCODE.
+
+   OPERANDS	is the list of operands.
+
+   The preceding macros merge the text of the OPCODE and MASK fields.
+
+   The disassembler reads the table in order and prints the first
+   instruction which matches, so this table is sorted to put more
+   specific instructions before more general instructions. 
+
+   Otherwise, it is sorted by major opcode and minor function code.
+
+   There are three classes of not-really-instructions in this table:
+
+   ALIAS	is another name for another instruction.  Some of
+		these come from the Architecture Handbook, some
+		come from the original gas opcode tables.  In all
+		cases, the functionality of the opcode is unchanged.
+
+   PSEUDO	a stylized code form endorsed by Chapter A.4 of the
+		Architecture Handbook.
+
+   EXTRA	a stylized code form found in the original gas tables.
+
+   XXX: Can anyone shed light on the pal{19,1b,1d,1e,1f} opcodes?
+   XXX: Do we want to conditionally compile complete sets of the
+        PALcodes described in the Architecture Handbook?
+*/
+
+const struct alpha_opcode alpha_opcodes[] = {
+  { "halt",		SPCD(0x00,0x0000), ALL, ARG_NONE },
+  { "draina",		SPCD(0x00,0x0002), ALL, ARG_NONE },
+  { "bpt",		SPCD(0x00,0x0080), ALL, ARG_NONE },
+  { "callsys",		SPCD(0x00,0x0083), ALL, ARG_NONE },
+  { "chmk", 		SPCD(0x00,0x0083), ALL, ARG_NONE },
+  { "imb",		SPCD(0x00,0x0086), ALL, ARG_NONE },
+  { "call_pal",		PCD(0x00), ALL, ARG_PCD },
+  { "pal",		PCD(0x00), ALL, ARG_PCD },		/* alias */
+
+  { "lda",		MEM(0x08), ALL, ARG_MEM },
+  { "ldah",		MEM(0x09), ALL, ARG_MEM },
+  { "unop",		MEM(0x0B), ALL, { ZA } },		/* pseudo */
+  { "ldq_u",		MEM(0x0B), ALL, ARG_MEM },
+  { "stq_u",		MEM(0x0F), ALL, ARG_MEM },
+
+  { "sextl",		OPR(0x10,0x00), ALL, ARG_OPRZ1 },	/* pseudo */
+  { "sextl",		OPRL(0x10,0x00), ALL, ARG_OPRLZ1 },	/* pseudo */
+  { "addl",		OPR(0x10,0x00), ALL, ARG_OPR },
+  { "addl",		OPRL(0x10,0x00), ALL, ARG_OPRL },
+  { "s4addl",		OPR(0x10,0x02), ALL, ARG_OPR },
+  { "s4addl",		OPRL(0x10,0x02), ALL, ARG_OPRL },
+  { "negl",		OPR(0x10,0x09), ALL, ARG_OPRZ1 },	/* pseudo */
+  { "negl",		OPRL(0x10,0x09), ALL, ARG_OPRLZ1 },	/* pseudo */
+  { "subl",		OPR(0x10,0x09), ALL, ARG_OPR },
+  { "subl",		OPRL(0x10,0x09), ALL, ARG_OPRL },
+  { "s4subl",		OPR(0x10,0x0B), ALL, ARG_OPR },
+  { "s4subl",		OPRL(0x10,0x0B), ALL, ARG_OPRL },
+  { "cmpbge",		OPR(0x10,0x0F), ALL, ARG_OPR },
+  { "cmpbge",		OPRL(0x10,0x0F), ALL, ARG_OPRL },
+  { "s8addl",		OPR(0x10,0x12), ALL, ARG_OPR },
+  { "s8addl",		OPRL(0x10,0x12), ALL, ARG_OPRL },
+  { "s8subl",		OPR(0x10,0x1B), ALL, ARG_OPR },
+  { "s8subl",		OPRL(0x10,0x1B), ALL, ARG_OPRL },
+  { "cmpult",		OPR(0x10,0x1D), ALL, ARG_OPR },
+  { "cmpult",		OPRL(0x10,0x1D), ALL, ARG_OPRL },
+  { "addq",		OPR(0x10,0x20), ALL, ARG_OPR },
+  { "addq",		OPRL(0x10,0x20), ALL, ARG_OPRL },
+  { "s4addq",		OPR(0x10,0x22), ALL, ARG_OPR },
+  { "s4addq",		OPRL(0x10,0x22), ALL, ARG_OPRL },
+  { "negq", 		OPR(0x10,0x29), ALL, ARG_OPRZ1 },	/* pseudo */
+  { "negq", 		OPRL(0x10,0x29), ALL, ARG_OPRLZ1 },	/* pseudo */
+  { "subq",		OPR(0x10,0x29), ALL, ARG_OPR },
+  { "subq",		OPRL(0x10,0x29), ALL, ARG_OPRL },
+  { "s4subq",		OPR(0x10,0x2B), ALL, ARG_OPR },
+  { "s4subq",		OPRL(0x10,0x2B), ALL, ARG_OPRL },
+  { "cmpeq",		OPR(0x10,0x2D), ALL, ARG_OPR },
+  { "cmpeq",		OPRL(0x10,0x2D), ALL, ARG_OPRL },
+  { "s8addq",		OPR(0x10,0x32), ALL, ARG_OPR },
+  { "s8addq",		OPRL(0x10,0x32), ALL, ARG_OPRL },
+  { "s8subq",		OPR(0x10,0x3B), ALL, ARG_OPR },
+  { "s8subq",		OPRL(0x10,0x3B), ALL, ARG_OPRL },
+  { "cmpule",		OPR(0x10,0x3D), ALL, ARG_OPR },
+  { "cmpule",		OPRL(0x10,0x3D), ALL, ARG_OPRL },
+  { "addl/v",		OPR(0x10,0x40), ALL, ARG_OPR },
+  { "addl/v",		OPRL(0x10,0x40), ALL, ARG_OPRL },
+  { "negl/v",		OPR(0x10,0x49), ALL, ARG_OPRZ1 },	/* pseudo */
+  { "negl/v",		OPRL(0x10,0x49), ALL, ARG_OPRLZ1 },	/* pseudo */
+  { "subl/v",		OPR(0x10,0x49), ALL, ARG_OPR },
+  { "subl/v",		OPRL(0x10,0x49), ALL, ARG_OPRL },
+  { "cmplt",		OPR(0x10,0x4D), ALL, ARG_OPR },
+  { "cmplt",		OPRL(0x10,0x4D), ALL, ARG_OPRL },
+  { "addq/v",		OPR(0x10,0x60), ALL, ARG_OPR },
+  { "addq/v",		OPRL(0x10,0x60), ALL, ARG_OPRL },
+  { "negq/v",		OPR(0x10,0x69), ALL, ARG_OPRZ1 },	/* pseudo */
+  { "negq/v",		OPRL(0x10,0x69), ALL, ARG_OPRLZ1 },	/* pseudo */
+  { "subq/v",		OPR(0x10,0x69), ALL, ARG_OPR },
+  { "subq/v",		OPRL(0x10,0x69), ALL, ARG_OPRL },
+  { "cmple",		OPR(0x10,0x6D), ALL, ARG_OPR },
+  { "cmple",		OPRL(0x10,0x6D), ALL, ARG_OPRL },
+
+  { "and",		OPR(0x11,0x00), ALL, ARG_OPR },
+  { "and",		OPRL(0x11,0x00), ALL, ARG_OPRL },
+  { "andnot",		OPR(0x11,0x08), ALL, ARG_OPR },		/* alias */
+  { "andnot",		OPRL(0x11,0x08), ALL, ARG_OPRL },	/* alias */
+  { "bic",		OPR(0x11,0x08), ALL, ARG_OPR },
+  { "bic",		OPRL(0x11,0x08), ALL, ARG_OPRL },
+  { "cmovlbs",		OPR(0x11,0x14), ALL, ARG_OPR },
+  { "cmovlbs",		OPRL(0x11,0x14), ALL, ARG_OPRL },
+  { "cmovlbc",		OPR(0x11,0x16), ALL, ARG_OPR },
+  { "cmovlbc",		OPRL(0x11,0x16), ALL, ARG_OPRL },
+  { "nop",		OPR(0x11,0x20), ALL, { ZA, ZB, ZC } }, /* pseudo */
+  { "clr",		OPR(0x11,0x20), ALL, { ZA, ZB, RC } }, /* pseudo */
+  { "mov",		OPR(0x11,0x20), ALL, { ZA, RB, RC } }, /* pseudo */
+  { "mov",		OPR(0x11,0x20), ALL, { RA, RBA, RC } }, /* pseudo */
+  { "mov",		OPRL(0x11,0x20), ALL, { ZA, LIT, RC } }, /* pseudo */
+  { "or",		OPR(0x11,0x20), ALL, ARG_OPR },		/* alias */
+  { "or",		OPRL(0x11,0x20), ALL, ARG_OPRL },	/* alias */
+  { "bis",		OPR(0x11,0x20), ALL, ARG_OPR },
+  { "bis",		OPRL(0x11,0x20), ALL, ARG_OPRL },
+  { "cmoveq",		OPR(0x11,0x24), ALL, ARG_OPR },
+  { "cmoveq",		OPRL(0x11,0x24), ALL, ARG_OPRL },
+  { "cmovne",		OPR(0x11,0x26), ALL, ARG_OPR },
+  { "cmovne",		OPRL(0x11,0x26), ALL, ARG_OPRL },
+  { "not",		OPR(0x11,0x28), ALL, ARG_OPRZ1 },	/* pseudo */
+  { "not",		OPRL(0x11,0x28), ALL, ARG_OPRLZ1 },	/* pseudo */
+  { "ornot",		OPR(0x11,0x28), ALL, ARG_OPR },
+  { "ornot",		OPRL(0x11,0x28), ALL, ARG_OPRL },
+  { "xor",		OPR(0x11,0x40), ALL, ARG_OPR },
+  { "xor",		OPRL(0x11,0x40), ALL, ARG_OPRL },
+  { "cmovlt",		OPR(0x11,0x44), ALL, ARG_OPR },
+  { "cmovlt",		OPRL(0x11,0x44), ALL, ARG_OPRL },
+  { "cmovge",		OPR(0x11,0x46), ALL, ARG_OPR },
+  { "cmovge",		OPRL(0x11,0x46), ALL, ARG_OPRL },
+  { "eqv",		OPR(0x11,0x48), ALL, ARG_OPR },
+  { "eqv",		OPRL(0x11,0x48), ALL, ARG_OPRL },
+  { "xornot",		OPR(0x11,0x48), ALL, ARG_OPR },		/* alias */
+  { "xornot",		OPRL(0x11,0x48), ALL, ARG_OPRL },	/* alias */
+  { "amask",		OPR(0x11,0x61), EV56, ARG_OPRZ1 },	/* ev56 */
+  { "amask",		OPRL(0x11,0x61), EV56, ARG_OPRLZ1 },	/* ev56 */
+  { "cmovle",		OPR(0x11,0x64), ALL, ARG_OPR },
+  { "cmovle",		OPRL(0x11,0x64), ALL, ARG_OPRL },
+  { "cmovgt",		OPR(0x11,0x66), ALL, ARG_OPR },
+  { "cmovgt",		OPRL(0x11,0x66), ALL, ARG_OPRL },
+  { "implver",		OPR(0x11,0x6C), ALL, ARG_OPRZ1 },	/* ev56 */
+  { "implver",		OPRL(0x11,0x6C), ALL, ARG_OPRLZ1 },	/* ev56 */
+
+  { "mskbl",		OPR(0x12,0x02), ALL, ARG_OPR },
+  { "mskbl",		OPRL(0x12,0x02), ALL, ARG_OPRL },
+  { "extbl",		OPR(0x12,0x06), ALL, ARG_OPR },
+  { "extbl",		OPRL(0x12,0x06), ALL, ARG_OPRL },
+  { "insbl",		OPR(0x12,0x0B), ALL, ARG_OPR },
+  { "insbl",		OPRL(0x12,0x0B), ALL, ARG_OPRL },
+  { "mskwl",		OPR(0x12,0x12), ALL, ARG_OPR },
+  { "mskwl",		OPRL(0x12,0x12), ALL, ARG_OPRL },
+  { "extwl",		OPR(0x12,0x16), ALL, ARG_OPR },
+  { "extwl",		OPRL(0x12,0x16), ALL, ARG_OPRL },
+  { "inswl",		OPR(0x12,0x1B), ALL, ARG_OPR },
+  { "inswl",		OPRL(0x12,0x1B), ALL, ARG_OPRL },
+  { "mskll",		OPR(0x12,0x22), ALL, ARG_OPR },
+  { "mskll",		OPRL(0x12,0x22), ALL, ARG_OPRL },
+  { "extll",		OPR(0x12,0x26), ALL, ARG_OPR },
+  { "extll",		OPRL(0x12,0x26), ALL, ARG_OPRL },
+  { "insll",		OPR(0x12,0x2B), ALL, ARG_OPR },
+  { "insll",		OPRL(0x12,0x2B), ALL, ARG_OPRL },
+  { "zap",		OPR(0x12,0x30), ALL, ARG_OPR },
+  { "zap",		OPRL(0x12,0x30), ALL, ARG_OPRL },
+  { "zapnot",		OPR(0x12,0x31), ALL, ARG_OPR },
+  { "zapnot",		OPRL(0x12,0x31), ALL, ARG_OPRL },
+  { "mskql",		OPR(0x12,0x32), ALL, ARG_OPR },
+  { "mskql",		OPRL(0x12,0x32), ALL, ARG_OPRL },
+  { "srl",		OPR(0x12,0x34), ALL, ARG_OPR },
+  { "srl",		OPRL(0x12,0x34), ALL, ARG_OPRL },
+  { "extql",		OPR(0x12,0x36), ALL, ARG_OPR },
+  { "extql",		OPRL(0x12,0x36), ALL, ARG_OPRL },
+  { "sll",		OPR(0x12,0x39), ALL, ARG_OPR },
+  { "sll",		OPRL(0x12,0x39), ALL, ARG_OPRL },
+  { "insql",		OPR(0x12,0x3B), ALL, ARG_OPR },
+  { "insql",		OPRL(0x12,0x3B), ALL, ARG_OPRL },
+  { "sra",		OPR(0x12,0x3C), ALL, ARG_OPR },
+  { "sra",		OPRL(0x12,0x3C), ALL, ARG_OPRL },
+  { "mskwh",		OPR(0x12,0x52), ALL, ARG_OPR },
+  { "mskwh",		OPRL(0x12,0x52), ALL, ARG_OPRL },
+  { "inswh",		OPR(0x12,0x57), ALL, ARG_OPR },
+  { "inswh",		OPRL(0x12,0x57), ALL, ARG_OPRL },
+  { "extwh",		OPR(0x12,0x5A), ALL, ARG_OPR },
+  { "extwh",		OPRL(0x12,0x5A), ALL, ARG_OPRL },
+  { "msklh",		OPR(0x12,0x62), ALL, ARG_OPR },
+  { "msklh",		OPRL(0x12,0x62), ALL, ARG_OPRL },
+  { "inslh",		OPR(0x12,0x67), ALL, ARG_OPR },
+  { "inslh",		OPRL(0x12,0x67), ALL, ARG_OPRL },
+  { "extlh",		OPR(0x12,0x6A), ALL, ARG_OPR },
+  { "extlh",		OPRL(0x12,0x6A), ALL, ARG_OPRL },
+  { "mskqh",		OPR(0x12,0x72), ALL, ARG_OPR },
+  { "mskqh",		OPRL(0x12,0x72), ALL, ARG_OPRL },
+  { "insqh",		OPR(0x12,0x77), ALL, ARG_OPR },
+  { "insqh",		OPRL(0x12,0x77), ALL, ARG_OPRL },
+  { "extqh",		OPR(0x12,0x7A), ALL, ARG_OPR },
+  { "extqh",		OPRL(0x12,0x7A), ALL, ARG_OPRL },
+
+  { "mull",		OPR(0x13,0x00), ALL, ARG_OPR },
+  { "mull",		OPRL(0x13,0x00), ALL, ARG_OPRL },
+  { "mulq",		OPR(0x13,0x20), ALL, ARG_OPR },
+  { "mulq",		OPRL(0x13,0x20), ALL, ARG_OPRL },
+  { "umulh",		OPR(0x13,0x30), ALL, ARG_OPR },
+  { "umulh",		OPRL(0x13,0x30), ALL, ARG_OPRL },
+  { "mull/v",		OPR(0x13,0x40), ALL, ARG_OPR },
+  { "mull/v",		OPRL(0x13,0x40), ALL, ARG_OPRL },
+  { "mulq/v",		OPR(0x13,0x60), ALL, ARG_OPR },
+  { "mulq/v",		OPRL(0x13,0x60), ALL, ARG_OPRL },
+
+  { "addf/c",		FP(0x15,0x000), ALL, ARG_FP },
+  { "subf/c",		FP(0x15,0x001), ALL, ARG_FP },
+  { "mulf/c",		FP(0x15,0x002), ALL, ARG_FP },
+  { "divf/c",		FP(0x15,0x003), ALL, ARG_FP },
+  { "cvtdg/c",		FP(0x15,0x01E), ALL, ARG_FPZ1 },
+  { "addg/c",		FP(0x15,0x020), ALL, ARG_FP },
+  { "subg/c",		FP(0x15,0x021), ALL, ARG_FP },
+  { "mulg/c",		FP(0x15,0x022), ALL, ARG_FP },
+  { "divg/c",		FP(0x15,0x023), ALL, ARG_FP },
+  { "cvtgf/c",		FP(0x15,0x02C), ALL, ARG_FPZ1 },
+  { "cvtgd/c",		FP(0x15,0x02D), ALL, ARG_FPZ1 },
+  { "cvtgq/c",		FP(0x15,0x02F), ALL, ARG_FPZ1 },
+  { "cvtqf/c",		FP(0x15,0x03C), ALL, ARG_FPZ1 },
+  { "cvtqg/c",		FP(0x15,0x03E), ALL, ARG_FPZ1 },
+  { "addf",		FP(0x15,0x080), ALL, ARG_FP },
+  { "negf",		FP(0x15,0x081), ALL, ARG_FPZ1 },	/* pseudo */
+  { "subf",		FP(0x15,0x081), ALL, ARG_FP },
+  { "mulf",		FP(0x15,0x082), ALL, ARG_FP },
+  { "divf",		FP(0x15,0x083), ALL, ARG_FP },
+  { "cvtdg",		FP(0x15,0x09E), ALL, ARG_FPZ1 },
+  { "addg",		FP(0x15,0x0A0), ALL, ARG_FP },
+  { "negg",		FP(0x15,0x0A1), ALL, ARG_FPZ1 },	/* pseudo */
+  { "subg",		FP(0x15,0x0A1), ALL, ARG_FP },
+  { "mulg",		FP(0x15,0x0A2), ALL, ARG_FP },
+  { "divg",		FP(0x15,0x0A3), ALL, ARG_FP },
+  { "cmpgeq",		FP(0x15,0x0A5), ALL, ARG_FP },
+  { "cmpglt",		FP(0x15,0x0A6), ALL, ARG_FP },
+  { "cmpgle",		FP(0x15,0x0A7), ALL, ARG_FP },
+  { "cvtgf",		FP(0x15,0x0AC), ALL, ARG_FPZ1 },
+  { "cvtgd",		FP(0x15,0x0AD), ALL, ARG_FPZ1 },
+  { "cvtgq",		FP(0x15,0x0AF), ALL, ARG_FPZ1 },
+  { "cvtqf",		FP(0x15,0x0BC), ALL, ARG_FPZ1 },
+  { "cvtqg",		FP(0x15,0x0BE), ALL, ARG_FPZ1 },
+  { "addf/uc",		FP(0x15,0x100), ALL, ARG_FP },
+  { "subf/uc",		FP(0x15,0x101), ALL, ARG_FP },
+  { "mulf/uc",		FP(0x15,0x102), ALL, ARG_FP },
+  { "divf/uc",		FP(0x15,0x103), ALL, ARG_FP },
+  { "cvtdg/uc",		FP(0x15,0x11E), ALL, ARG_FPZ1 },
+  { "addg/uc",		FP(0x15,0x120), ALL, ARG_FP },
+  { "subg/uc",		FP(0x15,0x121), ALL, ARG_FP },
+  { "mulg/uc",		FP(0x15,0x122), ALL, ARG_FP },
+  { "divg/uc",		FP(0x15,0x123), ALL, ARG_FP },
+  { "cvtgf/uc",		FP(0x15,0x12C), ALL, ARG_FPZ1 },
+  { "cvtgd/uc",		FP(0x15,0x12D), ALL, ARG_FPZ1 },
+  { "cvtgq/vc",		FP(0x15,0x12F), ALL, ARG_FPZ1 },
+  { "addf/u",		FP(0x15,0x180), ALL, ARG_FP },
+  { "subf/u",		FP(0x15,0x181), ALL, ARG_FP },
+  { "mulf/u",		FP(0x15,0x182), ALL, ARG_FP },
+  { "divf/u",		FP(0x15,0x183), ALL, ARG_FP },
+  { "cvtdg/u",		FP(0x15,0x19E), ALL, ARG_FPZ1 },
+  { "addg/u",		FP(0x15,0x1A0), ALL, ARG_FP },
+  { "subg/u",		FP(0x15,0x1A1), ALL, ARG_FP },
+  { "mulg/u",		FP(0x15,0x1A2), ALL, ARG_FP },
+  { "divg/u",		FP(0x15,0x1A3), ALL, ARG_FP },
+  { "cvtgf/u",		FP(0x15,0x1AC), ALL, ARG_FPZ1 },
+  { "cvtgd/u",		FP(0x15,0x1AD), ALL, ARG_FPZ1 },
+  { "cvtgq/v",		FP(0x15,0x1AF), ALL, ARG_FPZ1 },
+  { "addf/sc",		FP(0x15,0x400), ALL, ARG_FP },
+  { "subf/sc",		FP(0x15,0x401), ALL, ARG_FP },
+  { "mulf/sc",		FP(0x15,0x402), ALL, ARG_FP },
+  { "divf/sc",		FP(0x15,0x403), ALL, ARG_FP },
+  { "cvtdg/sc",		FP(0x15,0x41E), ALL, ARG_FPZ1 },
+  { "addg/sc",		FP(0x15,0x420), ALL, ARG_FP },
+  { "subg/sc",		FP(0x15,0x421), ALL, ARG_FP },
+  { "mulg/sc",		FP(0x15,0x422), ALL, ARG_FP },
+  { "divg/sc",		FP(0x15,0x423), ALL, ARG_FP },
+  { "cvtgf/sc",		FP(0x15,0x42C), ALL, ARG_FPZ1 },
+  { "cvtgd/sc",		FP(0x15,0x42D), ALL, ARG_FPZ1 },
+  { "cvtgq/sc",		FP(0x15,0x42F), ALL, ARG_FPZ1 },
+  { "addf/s",		FP(0x15,0x480), ALL, ARG_FP },
+  { "negf/s",		FP(0x15,0x481), ALL, ARG_FPZ1 },	/* pseudo */
+  { "subf/s",		FP(0x15,0x481), ALL, ARG_FP },
+  { "mulf/s",		FP(0x15,0x482), ALL, ARG_FP },
+  { "divf/s",		FP(0x15,0x483), ALL, ARG_FP },
+  { "cvtdg/s",		FP(0x15,0x49E), ALL, ARG_FPZ1 },
+  { "addg/s",		FP(0x15,0x4A0), ALL, ARG_FP },
+  { "negg/s",		FP(0x15,0x4A1), ALL, ARG_FPZ1 },	/* pseudo */
+  { "subg/s",		FP(0x15,0x4A1), ALL, ARG_FP },
+  { "mulg/s",		FP(0x15,0x4A2), ALL, ARG_FP },
+  { "divg/s",		FP(0x15,0x4A3), ALL, ARG_FP },
+  { "cmpgeq/s",		FP(0x15,0x4A5), ALL, ARG_FP },
+  { "cmpglt/s",		FP(0x15,0x4A6), ALL, ARG_FP },
+  { "cmpgle/s",		FP(0x15,0x4A7), ALL, ARG_FP },
+  { "cvtgf/s",		FP(0x15,0x4AC), ALL, ARG_FPZ1 },
+  { "cvtgd/s",		FP(0x15,0x4AD), ALL, ARG_FPZ1 },
+  { "cvtgq/s",		FP(0x15,0x4AF), ALL, ARG_FPZ1 },
+  { "addf/suc",		FP(0x15,0x500), ALL, ARG_FP },
+  { "subf/suc",		FP(0x15,0x501), ALL, ARG_FP },
+  { "mulf/suc",		FP(0x15,0x502), ALL, ARG_FP },
+  { "divf/suc",		FP(0x15,0x503), ALL, ARG_FP },
+  { "cvtdg/suc",	FP(0x15,0x51E), ALL, ARG_FPZ1 },
+  { "addg/suc",		FP(0x15,0x520), ALL, ARG_FP },
+  { "subg/suc",		FP(0x15,0x521), ALL, ARG_FP },
+  { "mulg/suc",		FP(0x15,0x522), ALL, ARG_FP },
+  { "divg/suc",		FP(0x15,0x523), ALL, ARG_FP },
+  { "cvtgf/suc",	FP(0x15,0x52C), ALL, ARG_FPZ1 },
+  { "cvtgd/suc",	FP(0x15,0x52D), ALL, ARG_FPZ1 },
+  { "cvtgq/svc",	FP(0x15,0x52F), ALL, ARG_FPZ1 },
+  { "addf/su",		FP(0x15,0x580), ALL, ARG_FP },
+  { "subf/su",		FP(0x15,0x581), ALL, ARG_FP },
+  { "mulf/su",		FP(0x15,0x582), ALL, ARG_FP },
+  { "divf/su",		FP(0x15,0x583), ALL, ARG_FP },
+  { "cvtdg/su",		FP(0x15,0x59E), ALL, ARG_FPZ1 },
+  { "addg/su",		FP(0x15,0x5A0), ALL, ARG_FP },
+  { "subg/su",		FP(0x15,0x5A1), ALL, ARG_FP },
+  { "mulg/su",		FP(0x15,0x5A2), ALL, ARG_FP },
+  { "divg/su",		FP(0x15,0x5A3), ALL, ARG_FP },
+  { "cvtgf/su",		FP(0x15,0x5AC), ALL, ARG_FPZ1 },
+  { "cvtgd/su",		FP(0x15,0x5AD), ALL, ARG_FPZ1 },
+  { "cvtgq/sv",		FP(0x15,0x5AF), ALL, ARG_FPZ1 },
+
+  { "adds/c",		FP(0x16,0x000), ALL, ARG_FP },
+  { "subs/c",		FP(0x16,0x001), ALL, ARG_FP },
+  { "muls/c",		FP(0x16,0x002), ALL, ARG_FP },
+  { "divs/c",		FP(0x16,0x003), ALL, ARG_FP },
+  { "addt/c",		FP(0x16,0x020), ALL, ARG_FP },
+  { "subt/c",		FP(0x16,0x021), ALL, ARG_FP },
+  { "mult/c",		FP(0x16,0x022), ALL, ARG_FP },
+  { "divt/c",		FP(0x16,0x023), ALL, ARG_FP },
+  { "cvtts/c",		FP(0x16,0x02C), ALL, ARG_FPZ1 },
+  { "cvttq/c",		FP(0x16,0x02F), ALL, ARG_FPZ1 },
+  { "cvtqs/c",		FP(0x16,0x03C), ALL, ARG_FPZ1 },
+  { "cvtqt/c",		FP(0x16,0x03E), ALL, ARG_FPZ1 },
+  { "adds/m",		FP(0x16,0x040), ALL, ARG_FP },
+  { "subs/m",		FP(0x16,0x041), ALL, ARG_FP },
+  { "muls/m",		FP(0x16,0x042), ALL, ARG_FP },
+  { "divs/m",		FP(0x16,0x043), ALL, ARG_FP },
+  { "addt/m",		FP(0x16,0x060), ALL, ARG_FP },
+  { "subt/m",		FP(0x16,0x061), ALL, ARG_FP },
+  { "mult/m",		FP(0x16,0x062), ALL, ARG_FP },
+  { "divt/m",		FP(0x16,0x063), ALL, ARG_FP },
+  { "cvtts/m",		FP(0x16,0x06C), ALL, ARG_FPZ1 },
+  { "cvttq/m",		FP(0x16,0x06F), ALL, ARG_FPZ1 },
+  { "cvtqs/m",		FP(0x16,0x07C), ALL, ARG_FPZ1 },
+  { "cvtqt/m",		FP(0x16,0x07E), ALL, ARG_FPZ1 },
+  { "adds",		FP(0x16,0x080), ALL, ARG_FP },
+  { "negs", 		FP(0x16,0x081), ALL, ARG_FPZ1 },	/* pseudo */
+  { "subs",		FP(0x16,0x081), ALL, ARG_FP },
+  { "muls",		FP(0x16,0x082), ALL, ARG_FP },
+  { "divs",		FP(0x16,0x083), ALL, ARG_FP },
+  { "addt",		FP(0x16,0x0A0), ALL, ARG_FP },
+  { "negt", 		FP(0x16,0x0A1), ALL, ARG_FPZ1 },	/* pseudo */
+  { "subt",		FP(0x16,0x0A1), ALL, ARG_FP },
+  { "mult",		FP(0x16,0x0A2), ALL, ARG_FP },
+  { "divt",		FP(0x16,0x0A3), ALL, ARG_FP },
+  { "cmptun",		FP(0x16,0x0A4), ALL, ARG_FP },
+  { "cmpteq",		FP(0x16,0x0A5), ALL, ARG_FP },
+  { "cmptlt",		FP(0x16,0x0A6), ALL, ARG_FP },
+  { "cmptle",		FP(0x16,0x0A7), ALL, ARG_FP },
+  { "cvtts",		FP(0x16,0x0AC), ALL, ARG_FPZ1 },
+  { "cvttq",		FP(0x16,0x0AF), ALL, ARG_FPZ1 },
+  { "cvtqs",		FP(0x16,0x0BC), ALL, ARG_FPZ1 },
+  { "cvtqt",		FP(0x16,0x0BE), ALL, ARG_FPZ1 },
+  { "adds/d",		FP(0x16,0x0C0), ALL, ARG_FP },
+  { "subs/d",		FP(0x16,0x0C1), ALL, ARG_FP },
+  { "muls/d",		FP(0x16,0x0C2), ALL, ARG_FP },
+  { "divs/d",		FP(0x16,0x0C3), ALL, ARG_FP },
+  { "addt/d",		FP(0x16,0x0E0), ALL, ARG_FP },
+  { "subt/d",		FP(0x16,0x0E1), ALL, ARG_FP },
+  { "mult/d",		FP(0x16,0x0E2), ALL, ARG_FP },
+  { "divt/d",		FP(0x16,0x0E3), ALL, ARG_FP },
+  { "cvtts/d",		FP(0x16,0x0EC), ALL, ARG_FPZ1 },
+  { "cvttq/d",		FP(0x16,0x0EF), ALL, ARG_FPZ1 },
+  { "cvtqs/d",		FP(0x16,0x0FC), ALL, ARG_FPZ1 },
+  { "cvtqt/d",		FP(0x16,0x0FE), ALL, ARG_FPZ1 },
+  { "adds/uc",		FP(0x16,0x100), ALL, ARG_FP },
+  { "subs/uc",		FP(0x16,0x101), ALL, ARG_FP },
+  { "muls/uc",		FP(0x16,0x102), ALL, ARG_FP },
+  { "divs/uc",		FP(0x16,0x103), ALL, ARG_FP },
+  { "addt/uc",		FP(0x16,0x120), ALL, ARG_FP },
+  { "subt/uc",		FP(0x16,0x121), ALL, ARG_FP },
+  { "mult/uc",		FP(0x16,0x122), ALL, ARG_FP },
+  { "divt/uc",		FP(0x16,0x123), ALL, ARG_FP },
+  { "cvtts/uc",		FP(0x16,0x12C), ALL, ARG_FPZ1 },
+  { "cvttq/vc",		FP(0x16,0x12F), ALL, ARG_FPZ1 },
+  { "adds/um",		FP(0x16,0x140), ALL, ARG_FP },
+  { "subs/um",		FP(0x16,0x141), ALL, ARG_FP },
+  { "muls/um",		FP(0x16,0x142), ALL, ARG_FP },
+  { "divs/um",		FP(0x16,0x143), ALL, ARG_FP },
+  { "addt/um",		FP(0x16,0x160), ALL, ARG_FP },
+  { "subt/um",		FP(0x16,0x161), ALL, ARG_FP },
+  { "mult/um",		FP(0x16,0x162), ALL, ARG_FP },
+  { "divt/um",		FP(0x16,0x163), ALL, ARG_FP },
+  { "cvtts/um",		FP(0x16,0x16C), ALL, ARG_FPZ1 },
+  { "cvttq/um",		FP(0x16,0x16F), ALL, ARG_FPZ1 },
+  { "cvtqs/um",		FP(0x16,0x17C), ALL, ARG_FPZ1 },
+  { "adds/u",		FP(0x16,0x180), ALL, ARG_FP },
+  { "subs/u",		FP(0x16,0x181), ALL, ARG_FP },
+  { "muls/u",		FP(0x16,0x182), ALL, ARG_FP },
+  { "divs/u",		FP(0x16,0x183), ALL, ARG_FP },
+  { "addt/u",		FP(0x16,0x1A0), ALL, ARG_FP },
+  { "subt/u",		FP(0x16,0x1A1), ALL, ARG_FP },
+  { "mult/u",		FP(0x16,0x1A2), ALL, ARG_FP },
+  { "divt/u",		FP(0x16,0x1A3), ALL, ARG_FP },
+  { "cvtts/u",		FP(0x16,0x1AC), ALL, ARG_FPZ1 },
+  { "cvttq/v",		FP(0x16,0x1AF), ALL, ARG_FPZ1 },
+  { "adds/ud",		FP(0x16,0x1C0), ALL, ARG_FP },
+  { "subs/ud",		FP(0x16,0x1C1), ALL, ARG_FP },
+  { "muls/ud",		FP(0x16,0x1C2), ALL, ARG_FP },
+  { "divs/ud",		FP(0x16,0x1C3), ALL, ARG_FP },
+  { "addt/ud",		FP(0x16,0x1E0), ALL, ARG_FP },
+  { "subt/ud",		FP(0x16,0x1E1), ALL, ARG_FP },
+  { "mult/ud",		FP(0x16,0x1E2), ALL, ARG_FP },
+  { "divt/ud",		FP(0x16,0x1E3), ALL, ARG_FP },
+  { "cvtts/ud",		FP(0x16,0x1EC), ALL, ARG_FPZ1 },
+  { "cvttq/ud",		FP(0x16,0x1EF), ALL, ARG_FPZ1 },
+  { "cvtst",		FP(0x16,0x2AC), ALL, ARG_FPZ1 },
+  { "adds/suc",		FP(0x16,0x500), ALL, ARG_FP },
+  { "subs/suc",		FP(0x16,0x501), ALL, ARG_FP },
+  { "muls/suc",		FP(0x16,0x502), ALL, ARG_FP },
+  { "divs/suc",		FP(0x16,0x503), ALL, ARG_FP },
+  { "addt/suc",		FP(0x16,0x520), ALL, ARG_FP },
+  { "subt/suc",		FP(0x16,0x521), ALL, ARG_FP },
+  { "mult/suc",		FP(0x16,0x522), ALL, ARG_FP },
+  { "divt/suc",		FP(0x16,0x523), ALL, ARG_FP },
+  { "cvtts/suc",	FP(0x16,0x52C), ALL, ARG_FPZ1 },
+  { "cvttq/svc",	FP(0x16,0x52F), ALL, ARG_FPZ1 },
+  { "adds/sum",		FP(0x16,0x540), ALL, ARG_FP },
+  { "subs/sum",		FP(0x16,0x541), ALL, ARG_FP },
+  { "muls/sum",		FP(0x16,0x542), ALL, ARG_FP },
+  { "divs/sum",		FP(0x16,0x543), ALL, ARG_FP },
+  { "addt/sum",		FP(0x16,0x560), ALL, ARG_FP },
+  { "subt/sum",		FP(0x16,0x561), ALL, ARG_FP },
+  { "mult/sum",		FP(0x16,0x562), ALL, ARG_FP },
+  { "divt/sum",		FP(0x16,0x563), ALL, ARG_FP },
+  { "cvtts/sum",	FP(0x16,0x56C), ALL, ARG_FPZ1 },
+  { "cvttq/sum",	FP(0x16,0x56F), ALL, ARG_FPZ1 },
+  { "cvtqs/sum",	FP(0x16,0x57C), ALL, ARG_FPZ1 },
+  { "adds/su",		FP(0x16,0x580), ALL, ARG_FP },
+  { "negs/su",		FP(0x16,0x581), ALL, ARG_FPZ1 },	/* pseudo */
+  { "subs/su",		FP(0x16,0x581), ALL, ARG_FP },
+  { "muls/su",		FP(0x16,0x582), ALL, ARG_FP },
+  { "divs/su",		FP(0x16,0x583), ALL, ARG_FP },
+  { "addt/su",		FP(0x16,0x5A0), ALL, ARG_FP },
+  { "negt/su",		FP(0x16,0x5A1), ALL, ARG_FPZ1 },	/* pseudo */
+  { "subt/su",		FP(0x16,0x5A1), ALL, ARG_FP },
+  { "mult/su",		FP(0x16,0x5A2), ALL, ARG_FP },
+  { "divt/su",		FP(0x16,0x5A3), ALL, ARG_FP },
+  { "cmptun/su",	FP(0x16,0x5A4), ALL, ARG_FP },
+  { "cmpteq/su",	FP(0x16,0x5A5), ALL, ARG_FP },
+  { "cmptlt/su",	FP(0x16,0x5A6), ALL, ARG_FP },
+  { "cmptle/su",	FP(0x16,0x5A7), ALL, ARG_FP },
+  { "cvtts/su",		FP(0x16,0x5AC), ALL, ARG_FPZ1 },
+  { "cvttq/sv",		FP(0x16,0x5AF), ALL, ARG_FPZ1 },
+  { "adds/sud",		FP(0x16,0x5C0), ALL, ARG_FP },
+  { "subs/sud",		FP(0x16,0x5C1), ALL, ARG_FP },
+  { "muls/sud",		FP(0x16,0x5C2), ALL, ARG_FP },
+  { "divs/sud",		FP(0x16,0x5C3), ALL, ARG_FP },
+  { "addt/sud",		FP(0x16,0x5E0), ALL, ARG_FP },
+  { "subt/sud",		FP(0x16,0x5E1), ALL, ARG_FP },
+  { "mult/sud",		FP(0x16,0x5E2), ALL, ARG_FP },
+  { "divt/sud",		FP(0x16,0x5E3), ALL, ARG_FP },
+  { "cvtts/sud",	FP(0x16,0x5EC), ALL, ARG_FPZ1 },
+  { "cvttq/sud",	FP(0x16,0x5EF), ALL, ARG_FPZ1 },
+  { "cvtst/s",		FP(0x16,0x6AC), ALL, ARG_FPZ1 },
+  { "adds/suic",	FP(0x16,0x700), ALL, ARG_FP },
+  { "subs/suic",	FP(0x16,0x701), ALL, ARG_FP },
+  { "muls/suic",	FP(0x16,0x702), ALL, ARG_FP },
+  { "divs/suic",	FP(0x16,0x703), ALL, ARG_FP },
+  { "addt/suic",	FP(0x16,0x720), ALL, ARG_FP },
+  { "subt/suic",	FP(0x16,0x721), ALL, ARG_FP },
+  { "mult/suic",	FP(0x16,0x722), ALL, ARG_FP },
+  { "divt/suic",	FP(0x16,0x723), ALL, ARG_FP },
+  { "cvtts/suic",	FP(0x16,0x72C), ALL, ARG_FPZ1 },
+  { "cvttq/svic",	FP(0x16,0x72F), ALL, ARG_FPZ1 },
+  { "cvtqs/suic",	FP(0x16,0x73C), ALL, ARG_FPZ1 },
+  { "cvtqt/suic",	FP(0x16,0x73E), ALL, ARG_FPZ1 },
+  { "adds/suim",	FP(0x16,0x740), ALL, ARG_FP },
+  { "subs/suim",	FP(0x16,0x741), ALL, ARG_FP },
+  { "muls/suim",	FP(0x16,0x742), ALL, ARG_FP },
+  { "divs/suim",	FP(0x16,0x743), ALL, ARG_FP },
+  { "addt/suim",	FP(0x16,0x760), ALL, ARG_FP },
+  { "subt/suim",	FP(0x16,0x761), ALL, ARG_FP },
+  { "mult/suim",	FP(0x16,0x762), ALL, ARG_FP },
+  { "divt/suim",	FP(0x16,0x763), ALL, ARG_FP },
+  { "cvtts/suim",	FP(0x16,0x76C), ALL, ARG_FPZ1 },
+  { "cvttq/suim",	FP(0x16,0x76F), ALL, ARG_FPZ1 },
+  { "cvtqs/suim",	FP(0x16,0x77C), ALL, ARG_FPZ1 },
+  { "cvtqt/suim",	FP(0x16,0x77E), ALL, ARG_FPZ1 },
+  { "adds/sui",		FP(0x16,0x780), ALL, ARG_FP },
+  { "negs/sui", 	FP(0x16,0x781), ALL, ARG_FPZ1 },	/* pseudo */
+  { "subs/sui",		FP(0x16,0x781), ALL, ARG_FP },
+  { "muls/sui",		FP(0x16,0x782), ALL, ARG_FP },
+  { "divs/sui",		FP(0x16,0x783), ALL, ARG_FP },
+  { "addt/sui",		FP(0x16,0x7A0), ALL, ARG_FP },
+  { "negt/sui", 	FP(0x16,0x7A1), ALL, ARG_FPZ1 },	/* pseudo */
+  { "subt/sui",		FP(0x16,0x7A1), ALL, ARG_FP },
+  { "mult/sui",		FP(0x16,0x7A2), ALL, ARG_FP },
+  { "divt/sui",		FP(0x16,0x7A3), ALL, ARG_FP },
+  { "cvtts/sui",	FP(0x16,0x7AC), ALL, ARG_FPZ1 },
+  { "cvttq/svi",	FP(0x16,0x7AF), ALL, ARG_FPZ1 },
+  { "cvtqs/sui",	FP(0x16,0x7BC), ALL, ARG_FPZ1 },
+  { "cvtqt/sui",	FP(0x16,0x7BE), ALL, ARG_FPZ1 },
+  { "adds/suid",	FP(0x16,0x7C0), ALL, ARG_FP },
+  { "subs/suid",	FP(0x16,0x7C1), ALL, ARG_FP },
+  { "muls/suid",	FP(0x16,0x7C2), ALL, ARG_FP },
+  { "divs/suid",	FP(0x16,0x7C3), ALL, ARG_FP },
+  { "addt/suid",	FP(0x16,0x7E0), ALL, ARG_FP },
+  { "subt/suid",	FP(0x16,0x7E1), ALL, ARG_FP },
+  { "mult/suid",	FP(0x16,0x7E2), ALL, ARG_FP },
+  { "divt/suid",	FP(0x16,0x7E3), ALL, ARG_FP },
+  { "cvtts/suid",	FP(0x16,0x7EC), ALL, ARG_FPZ1 },
+  { "cvttq/suid",	FP(0x16,0x7EF), ALL, ARG_FPZ1 },
+  { "cvtqs/suid",	FP(0x16,0x7FC), ALL, ARG_FPZ1 },
+  { "cvtqt/suid",	FP(0x16,0x7FE), ALL, ARG_FPZ1 },
+
+  { "cvtlq",		FP(0x17,0x010), ALL, ARG_FPZ1 },
+  { "fnop",		FP(0x17,0x020), ALL, { ZA, ZB, ZC } },	/* pseudo */
+  { "fclr",		FP(0x17,0x020), ALL, { ZA, ZB, FC } },	/* pseudo */
+  { "fabs",		FP(0x17,0x020), ALL, ARG_FPZ1 },	/* pseudo */
+  { "fmov",		FP(0x17,0x020), ALL, { FA, RBA, FC } }, /* pseudo */
+  { "cpys",		FP(0x17,0x020), ALL, ARG_FP },
+  { "fneg",		FP(0x17,0x021), ALL, { FA, RBA, FC } }, /* pseudo */
+  { "cpysn",		FP(0x17,0x021), ALL, ARG_FP },
+  { "cpyse",		FP(0x17,0x022), ALL, ARG_FP },
+  { "mt_fpcr",		FP(0x17,0x024), ALL, { FA, RBA, RCA } },
+  { "mf_fpcr",		FP(0x17,0x025), ALL, { FA, RBA, RCA } },
+  { "fcmoveq",		FP(0x17,0x02A), ALL, ARG_FP },
+  { "fcmovne",		FP(0x17,0x02B), ALL, ARG_FP },
+  { "fcmovlt",		FP(0x17,0x02C), ALL, ARG_FP },
+  { "fcmovge",		FP(0x17,0x02D), ALL, ARG_FP },
+  { "fcmovle",		FP(0x17,0x02E), ALL, ARG_FP },
+  { "fcmovgt",		FP(0x17,0x02F), ALL, ARG_FP },
+  { "cvtql",		FP(0x17,0x030), ALL, ARG_FPZ1 },
+  { "cvtql/v",		FP(0x17,0x130), ALL, ARG_FPZ1 },
+  { "cvtql/sv",		FP(0x17,0x530), ALL, ARG_FPZ1 },
+
+  { "trapb",		MFC(0x18,0x0000), ALL, ARG_NONE },
+  { "draint",		MFC(0x18,0x0000), ALL, ARG_NONE },	/* alias */
+  { "excb",		MFC(0x18,0x0400), ALL, ARG_NONE },
+  { "mb",		MFC(0x18,0x4000), ALL, ARG_NONE },
+  { "wmb",		MFC(0x18,0x4400), ALL, ARG_NONE },
+  { "fetch",		MFC(0x18,0x8000), ALL, { MDISP, RB } },
+  { "fetch_m",		MFC(0x18,0xA000), ALL, { MDISP, RB } },
+  { "rpcc",		MFC(0x18,0xC000), ALL, { RA } },
+  { "rc",		MFC(0x18,0xE000), ALL, { RA } },
+  { "rs",		MFC(0x18,0xF000), ALL, { RA } },
+
+  { "hw_mfpr",		OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
+  { "hw_mfpr",		OP(0x19), OP_MASK, EV5x, { RA, RBA, EV5HWINDEX } },
+  { "hw_mfpr/i",	OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
+  { "hw_mfpr/a",	OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
+  { "hw_mfpr/ai",	OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
+  { "hw_mfpr/p",	OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
+  { "hw_mfpr/pi",	OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
+  { "hw_mfpr/pa",	OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
+  { "hw_mfpr/pai",	OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
+  { "pal19",		PCD(0x19), ALL, ARG_PCD },
+
+  { "jmp",		MBR(0x1A,0), ALL, { RA, CPRB, JMPHINT } },
+  { "jsr",		MBR(0x1A,1), ALL, { RA, CPRB, JMPHINT } },
+  { "ret",		MBR(0x1A,2), ALL, { RA, CPRB, RETHINT } },
+  { "jcr",		MBR(0x1A,3), ALL, { RA, CPRB, RETHINT } }, /* alias */
+  { "jsr_coroutine",	MBR(0x1A,3), ALL, { RA, CPRB, RETHINT } },
+
+  { "hw_ldl",		EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
+  { "hw_ldl",		EV5HWMEM(0x1B,0x00), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/a",		EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
+  { "hw_ldl/a",		EV5HWMEM(0x1B,0x10), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/al",	EV5HWMEM(0x1B,0x11), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/ar",	EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
+  { "hw_ldl/av",	EV5HWMEM(0x1B,0x12), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/avl",	EV5HWMEM(0x1B,0x13), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/aw",	EV5HWMEM(0x1B,0x18), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/awl",	EV5HWMEM(0x1B,0x19), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/awv",	EV5HWMEM(0x1B,0x1a), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/awvl",	EV5HWMEM(0x1B,0x1b), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/l",		EV5HWMEM(0x1B,0x01), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/p",		EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
+  { "hw_ldl/p",		EV5HWMEM(0x1B,0x20), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pa",	EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
+  { "hw_ldl/pa",	EV5HWMEM(0x1B,0x30), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pal",	EV5HWMEM(0x1B,0x31), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/par",	EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
+  { "hw_ldl/pav",	EV5HWMEM(0x1B,0x32), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pavl",	EV5HWMEM(0x1B,0x33), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/paw",	EV5HWMEM(0x1B,0x38), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pawl",	EV5HWMEM(0x1B,0x39), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pawv",	EV5HWMEM(0x1B,0x3a), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pawvl",	EV5HWMEM(0x1B,0x3b), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pl",	EV5HWMEM(0x1B,0x21), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pr",	EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
+  { "hw_ldl/pv",	EV5HWMEM(0x1B,0x22), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pvl",	EV5HWMEM(0x1B,0x23), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pw",	EV5HWMEM(0x1B,0x28), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pwl",	EV5HWMEM(0x1B,0x29), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pwv",	EV5HWMEM(0x1B,0x2a), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/pwvl",	EV5HWMEM(0x1B,0x2b), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/r",		EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
+  { "hw_ldl/v",		EV5HWMEM(0x1B,0x02), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/vl",	EV5HWMEM(0x1B,0x03), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/w",		EV5HWMEM(0x1B,0x08), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/wl",	EV5HWMEM(0x1B,0x09), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/wv",	EV5HWMEM(0x1B,0x0a), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl/wvl",	EV5HWMEM(0x1B,0x0b), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l",		EV5HWMEM(0x1B,0x01), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/a",	EV5HWMEM(0x1B,0x11), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/av",	EV5HWMEM(0x1B,0x13), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/aw",	EV5HWMEM(0x1B,0x19), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/awv",	EV5HWMEM(0x1B,0x1b), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/p",	EV5HWMEM(0x1B,0x21), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/pa",	EV5HWMEM(0x1B,0x31), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/pav",	EV5HWMEM(0x1B,0x33), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/paw",	EV5HWMEM(0x1B,0x39), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/pawv",	EV5HWMEM(0x1B,0x3b), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/pv",	EV5HWMEM(0x1B,0x23), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/pw",	EV5HWMEM(0x1B,0x29), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/pwv",	EV5HWMEM(0x1B,0x2b), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/v",	EV5HWMEM(0x1B,0x03), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/w",	EV5HWMEM(0x1B,0x09), EV5x, ARG_EV5HWMEM },
+  { "hw_ldl_l/wv",	EV5HWMEM(0x1B,0x0b), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq",		EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
+  { "hw_ldq",		EV5HWMEM(0x1B,0x04), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/a",		EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
+  { "hw_ldq/a",		EV5HWMEM(0x1B,0x14), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/al",	EV5HWMEM(0x1B,0x15), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/ar",	EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
+  { "hw_ldq/av",	EV5HWMEM(0x1B,0x16), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/avl",	EV5HWMEM(0x1B,0x17), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/aw",	EV5HWMEM(0x1B,0x1c), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/awl",	EV5HWMEM(0x1B,0x1d), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/awv",	EV5HWMEM(0x1B,0x1e), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/awvl",	EV5HWMEM(0x1B,0x1f), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/l",		EV5HWMEM(0x1B,0x05), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/p",		EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
+  { "hw_ldq/p",		EV5HWMEM(0x1B,0x24), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pa",	EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
+  { "hw_ldq/pa",	EV5HWMEM(0x1B,0x34), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pal",	EV5HWMEM(0x1B,0x35), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/par",	EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
+  { "hw_ldq/pav",	EV5HWMEM(0x1B,0x36), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pavl",	EV5HWMEM(0x1B,0x37), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/paw",	EV5HWMEM(0x1B,0x3c), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pawl",	EV5HWMEM(0x1B,0x3d), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pawv",	EV5HWMEM(0x1B,0x3e), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pawvl",	EV5HWMEM(0x1B,0x3f), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pl",	EV5HWMEM(0x1B,0x25), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pr",	EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
+  { "hw_ldq/pv",	EV5HWMEM(0x1B,0x26), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pvl",	EV5HWMEM(0x1B,0x27), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pw",	EV5HWMEM(0x1B,0x2c), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pwl",	EV5HWMEM(0x1B,0x2d), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pwv",	EV5HWMEM(0x1B,0x2e), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/pwvl",	EV5HWMEM(0x1B,0x2f), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/r",		EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
+  { "hw_ldq/v",		EV5HWMEM(0x1B,0x06), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/vl",	EV5HWMEM(0x1B,0x07), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/w",		EV5HWMEM(0x1B,0x0c), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/wl",	EV5HWMEM(0x1B,0x0d), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/wv",	EV5HWMEM(0x1B,0x0e), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq/wvl",	EV5HWMEM(0x1B,0x0f), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l",		EV5HWMEM(0x1B,0x05), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/a",	EV5HWMEM(0x1B,0x15), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/av",	EV5HWMEM(0x1B,0x17), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/aw",	EV5HWMEM(0x1B,0x1d), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/awv",	EV5HWMEM(0x1B,0x1f), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/p",	EV5HWMEM(0x1B,0x25), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/pa",	EV5HWMEM(0x1B,0x35), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/pav",	EV5HWMEM(0x1B,0x37), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/paw",	EV5HWMEM(0x1B,0x3d), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/pawv",	EV5HWMEM(0x1B,0x3f), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/pv",	EV5HWMEM(0x1B,0x27), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/pw",	EV5HWMEM(0x1B,0x2d), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/pwv",	EV5HWMEM(0x1B,0x2f), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/v",	EV5HWMEM(0x1B,0x07), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/w",	EV5HWMEM(0x1B,0x0d), EV5x, ARG_EV5HWMEM },
+  { "hw_ldq_l/wv",	EV5HWMEM(0x1B,0x0f), EV5x, ARG_EV5HWMEM },
+  { "hw_ld",		EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
+  { "hw_ld",		EV5HWMEM(0x1B,0x00), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/a",		EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
+  { "hw_ld/a",		EV5HWMEM(0x1B,0x10), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/al",		EV5HWMEM(0x1B,0x11), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/aq",		EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
+  { "hw_ld/aq",		EV5HWMEM(0x1B,0x14), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/aql",	EV5HWMEM(0x1B,0x15), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/aqv",	EV5HWMEM(0x1B,0x16), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/aqvl",	EV5HWMEM(0x1B,0x17), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/ar",		EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
+  { "hw_ld/arq",	EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
+  { "hw_ld/av",		EV5HWMEM(0x1B,0x12), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/avl",	EV5HWMEM(0x1B,0x13), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/aw",		EV5HWMEM(0x1B,0x18), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/awl",	EV5HWMEM(0x1B,0x19), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/awq",	EV5HWMEM(0x1B,0x1c), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/awql",	EV5HWMEM(0x1B,0x1d), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/awqv",	EV5HWMEM(0x1B,0x1e), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/awqvl",	EV5HWMEM(0x1B,0x1f), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/awv",	EV5HWMEM(0x1B,0x1a), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/awvl",	EV5HWMEM(0x1B,0x1b), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/l",		EV5HWMEM(0x1B,0x01), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/p",		EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
+  { "hw_ld/p",		EV5HWMEM(0x1B,0x20), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pa",		EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
+  { "hw_ld/pa",		EV5HWMEM(0x1B,0x30), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pal",	EV5HWMEM(0x1B,0x31), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/paq",	EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
+  { "hw_ld/paq",	EV5HWMEM(0x1B,0x34), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/paql",	EV5HWMEM(0x1B,0x35), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/paqv",	EV5HWMEM(0x1B,0x36), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/paqvl",	EV5HWMEM(0x1B,0x37), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/par",	EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
+  { "hw_ld/parq",	EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
+  { "hw_ld/pav",	EV5HWMEM(0x1B,0x32), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pavl",	EV5HWMEM(0x1B,0x33), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/paw",	EV5HWMEM(0x1B,0x38), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pawl",	EV5HWMEM(0x1B,0x39), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pawq",	EV5HWMEM(0x1B,0x3c), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pawql",	EV5HWMEM(0x1B,0x3d), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pawqv",	EV5HWMEM(0x1B,0x3e), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pawqvl",	EV5HWMEM(0x1B,0x3f), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pawv",	EV5HWMEM(0x1B,0x3a), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pawvl",	EV5HWMEM(0x1B,0x3b), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pl",		EV5HWMEM(0x1B,0x21), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pq",		EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
+  { "hw_ld/pq",		EV5HWMEM(0x1B,0x24), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pql",	EV5HWMEM(0x1B,0x25), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pqv",	EV5HWMEM(0x1B,0x26), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pqvl",	EV5HWMEM(0x1B,0x27), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pr",		EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
+  { "hw_ld/prq",	EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
+  { "hw_ld/pv",		EV5HWMEM(0x1B,0x22), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pvl",	EV5HWMEM(0x1B,0x23), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pw",		EV5HWMEM(0x1B,0x28), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pwl",	EV5HWMEM(0x1B,0x29), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pwq",	EV5HWMEM(0x1B,0x2c), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pwql",	EV5HWMEM(0x1B,0x2d), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pwqv",	EV5HWMEM(0x1B,0x2e), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pwqvl",	EV5HWMEM(0x1B,0x2f), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pwv",	EV5HWMEM(0x1B,0x2a), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/pwvl",	EV5HWMEM(0x1B,0x2b), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/q",		EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
+  { "hw_ld/q",		EV5HWMEM(0x1B,0x04), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/ql",		EV5HWMEM(0x1B,0x05), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/qv",		EV5HWMEM(0x1B,0x06), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/qvl",	EV5HWMEM(0x1B,0x07), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/r",		EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
+  { "hw_ld/rq",		EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
+  { "hw_ld/v",		EV5HWMEM(0x1B,0x02), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/vl",		EV5HWMEM(0x1B,0x03), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/w",		EV5HWMEM(0x1B,0x08), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/wl",		EV5HWMEM(0x1B,0x09), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/wq",		EV5HWMEM(0x1B,0x0c), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/wql",	EV5HWMEM(0x1B,0x0d), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/wqv",	EV5HWMEM(0x1B,0x0e), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/wqvl",	EV5HWMEM(0x1B,0x0f), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/wv",		EV5HWMEM(0x1B,0x0a), EV5x, ARG_EV5HWMEM },
+  { "hw_ld/wvl",	EV5HWMEM(0x1B,0x0b), EV5x, ARG_EV5HWMEM },
+  { "pal1b",		PCD(0x1B), ALL, ARG_PCD },
+
+  { "hw_mtpr",		OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
+  { "hw_mtpr",		OP(0x1D), OP_MASK, EV5x, { RA, RBA, EV5HWINDEX } },
+  { "hw_mtpr/i", 	OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
+  { "hw_mtpr/a", 	OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
+  { "hw_mtpr/ai",	OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
+  { "hw_mtpr/p", 	OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
+  { "hw_mtpr/pi",	OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
+  { "hw_mtpr/pa",	OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
+  { "hw_mtpr/pai",	OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
+  { "pal1d",		PCD(0x1D), ALL, ARG_PCD },
+
+  { "hw_rei",		SPCD(0x1E,0x3FF8000), EV4|EV5x, ARG_NONE },
+  { "hw_rei_stall",	SPCD(0x1E,0x3FFC000), EV5x, ARG_NONE },
+  { "pal1e",		PCD(0x1E), ALL, ARG_PCD },
+
+  { "hw_stl",		EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
+  { "hw_stl",		EV5HWMEM(0x1F,0x00), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/a",		EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
+  { "hw_stl/a",		EV5HWMEM(0x1F,0x10), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/ac",	EV5HWMEM(0x1F,0x11), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/ar",	EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
+  { "hw_stl/av",	EV5HWMEM(0x1F,0x12), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/avc",	EV5HWMEM(0x1F,0x13), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/c",		EV5HWMEM(0x1F,0x01), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/p",		EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
+  { "hw_stl/p",		EV5HWMEM(0x1F,0x20), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/pa",	EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
+  { "hw_stl/pa",	EV5HWMEM(0x1F,0x30), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/pac",	EV5HWMEM(0x1F,0x31), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/pav",	EV5HWMEM(0x1F,0x32), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/pavc",	EV5HWMEM(0x1F,0x33), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/pc",	EV5HWMEM(0x1F,0x21), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/pr",	EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
+  { "hw_stl/pv",	EV5HWMEM(0x1F,0x22), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/pvc",	EV5HWMEM(0x1F,0x23), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/r",		EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
+  { "hw_stl/v",		EV5HWMEM(0x1F,0x02), EV5x, ARG_EV5HWMEM },
+  { "hw_stl/vc",	EV5HWMEM(0x1F,0x03), EV5x, ARG_EV5HWMEM },
+  { "hw_stl_c",		EV5HWMEM(0x1F,0x01), EV5x, ARG_EV5HWMEM },
+  { "hw_stl_c/a",	EV5HWMEM(0x1F,0x11), EV5x, ARG_EV5HWMEM },
+  { "hw_stl_c/av",	EV5HWMEM(0x1F,0x13), EV5x, ARG_EV5HWMEM },
+  { "hw_stl_c/p",	EV5HWMEM(0x1F,0x21), EV5x, ARG_EV5HWMEM },
+  { "hw_stl_c/pa",	EV5HWMEM(0x1F,0x31), EV5x, ARG_EV5HWMEM },
+  { "hw_stl_c/pav",	EV5HWMEM(0x1F,0x33), EV5x, ARG_EV5HWMEM },
+  { "hw_stl_c/pv",	EV5HWMEM(0x1F,0x23), EV5x, ARG_EV5HWMEM },
+  { "hw_stl_c/v",	EV5HWMEM(0x1F,0x03), EV5x, ARG_EV5HWMEM },
+  { "hw_stq",		EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
+  { "hw_stq",		EV5HWMEM(0x1F,0x04), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/a",		EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
+  { "hw_stq/a",		EV5HWMEM(0x1F,0x14), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/ac",	EV5HWMEM(0x1F,0x15), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/ar",	EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
+  { "hw_stq/av",	EV5HWMEM(0x1F,0x16), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/avc",	EV5HWMEM(0x1F,0x17), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/c",		EV5HWMEM(0x1F,0x05), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/p",		EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
+  { "hw_stq/p",		EV5HWMEM(0x1F,0x24), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/pa",	EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
+  { "hw_stq/pa",	EV5HWMEM(0x1F,0x34), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/pac",	EV5HWMEM(0x1F,0x35), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/par",	EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
+  { "hw_stq/par",	EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
+  { "hw_stq/pav",	EV5HWMEM(0x1F,0x36), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/pavc",	EV5HWMEM(0x1F,0x37), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/pc",	EV5HWMEM(0x1F,0x25), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/pr",	EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
+  { "hw_stq/pv",	EV5HWMEM(0x1F,0x26), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/pvc",	EV5HWMEM(0x1F,0x27), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/r",		EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
+  { "hw_stq/v",		EV5HWMEM(0x1F,0x06), EV5x, ARG_EV5HWMEM },
+  { "hw_stq/vc",	EV5HWMEM(0x1F,0x07), EV5x, ARG_EV5HWMEM },
+  { "hw_stq_c",		EV5HWMEM(0x1F,0x05), EV5x, ARG_EV5HWMEM },
+  { "hw_stq_c/a",	EV5HWMEM(0x1F,0x15), EV5x, ARG_EV5HWMEM },
+  { "hw_stq_c/av",	EV5HWMEM(0x1F,0x17), EV5x, ARG_EV5HWMEM },
+  { "hw_stq_c/p",	EV5HWMEM(0x1F,0x25), EV5x, ARG_EV5HWMEM },
+  { "hw_stq_c/pa",	EV5HWMEM(0x1F,0x35), EV5x, ARG_EV5HWMEM },
+  { "hw_stq_c/pav",	EV5HWMEM(0x1F,0x37), EV5x, ARG_EV5HWMEM },
+  { "hw_stq_c/pv",	EV5HWMEM(0x1F,0x27), EV5x, ARG_EV5HWMEM },
+  { "hw_stq_c/v",	EV5HWMEM(0x1F,0x07), EV5x, ARG_EV5HWMEM },
+  { "hw_st",		EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
+  { "hw_st",		EV5HWMEM(0x1F,0x00), EV5x, ARG_EV5HWMEM },
+  { "hw_st/a",		EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
+  { "hw_st/a",		EV5HWMEM(0x1F,0x10), EV5x, ARG_EV5HWMEM },
+  { "hw_st/ac",		EV5HWMEM(0x1F,0x11), EV5x, ARG_EV5HWMEM },
+  { "hw_st/aq",		EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
+  { "hw_st/aq",		EV5HWMEM(0x1F,0x14), EV5x, ARG_EV5HWMEM },
+  { "hw_st/aqc",	EV5HWMEM(0x1F,0x15), EV5x, ARG_EV5HWMEM },
+  { "hw_st/aqv",	EV5HWMEM(0x1F,0x16), EV5x, ARG_EV5HWMEM },
+  { "hw_st/aqvc",	EV5HWMEM(0x1F,0x17), EV5x, ARG_EV5HWMEM },
+  { "hw_st/ar",		EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
+  { "hw_st/arq",	EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
+  { "hw_st/av",		EV5HWMEM(0x1F,0x12), EV5x, ARG_EV5HWMEM },
+  { "hw_st/avc",	EV5HWMEM(0x1F,0x13), EV5x, ARG_EV5HWMEM },
+  { "hw_st/c",		EV5HWMEM(0x1F,0x01), EV5x, ARG_EV5HWMEM },
+  { "hw_st/p",		EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
+  { "hw_st/p",		EV5HWMEM(0x1F,0x20), EV5x, ARG_EV5HWMEM },
+  { "hw_st/pa",		EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
+  { "hw_st/pa",		EV5HWMEM(0x1F,0x30), EV5x, ARG_EV5HWMEM },
+  { "hw_st/pac",	EV5HWMEM(0x1F,0x31), EV5x, ARG_EV5HWMEM },
+  { "hw_st/paq",	EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
+  { "hw_st/paq",	EV5HWMEM(0x1F,0x34), EV5x, ARG_EV5HWMEM },
+  { "hw_st/paqc",	EV5HWMEM(0x1F,0x35), EV5x, ARG_EV5HWMEM },
+  { "hw_st/paqv",	EV5HWMEM(0x1F,0x36), EV5x, ARG_EV5HWMEM },
+  { "hw_st/paqvc",	EV5HWMEM(0x1F,0x37), EV5x, ARG_EV5HWMEM },
+  { "hw_st/par",	EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
+  { "hw_st/parq",	EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
+  { "hw_st/pav",	EV5HWMEM(0x1F,0x32), EV5x, ARG_EV5HWMEM },
+  { "hw_st/pavc",	EV5HWMEM(0x1F,0x33), EV5x, ARG_EV5HWMEM },
+  { "hw_st/pc",		EV5HWMEM(0x1F,0x21), EV5x, ARG_EV5HWMEM },
+  { "hw_st/pq",		EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
+  { "hw_st/pq",		EV5HWMEM(0x1F,0x24), EV5x, ARG_EV5HWMEM },
+  { "hw_st/pqc",	EV5HWMEM(0x1F,0x25), EV5x, ARG_EV5HWMEM },
+  { "hw_st/pqv",	EV5HWMEM(0x1F,0x26), EV5x, ARG_EV5HWMEM },
+  { "hw_st/pqvc",	EV5HWMEM(0x1F,0x27), EV5x, ARG_EV5HWMEM },
+  { "hw_st/pr",		EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
+  { "hw_st/prq",	EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
+  { "hw_st/pv",		EV5HWMEM(0x1F,0x22), EV5x, ARG_EV5HWMEM },
+  { "hw_st/pvc",	EV5HWMEM(0x1F,0x23), EV5x, ARG_EV5HWMEM },
+  { "hw_st/q",		EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
+  { "hw_st/q",		EV5HWMEM(0x1F,0x04), EV5x, ARG_EV5HWMEM },
+  { "hw_st/qc",		EV5HWMEM(0x1F,0x05), EV5x, ARG_EV5HWMEM },
+  { "hw_st/qv",		EV5HWMEM(0x1F,0x06), EV5x, ARG_EV5HWMEM },
+  { "hw_st/qvc",	EV5HWMEM(0x1F,0x07), EV5x, ARG_EV5HWMEM },
+  { "hw_st/r",		EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
+  { "hw_st/v",		EV5HWMEM(0x1F,0x02), EV5x, ARG_EV5HWMEM },
+  { "hw_st/vc",		EV5HWMEM(0x1F,0x03), EV5x, ARG_EV5HWMEM },
+  { "pal1f",		PCD(0x1F), ALL, ARG_PCD },
+
+  { "ldf",		MEM(0x20), ALL, ARG_FMEM },
+  { "ldg",		MEM(0x21), ALL, ARG_FMEM },
+  { "lds",		MEM(0x22), ALL, ARG_FMEM },
+  { "ldt",		MEM(0x23), ALL, ARG_FMEM },
+  { "stf",		MEM(0x24), ALL, ARG_FMEM },
+  { "stg",		MEM(0x25), ALL, ARG_FMEM },
+  { "sts",		MEM(0x26), ALL, ARG_FMEM },
+  { "stt",		MEM(0x27), ALL, ARG_FMEM },
+
+  { "ldl",		MEM(0x28), ALL, ARG_MEM },
+  { "ldq",		MEM(0x29), ALL, ARG_MEM },
+  { "ldl_l",		MEM(0x2A), ALL, ARG_MEM },
+  { "ldq_l",		MEM(0x2B), ALL, ARG_MEM },
+  { "stl",		MEM(0x2C), ALL, ARG_MEM },
+  { "stq",		MEM(0x2D), ALL, ARG_MEM },
+  { "stl_c",		MEM(0x2E), ALL, ARG_MEM },
+  { "stq_c",		MEM(0x2F), ALL, ARG_MEM },
+
+  { "br",		BRA(0x30), ALL, { ZA, BDISP } },	/* pseudo */
+  { "br",		BRA(0x30), ALL, ARG_BRA },
+  { "fbeq",		BRA(0x31), ALL, ARG_FBRA },
+  { "fblt",		BRA(0x32), ALL, ARG_FBRA },
+  { "fble",		BRA(0x33), ALL, ARG_FBRA },
+  { "bsr",		BRA(0x34), ALL, ARG_BRA },
+  { "fbne",		BRA(0x35), ALL, ARG_FBRA },
+  { "fbge",		BRA(0x36), ALL, ARG_FBRA },
+  { "fbgt",		BRA(0x37), ALL, ARG_FBRA },
+  { "blbc",		BRA(0x38), ALL, ARG_BRA },
+  { "beq",		BRA(0x39), ALL, ARG_BRA },
+  { "blt",		BRA(0x3A), ALL, ARG_BRA },
+  { "ble",		BRA(0x3B), ALL, ARG_BRA },
+  { "blbs",		BRA(0x3C), ALL, ARG_BRA },
+  { "bne",		BRA(0x3D), ALL, ARG_BRA },
+  { "bge",		BRA(0x3E), ALL, ARG_BRA },
+  { "bgt",		BRA(0x3F), ALL, ARG_BRA },
+};
+
+const int alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);
diff --git a/gnu/usr.bin/binutils/opcodes/makefile.vms b/gnu/usr.bin/binutils/opcodes/makefile.vms
new file mode 100644
index 00000000000..160319d5ce8
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/makefile.vms
@@ -0,0 +1,31 @@
+#
+# Makefile for libopcodes under openVMS/AXP
+#
+# For use with gnu-make for vms
+#
+# Created by Klaus Kaempf, kkaempf@progis.de
+#
+#
+CC=gcc
+
+OBJS=alpha-dis.obj,alpha-opc.obj,dis-buf.obj,disassemble.obj
+
+ifeq ($(CC),gcc)
+DEFS=/define=(OBJ_EVAX)
+CFLAGS=/include=([],[-.include],[-.bfd])$(DEFS)
+else
+DEFS=/define=(OBJ_EVAX,"const=")
+CFLAGS=/noopt/debug/include=([],[-.include],[-.bfd])$(DEFS)
+endif
+
+libopcodes.olb: sysdep.h $(OBJS)
+	purge
+	lib/create libopcodes *.obj
+
+disassemble.obj: disassemble.c
+	$(CC)$(CFLAGS)/define=("ARCH_alpha") $<
+
+alpha-dis.obj: alpha-dis.c
+
+sysdep.h: [-.bfd.hosts]alphavms.h
+	$(CP) $< $@