regen

1 files changed, 61 insertions, 61 deletions

diff --git a/sys/dev/mii/miidevs.h b/sys/dev/mii/miidevs.h
index 0cc51f1b82a..217e5f6d5c6 100644
--- a/sys/dev/mii/miidevs.h
+++ b/sys/dev/mii/miidevs.h
@@ -1,10 +1,10 @@
-/*	$OpenBSD: miidevs.h,v 1.105 2008/10/24 23:04:30 brad Exp $	*/
+/*	$OpenBSD: miidevs.h,v 1.106 2008/10/24 23:50:59 brad Exp $	*/
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *	OpenBSD: miidevs,v 1.102 2008/10/24 23:01:50 brad Exp 
+ *	OpenBSD: miidevs,v 1.103 2008/10/24 23:50:42 brad Exp 
  */
 /* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */
 
@@ -41,47 +41,47 @@
 /*
  * List of known MII OUIs
  */
-#define	MII_OUI_AMD	0x00001a	/* Advanced Micro Devices */
-#define	MII_OUI_REALTEK	0x000020	/* Realtek Semiconductor */
+#define	MII_OUI_AMD	0x00001a	/* AMD */
+#define	MII_OUI_REALTEK	0x000020	/* Realtek */
 #define	MII_OUI_VITESSE	0x0001c1	/* Vitesse */
-#define	MII_OUI_CICADA	0x0003f1	/* Cicada Semiconductor */
-#define	MII_OUI_CENIX	0x000749	/* CENiX Inc. */
-#define	MII_OUI_BROADCOM2	0x000af7	/* Broadcom Corporation */
-#define	MII_OUI_ASIX	0x000ec6	/* ASIX Electronics */
-#define	MII_OUI_BROADCOM	0x001018	/* Broadcom Corporation */
+#define	MII_OUI_CICADA	0x0003f1	/* Cicada */
+#define	MII_OUI_CENIX	0x000749	/* CENiX */
+#define	MII_OUI_BROADCOM2	0x000af7	/* Broadcom */
+#define	MII_OUI_ASIX	0x000ec6	/* ASIX */
+#define	MII_OUI_BROADCOM	0x001018	/* Broadcom */
 #define	MII_OUI_3COM	0x00105a	/* 3com */
-#define	MII_OUI_ALTIMA	0x0010a9	/* Altima Communications */
-#define	MII_OUI_ENABLESEMI	0x0010dd	/* Enable Semiconductor */
-#define	MII_OUI_ATHEROS	0x001374	/* Atheros Communications */
-#define	MII_OUI_JMICRON	0x001b8c	/* JMicron Technologies */
+#define	MII_OUI_ALTIMA	0x0010a9	/* Altima */
+#define	MII_OUI_ENABLESEMI	0x0010dd	/* Enable Semi. */
+#define	MII_OUI_ATHEROS	0x001374	/* Atheros */
+#define	MII_OUI_JMICRON	0x001b8c	/* JMicron */
 #define	MII_OUI_LEVEL1	0x00207b	/* Level 1 */
-#define	MII_OUI_VIA	0x004063	/* VIA Networking Technologies */
-#define	MII_OUI_MARVELL	0x005043	/* Marvell Semiconductor */
-#define	MII_OUI_LUCENT	0x00601d	/* Lucent Technologies */
-#define	MII_OUI_QUALSEMI	0x006051	/* Quality Semiconductor */
-#define	MII_OUI_DAVICOM	0x00606e	/* Davicom Semiconductor */
+#define	MII_OUI_VIA	0x004063	/* VIA Networking */
+#define	MII_OUI_MARVELL	0x005043	/* Marvell */
+#define	MII_OUI_LUCENT	0x00601d	/* Lucent */
+#define	MII_OUI_QUALITYSEMI	0x006051	/* Quality Semi. */
+#define	MII_OUI_DAVICOM	0x00606e	/* Davicom */
 #define	MII_OUI_SMSC	0x00800f	/* Standard Microsystems */
-#define	MII_OUI_ICPLUS	0x0090c3	/* IC Plus Corp. */
-#define	MII_OUI_TOPIC	0x0090c3	/* Topic Semiconductor */
+#define	MII_OUI_ICPLUS	0x0090c3	/* IC Plus */
+#define	MII_OUI_TOPICSEMI	0x0090c3	/* Topic Semi. */
 #define	MII_OUI_AGERE	0x00a0bc	/* Agere */
 #define	MII_OUI_ICS	0x00a0be	/* Integrated Circuit Systems */
 #define	MII_OUI_SEEQ	0x00a07d	/* Seeq */
 #define	MII_OUI_INTEL	0x00aa00	/* Intel */
-#define	MII_OUI_TSC	0x00c039	/* TDK Semiconductor */
-#define	MII_OUI_MYSON	0x00c0b4	/* Myson Technology */
+#define	MII_OUI_TDK	0x00c039	/* TDK */
+#define	MII_OUI_MYSON	0x00c0b4	/* Myson */
 #define	MII_OUI_PMCSIERRA	0x00e004	/* PMC-Sierra */
 #define	MII_OUI_SIS	0x00e006	/* Silicon Integrated Systems */
-#define	MII_OUI_REALTEK2	0x00e04c	/* Realtek Semiconductor */
+#define	MII_OUI_REALTEK2	0x00e04c	/* Realtek */
 #define	MII_OUI_JATO	0x00e083	/* Jato Technologies */
-#define	MII_OUI_XAQTI	0x00e0ae	/* XaQti Corp. */
-#define	MII_OUI_PLESSEY	0x046b40	/* Plessey Semiconductor */
-#define	MII_OUI_NATSEMI	0x080017	/* National Semiconductor */
+#define	MII_OUI_XAQTI	0x00e0ae	/* XaQti */
+#define	MII_OUI_PLESSEYSEMI	0x046b40	/* Plessey Semi. */
+#define	MII_OUI_NATSEMI	0x080017	/* National Semi. */
 #define	MII_OUI_TI	0x080028	/* Texas Instruments */
 
 /* in the 79c873, AMD uses another OUI (which matches Davicom!) */
-#define	MII_OUI_xxALTIMA	0x000895	/* Altima Communications */
-#define	MII_OUI_xxAMD	0x00606e	/* Advanced Micro Devices */
-#define	MII_OUI_xxCICADA	0x00c08f	/* Cicada Semiconductor (alt) */
+#define	MII_OUI_xxALTIMA	0x000895	/* Altima */
+#define	MII_OUI_xxAMD	0x00606e	/* AMD */
+#define	MII_OUI_xxCICADA	0x00c08f	/* Cicada (alt) */
 #define	MII_OUI_xxINTEL	0x00f800	/* Intel (alt) */
 
 /* some vendors have the bits swapped within bytes
@@ -89,9 +89,9 @@
 #define	MII_OUI_xxICS	0x00057d	/* Integrated Circuit Systems */
 #define	MII_OUI_xxSEEQ	0x0005be	/* Seeq */
 #define	MII_OUI_xxSIS	0x000760	/* Silicon Integrated Systems */
-#define	MII_OUI_xxBROADCOM	0x000818	/* Broadcom Corporation */
+#define	MII_OUI_xxBROADCOM	0x000818	/* Broadcom */
 #define	MII_OUI_xxTI	0x100014	/* Texas Instruments */
-#define	MII_OUI_xxXAQTI	0x350700	/* XaQti Corp. */
+#define	MII_OUI_xxXAQTI	0x350700	/* XaQti */
 
 /* Level 1 is completely different - from right to left.
 	(Two bits get lost in the third OUI byte.) */
@@ -99,22 +99,22 @@
 #define	MII_OUI_xxLEVEL1	0x1e0400	/* Level 1 */
 
 /* Don't know what's going on here. */
-#define	MII_OUI_xxBROADCOM2	0x0050ef	/* Broadcom Corporation */
-#define	MII_OUI_xxDAVICOM	0x006040	/* Davicom Semiconductor */
+#define	MII_OUI_xxBROADCOM2	0x0050ef	/* Broadcom */
+#define	MII_OUI_xxDAVICOM	0x006040	/* Davicom */
 
 /* This is the OUI of the gigE PHY in the RealTek 8169S/8110S chips */
-#define	MII_OUI_xxREALTEK	0x000732	/* Realtek Semiconductor */
+#define	MII_OUI_xxREALTEK	0x000732	/* Realtek */
 
 /* Contrived vendor for dcphy */
 #define	MII_OUI_xxDEC	0x040440	/* Digital Clone */
 
-#define	MII_OUI_xxMARVELL	0x000ac2	/* Marvell Semiconductor */
+#define	MII_OUI_xxMARVELL	0x000ac2	/* Marvell */
 
 /*
  * List of known models.  Grouped by oui.
  */
 
-/* Advanced Micro Devices PHYs */
+/* AMD PHYs */
 #define	MII_MODEL_xxAMD_79C873	0x0000
 #define	MII_STR_xxAMD_79C873	"Am79C873 10/100 PHY"
 #define	MII_MODEL_AMD_79C875phy	0x0014
@@ -126,13 +126,13 @@
 #define	MII_MODEL_AGERE_ET1011	0x0004
 #define	MII_STR_AGERE_ET1011	"ET1011 10/100/1000baseT PHY"
 
-/* Atheros Communications PHYs */
+/* Atheros PHYs */
 #define	MII_MODEL_ATHEROS_F1	0x0001
 #define	MII_STR_ATHEROS_F1	"F1 10/100/1000 PHY"
 #define	MII_MODEL_ATHEROS_F2	0x0002
 #define	MII_STR_ATHEROS_F2	"F2 10/100 PHY"
 
-/* Altima Communications PHYs */
+/* Altima PHYs */
 #define	MII_MODEL_xxALTIMA_AC_UNKNOWN	0x0001
 #define	MII_STR_xxALTIMA_AC_UNKNOWN	"AC_UNKNOWN 10/100 PHY"
 #define	MII_MODEL_xxALTIMA_AC101L	0x0012
@@ -140,7 +140,7 @@
 #define	MII_MODEL_xxALTIMA_AC101	0x0021
 #define	MII_STR_xxALTIMA_AC101	"AC101 10/100 PHY"
 
-/* Broadcom Corp. PHYs */
+/* Broadcom PHYs */
 #define	MII_MODEL_xxBROADCOM_BCM5400	0x0004
 #define	MII_STR_xxBROADCOM_BCM5400	"BCM5400 1000baseT PHY"
 #define	MII_MODEL_xxBROADCOM_BCM5401	0x0005
@@ -206,7 +206,7 @@
 #define	MII_MODEL_BROADCOM2_BCM5906	0x0004
 #define	MII_STR_BROADCOM2_BCM5906	"BCM5906 10/100baseTX PHY"
 
-/* Cicada Semiconductor PHYs (now owned by Vitesse) */
+/* Cicada PHYs (now owned by Vitesse) */
 #define	MII_MODEL_xxCICADA_CS8201B	0x0021
 #define	MII_STR_xxCICADA_CS8201B	"Cicada CS8201 10/100/1000TX PHY"
 #define	MII_MODEL_CICADA_CS8201	0x0001
@@ -220,7 +220,7 @@
 #define	MII_MODEL_CICADA_CS8201B	0x0021
 #define	MII_STR_CICADA_CS8201B	"Cicada CS8201 10/100/1000TX PHY"
 
-/* Davicom Semiconductor PHYs */
+/* Davicom PHYs */
 #define	MII_MODEL_xxDAVICOM_DM9101	0x0000
 #define	MII_STR_xxDAVICOM_DM9101	"DM9101 10/100 PHY"
 #define	MII_MODEL_DAVICOM_DM9102	0x0004
@@ -232,7 +232,7 @@
 #define	MII_MODEL_xxDEC_xxDC	0x0001
 #define	MII_STR_xxDEC_xxDC	"DC"
 
-/* Enable Semiconductor PHYs (Agere) */
+/* Enable Semi. PHYs (Agere) */
 #define	MII_MODEL_ENABLESEMI_LU3X31FT	0x0001
 #define	MII_STR_ENABLESEMI_LU3X31FT	"Enable LU3X31FT"
 #define	MII_MODEL_ENABLESEMI_LU3X31T2	0x0002
@@ -242,7 +242,7 @@
 #define	MII_MODEL_ENABLESEMI_88E1000	0x0005
 #define	MII_STR_ENABLESEMI_88E1000	"Enable 88E1000"
 
-/* IC Plus Corp. PHYs */
+/* IC Plus PHYs */
 #define	MII_MODEL_ICPLUS_IP100	0x0004
 #define	MII_STR_ICPLUS_IP100	"IP100 10/100 PHY"
 #define	MII_MODEL_ICPLUS_IP101	0x0005
@@ -278,7 +278,7 @@
 #define	MII_MODEL_JATO_BASEX	0x0000
 #define	MII_STR_JATO_BASEX	"Jato 1000baseX PHY"
 
-/* JMicron Technologies PHYs */
+/* JMicron PHYs */
 #define	MII_MODEL_JMICRON_JMP211	0x0021
 #define	MII_STR_JMICRON_JMP211	"JMP211 10/100/1000 PHY"
 #define	MII_MODEL_JMICRON_JMP202	0x0022
@@ -294,7 +294,7 @@
 #define	MII_MODEL_LEVEL1_LXT1000	0x000c
 #define	MII_STR_LEVEL1_LXT1000	"LXT1000 10/100/1000 PHY"
 
-/* Lucent Technologies PHYs */
+/* Lucent PHYs */
 #define	MII_MODEL_LUCENT_LU6612	0x000c
 #define	MII_STR_LUCENT_LU6612	"LU6612 10/100 PHY"
 #define	MII_MODEL_LUCENT_LU3X51FT	0x0033
@@ -302,7 +302,7 @@
 #define	MII_MODEL_LUCENT_LU3X54FT	0x0036
 #define	MII_STR_LUCENT_LU3X54FT	"LU3X54FT 10/100 PHY"
 
-/* Marvell Semiconductor PHYs */
+/* Marvell PHYs */
 #define	MII_MODEL_xxMARVELL_E1000_5	0x0002
 #define	MII_STR_xxMARVELL_E1000_5	"Marvell 88E1000 5 Gigabit PHY"
 #define	MII_MODEL_xxMARVELL_E1000_6	0x0003
@@ -340,11 +340,11 @@
 #define	MII_MODEL_MARVELL_E3016	0x0026
 #define	MII_STR_MARVELL_E3016	"Marvell 88E3016 10/100 PHY"
 
-/* Myson Technology PHYs */
+/* Myson PHYs */
 #define	MII_MODEL_MYSON_MTD972	0x0000
 #define	MII_STR_MYSON_MTD972	"MTD972 10/100 PHY"
 
-/* National Semiconductor PHYs */
+/* National Semi. PHYs */
 #define	MII_MODEL_NATSEMI_DP83840	0x0000
 #define	MII_STR_NATSEMI_DP83840	"DP83840 10/100 PHY"
 #define	MII_MODEL_NATSEMI_DP83843	0x0001
@@ -360,15 +360,15 @@
 #define	MII_MODEL_NATSEMI_DP83865	0x0007
 #define	MII_STR_NATSEMI_DP83865	"DP83865 10/100/1000 PHY"
 
-/* Plessey Semiconductor PHYs */
+/* Plessey Semi. PHYs */
 #define	MII_MODEL_PLESSEY_NWK914	0x0000
 #define	MII_STR_PLESSEY_NWK914	"NWK914 10/100 PHY"
 
-/* Quality Semiconductor PHYs */
-#define	MII_MODEL_QUALSEMI_QS6612	0x0000
-#define	MII_STR_QUALSEMI_QS6612	"QS6612 10/100 PHY"
+/* Quality Semi. PHYs */
+#define	MII_MODEL_QUALITYSEMI_QS6612	0x0000
+#define	MII_STR_QUALITYSEMI_QS6612	"QS6612 10/100 PHY"
 
-/* Realtek Semiconductor PHYs */
+/* Realtek PHYs */
 #define	MII_MODEL_xxREALTEK_RTL8169S	0x0011
 #define	MII_STR_xxREALTEK_RTL8169S	"RTL8169S/8110S PHY"
 #define	MII_MODEL_REALTEK_RTL8201L	0x0020
@@ -398,13 +398,13 @@
 #define	MII_MODEL_xxTI_TNETE2101	0x0003
 #define	MII_STR_xxTI_TNETE2101	"TNETE2101 PHY"
 
-/* TDK Semiconductor PHYs */
-#define	MII_MODEL_TSC_78Q2120	0x0014
-#define	MII_STR_TSC_78Q2120	"78Q2120 10/100 PHY"
-#define	MII_MODEL_TSC_78Q2121	0x0015
-#define	MII_STR_TSC_78Q2121	"78Q2121 100baseTX PHY"
+/* TDK PHYs */
+#define	MII_MODEL_TDK_78Q2120	0x0014
+#define	MII_STR_TDK_78Q2120	"78Q2120 10/100 PHY"
+#define	MII_MODEL_TDK_78Q2121	0x0015
+#define	MII_STR_TDK_78Q2121	"78Q2121 100baseTX PHY"
 
-/* VIA Networking Technologies PHYs */
+/* VIA Networking PHYs */
 #define	MII_MODEL_VIA_VT6103	0x0032
 #define	MII_STR_VIA_VT6103	"VT6103 10/100 PHY"
 #define	MII_MODEL_VIA_VT6103_2	0x0034
@@ -414,6 +414,6 @@
 #define	MII_MODEL_VITESSE_VSC8601	0x0002
 #define	MII_STR_VITESSE_VSC8601	"VSC8601 10/100/1000 PHY"
 
-/* XaQti Corp. PHYs */
+/* XaQti PHYs */
 #define	MII_MODEL_XAQTI_XMACII	0x0000
-#define	MII_STR_XAQTI_XMACII	"XaQti Corp. XMAC II Gigabit PHY"
+#define	MII_STR_XAQTI_XMACII	"XMAC II Gigabit PHY"