diff options
| author | Brad Smith <brad@cvs.openbsd.org> | 2006-02-01 01:09:16 +0000 |
|---|---|---|
| committer | Brad Smith <brad@cvs.openbsd.org> | 2006-02-01 01:09:16 +0000 |
| commit | 5c7ddb8baffb3fdbfb49f5895311f3b13c3b77b2 (patch) | |
| tree | c32e5febfc306ff758188badfd7448a25062cb7f | |
| parent | aab270d10bf4250c74a9b13700c3a6a7a9e0a82f (diff) | |
some more constants.
From NetBSD
| -rw-r--r-- | sys/dev/pci/if_bgereg.h | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/sys/dev/pci/if_bgereg.h b/sys/dev/pci/if_bgereg.h index fc78ab59358..40abc730b44 100644 --- a/sys/dev/pci/if_bgereg.h +++ b/sys/dev/pci/if_bgereg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: if_bgereg.h,v 1.39 2006/01/25 21:01:24 brad Exp $ */ +/* $OpenBSD: if_bgereg.h,v 1.40 2006/02/01 01:09:15 brad Exp $ */ /* * Copyright (c) 2001 Wind River Systems @@ -200,6 +200,15 @@ #define BGE_PCI_ISR_MBX_HI 0xB0 #define BGE_PCI_ISR_MBX_LO 0xB4 +/* XXX: + * Used in PCI-Express code for 575x chips. + * Should be replaced with checking for a PCI config-space + * capability for PCI-Express, and PCI-Express standard + * offsets into that capability block. + */ +#define BGE_PCI_CONF_DEV_CTRL 0xD8 +#define BGE_PCI_CONF_DEV_STUS 0xDA + /* PCI Misc. Host control register */ #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 @@ -305,6 +314,10 @@ #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD_SHIFT 28 +/* PCI DMA Read/Write Control register, alternate usage for PCI-Express */ +#define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128 0x00180000 +#define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256 0x00380000 + #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 @@ -1335,6 +1348,10 @@ #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC +/* Alternate encodings for PCI-Express, from Broadcom-supplied Linux driver */ +#define BGE_RDMA_MODE_FIFO_LONG_BURST ((1<<17) || (1 << 16)) +#define BGE_RDMA_MODE_FIFO_SIZE_128 (1 << 17) + /* Read DMA status register */ #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 @@ -1662,6 +1679,21 @@ #define BGE_MDI_CTL 0x6844 #define BGE_EE_DELAY 0x6848 +/* + * TLP Control Register + * Applicable to BCM5721 and BCM5751 only + */ +#define BGE_TLP_CONTROL_REG 0x7c00 +#define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 + +/* + * PHY Test Control Register + * Applicable to BCM5721 and BCM5751 only + */ +#define BGE_PHY_TEST_CTRL_REG 0x7e2c +#define BGE_PHY_PCIE_SCRAM_MODE 0x0020 +#define BGE_PHY_PCIE_LTASS_MODE 0x0040 + /* Mode control register */ #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 |