dma support for serverwors osb4 and csb5, from netbsd; csapuntz@, deraadt@ ok

1 files changed, 187 insertions, 1 deletions

diff --git a/sys/dev/pci/pciide.c b/sys/dev/pci/pciide.c
index 4fad9cd9d6c..ae7057cb354 100644
--- a/sys/dev/pci/pciide.c
+++ b/sys/dev/pci/pciide.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pciide.c,v 1.87 2002/07/10 11:01:01 markus Exp $	*/
+/*	$OpenBSD: pciide.c,v 1.88 2002/07/29 22:19:39 mickey Exp $	*/
 /*	$NetBSD: pciide.c,v 1.127 2001/08/03 01:31:08 tsutsui Exp $	*/
 
 /*
@@ -242,6 +242,10 @@ int  hpt_pci_intr(void *);
 void acard_chip_map(struct pciide_softc*, struct pci_attach_args*);
 void acard_setup_channel(struct channel_softc*);
 int  acard_pci_intr(void *);
+
+void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
+void serverworks_setup_channel __P((struct channel_softc*));
+int  serverworks_pci_intr __P((void *));
  
 void pciide_channel_dma_setup(struct pciide_channel *);
 int  pciide_dma_table_setup(struct pciide_softc*, int, int);
@@ -481,6 +485,18 @@ const struct pciide_product_desc pciide_acard_products[] =  {
 	}
 };
 
+const struct pciide_product_desc pciide_serverworks_products[] =  {
+	{ PCI_PRODUCT_RCC_OSB4_IDE,
+	  0,
+	  serverworks_chip_map,
+	},
+	{ PCI_PRODUCT_RCC_CSB5_IDE,
+	  0,
+	  serverworks_chip_map,
+	},
+};
+
+
 struct pciide_vendor_desc {
 	u_int32_t ide_vendor;
 	const struct pciide_product_desc *ide_products;
@@ -512,6 +528,8 @@ const struct pciide_vendor_desc pciide_vendors[] = {
 	  sizeof(pciide_triones_products)/sizeof(pciide_triones_products[0]) },
 	{ PCI_VENDOR_ACARD, pciide_acard_products,
 	  sizeof(pciide_acard_products)/sizeof(pciide_acard_products[0]) },
+	{ PCI_VENDOR_RCC, pciide_serverworks_products,
+	  sizeof(pciide_serverworks_products)/sizeof(pciide_serverworks_products[0]) },
 	{ PCI_VENDOR_PROMISE, pciide_promise_products,
 	  sizeof(pciide_promise_products)/sizeof(pciide_promise_products[0]) }
 };
@@ -4338,6 +4356,174 @@ opti_setup_channel(chp)
 	pciide_print_modes(cp);
 }
 
+void
+serverworks_chip_map(sc, pa)
+	struct pciide_softc *sc;
+	struct pci_attach_args *pa;
+{
+	struct pciide_channel *cp;
+	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
+	pcitag_t pcib_tag;
+	int channel;
+	bus_size_t cmdsize, ctlsize;
+
+	if (pciide_chipen(sc, pa) == 0)
+		return;
+
+	printf(": DMA");
+	pciide_mapreg_dma(sc, pa);
+	printf("\n");
+	sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
+	    WDC_CAPABILITY_MODE;
+
+	if (sc->sc_dma_ok) {
+		sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
+		sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
+		sc->sc_wdcdev.irqack = pciide_irqack;
+	}
+	sc->sc_wdcdev.PIO_cap = 4;
+	sc->sc_wdcdev.DMA_cap = 2;
+	switch (sc->sc_pp->ide_product) {
+	case PCI_PRODUCT_RCC_OSB4_IDE:
+		sc->sc_wdcdev.UDMA_cap = 2;
+		break;
+	case PCI_PRODUCT_RCC_CSB5_IDE:
+		if (PCI_REVISION(pa->pa_class) < 0x92)
+			sc->sc_wdcdev.UDMA_cap = 4;
+		else
+			sc->sc_wdcdev.UDMA_cap = 5;
+		break;
+	}
+
+	sc->sc_wdcdev.set_modes = serverworks_setup_channel;
+	sc->sc_wdcdev.channels = sc->wdc_chanarray;
+	sc->sc_wdcdev.nchannels = 2;
+
+	for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
+		cp = &sc->pciide_channels[channel];
+		if (pciide_chansetup(sc, channel, interface) == 0)
+			continue;
+		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
+		    serverworks_pci_intr);
+		if (cp->hw_ok == 0)
+			return;
+		pciide_map_compat_intr(pa, cp, channel, interface);
+		if (cp->hw_ok == 0)
+			return;
+		serverworks_setup_channel(&cp->wdc_channel);
+	}
+
+	pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0);
+	pci_conf_write(pa->pa_pc, pcib_tag, 0x64,
+	    (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000);
+}
+
+void
+serverworks_setup_channel(chp)
+	struct channel_softc *chp;
+{
+	struct ata_drive_datas *drvp;
+	struct pciide_channel *cp = (struct pciide_channel*)chp;
+	struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
+	int channel = chp->channel;
+	int drive, unit;
+	u_int32_t pio_time, dma_time, pio_mode, udma_mode;
+	u_int32_t idedma_ctl;
+	static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20};
+	static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20};
+
+	/* setup DMA if needed */
+	pciide_channel_dma_setup(cp);
+
+	pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40);
+	dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44);
+	pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48);
+	udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54);
+
+	pio_time &= ~(0xffff << (16 * channel));
+	dma_time &= ~(0xffff << (16 * channel));
+	pio_mode &= ~(0xff << (8 * channel + 16));
+	udma_mode &= ~(0xff << (8 * channel + 16));
+	udma_mode &= ~(3 << (2 * channel));
+
+	idedma_ctl = 0;
+
+	/* Per drive settings */
+	for (drive = 0; drive < 2; drive++) {
+		drvp = &chp->ch_drive[drive];
+		/* If no drive, skip */
+		if ((drvp->drive_flags & DRIVE) == 0)
+			continue;
+		unit = drive + 2 * channel;
+		/* add timing values, setup DMA if needed */
+		pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1));
+		pio_mode |= drvp->PIO_mode << (4 * unit + 16);
+		if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) &&
+		    (drvp->drive_flags & DRIVE_UDMA)) {
+			/* use Ultra/DMA, check for 80-pin cable */
+			if (drvp->UDMA_mode > 2 &&
+			    (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0)
+				drvp->UDMA_mode = 2;
+			dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1));
+			udma_mode |= drvp->UDMA_mode << (4 * unit + 16);
+			udma_mode |= 1 << unit;
+			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
+		} else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) &&
+		    (drvp->drive_flags & DRIVE_DMA)) {
+			/* use Multiword DMA */
+			drvp->drive_flags &= ~DRIVE_UDMA;
+			dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1));
+			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
+		} else {
+			/* PIO only */
+			drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA);
+		}
+	}
+
+	pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time);
+	pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time);
+	if (sc->sc_pp->ide_product != PCI_PRODUCT_RCC_OSB4_IDE)
+		pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode);
+	pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode);
+
+	if (idedma_ctl != 0) {
+		/* Add software bits in status register */
+		bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
+		    IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl);
+	}
+	pciide_print_modes(cp);
+}
+
+int
+serverworks_pci_intr(arg)
+	void *arg;
+{
+	struct pciide_softc *sc = arg;
+	struct pciide_channel *cp;
+	struct channel_softc *wdc_cp;
+	int rv = 0;
+	int dmastat, i, crv;
+
+	for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
+		dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
+		    IDEDMA_CTL + IDEDMA_SCH_OFFSET * i);
+		if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) !=
+		    IDEDMA_CTL_INTR)
+			continue;
+		cp = &sc->pciide_channels[i];
+		wdc_cp = &cp->wdc_channel;
+		crv = wdcintr(wdc_cp);
+		if (crv == 0) {
+			printf("%s:%d: bogus intr\n",
+			    sc->sc_wdcdev.sc_dev.dv_xname, i);
+			bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
+			    IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat);
+		} else
+			rv = 1;
+	}
+	return rv;
+}
+
 
 #define	ACARD_IS_850(sc)							\
 	((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U)