Sync up to Intel's latest FreeBSD ixgb driver (5.0.1).

From: Intel's web-site

2 files changed, 8 insertions, 11 deletions

diff --git a/sys/dev/pci/if_ixgb.c b/sys/dev/pci/if_ixgb.c
index c55909cb055..1cd01e88b17 100644
--- a/sys/dev/pci/if_ixgb.c
+++ b/sys/dev/pci/if_ixgb.c
@@ -31,7 +31,7 @@ POSSIBILITY OF SUCH DAMAGE.
 
 ***************************************************************************/
 
-/* $OpenBSD: if_ixgb.c,v 1.11 2006/03/25 22:41:45 djm Exp $ */
+/* $OpenBSD: if_ixgb.c,v 1.12 2006/03/27 17:07:10 brad Exp $ */
 
 #include <dev/pci/if_ixgb.h>
 
@@ -44,7 +44,7 @@ int             ixgb_display_debug_stats = 0;
  *  Driver version
  *********************************************************************/
 
-char ixgb_driver_version[] = "1.0.26";
+char ixgb_driver_version[] = "5.0.1";
 
 /*********************************************************************
  *  PCI Device ID Table
@@ -126,8 +126,8 @@ struct cfdriver ixgb_cd = {
 };
 
 /* some defines for controlling descriptor fetches in h/w */
-#define RXDCTL_PTHRESH_DEFAULT 128	/* chip considers prefech below this */
-#define RXDCTL_HTHRESH_DEFAULT 16	/* chip will only prefetch if tail is
+#define RXDCTL_PTHRESH_DEFAULT 0	/* chip considers prefech below this */
+#define RXDCTL_HTHRESH_DEFAULT 0	/* chip will only prefetch if tail is
 					 * pushed this many descriptors from
 					 * head */
 #define RXDCTL_WTHRESH_DEFAULT 0	/* chip writes back at this many or RXT0 */
diff --git a/sys/dev/pci/if_ixgb.h b/sys/dev/pci/if_ixgb.h
index d8121a2fc7d..c04a8b7fe5d 100644
--- a/sys/dev/pci/if_ixgb.h
+++ b/sys/dev/pci/if_ixgb.h
@@ -31,7 +31,7 @@ POSSIBILITY OF SUCH DAMAGE.
 
 ***************************************************************************/
 
-/* $OpenBSD: if_ixgb.h,v 1.3 2006/02/26 01:27:16 brad Exp $ */
+/* $OpenBSD: if_ixgb.h,v 1.4 2006/03/27 17:07:10 brad Exp $ */
 
 #ifndef _IXGB_H_DEFINED_
 #define _IXGB_H_DEFINED_
@@ -84,7 +84,7 @@ POSSIBILITY OF SUCH DAMAGE.
 /* Tunables */
 
 /*
- * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
+ * TxDescriptors Valid Range: 64-4096 Default Value: 1024 This value is the
  * number of transmit descriptors allocated by the driver. Increasing this
  * value allows the driver to queue more transmits. Each descriptor is 16
  * bytes.
@@ -92,15 +92,13 @@ POSSIBILITY OF SUCH DAMAGE.
 #define IXGB_MAX_TXD                      1024
 
 /*
- * RxDescriptors Valid Range: 64-512 Default Value: 512 This value is the
+ * RxDescriptors Valid Range: 64-4096 Default Value: 1024 This value is the
  * number of receive descriptors allocated by the driver. Increasing this
  * value allows the driver to buffer more incoming packets. Each descriptor
  * is 16 bytes.  A receive buffer is also allocated for each descriptor. The
  * maximum MTU size is 16110.
- * Note: Maximum number of receive descriptors is limited to 512 to avoid a
- * hardware descriptor cache issue under heavy receive traffic. 
  */
-#define IXGB_MAX_RXD                     512
+#define IXGB_MAX_RXD                     1024
 
 /*
  * TxIntDelay Valid Range: 0-65535 (0=off) Default Value: 32 This value
@@ -121,7 +119,6 @@ POSSIBILITY OF SUCH DAMAGE.
  * of TCP traffic. If the system is reporting dropped receives, this value
  * may be set too high, causing the driver to run out of available receive
  * descriptors.
- * 
  */
 #define RDTR 72