Winbond W89C840F ethernet driver

3 files changed, 2713 insertions, 1 deletions

diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci
index c204319aa9d..3ad868d459b 100644
--- a/sys/dev/pci/files.pci
+++ b/sys/dev/pci/files.pci
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.pci,v 1.36 1999/02/19 02:52:25 deraadt Exp $
+#	$OpenBSD: files.pci,v 1.37 1999/03/11 18:20:13 jason Exp $
 #	$NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $
 #
 # Config file and device description for machine-independent PCI code.
@@ -152,3 +152,7 @@ device	aeon: crypto
 attach	aeon at pci
 file	dev/pci/aeon.c			aeon
 
+# Winbond W89C840F ethernet
+device	wb: ether, ifnet
+attach	wb at pci
+file	dev/pci/if_wb.c			wb
diff --git a/sys/dev/pci/if_wb.c b/sys/dev/pci/if_wb.c
new file mode 100644
index 00000000000..6513bc460f6
--- /dev/null
+++ b/sys/dev/pci/if_wb.c
@@ -0,0 +1,2117 @@
+/*	$OpenBSD: if_wb.c,v 1.1 1999/03/11 18:20:13 jason Exp $	*/
+
+/*
+ * Copyright (c) 1997, 1998
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	$FreeBSD: if_wb.c,v 1.7 1999/02/01 21:25:52 wpaul Exp $
+ */
+
+/*
+ * Winbond fast ethernet PCI NIC driver
+ *
+ * Supports various cheap network adapters based on the Winbond W89C840F
+ * fast ethernet controller chip. This includes adapters manufactured by
+ * Winbond itself and some made by Linksys.
+ *
+ * Written by Bill Paul <wpaul@ctr.columbia.edu>
+ * Electrical Engineering Department
+ * Columbia University, New York City
+ */
+
+/*
+ * The Winbond W89C840F chip is a bus master; in some ways it resembles
+ * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
+ * one major difference which is that while the registers do many of
+ * the same things as a tulip adapter, the offsets are different: where
+ * tulip registers are typically spaced 8 bytes apart, the Winbond
+ * registers are spaced 4 bytes apart. The receiver filter is also
+ * programmed differently.
+ * 
+ * Like the tulip, the Winbond chip uses small descriptors containing
+ * a status word, a control word and 32-bit areas that can either be used
+ * to point to two external data blocks, or to point to a single block
+ * and another descriptor in a linked list. Descriptors can be grouped
+ * together in blocks to form fixed length rings or can be chained
+ * together in linked lists. A single packet may be spread out over
+ * several descriptors if necessary.
+ *
+ * For the receive ring, this driver uses a linked list of descriptors,
+ * each pointing to a single mbuf cluster buffer, which us large enough
+ * to hold an entire packet. The link list is looped back to created a
+ * closed ring.
+ *
+ * For transmission, the driver creates a linked list of 'super descriptors'
+ * which each contain several individual descriptors linked toghether.
+ * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
+ * abuse as fragment pointers. This allows us to use a buffer managment
+ * scheme very similar to that used in the ThunderLAN and Etherlink XL
+ * drivers.
+ *
+ * Autonegotiation is performed using the external PHY via the MII bus.
+ * The sample boards I have all use a Davicom PHY.
+ *
+ * Note: the author of the Linux driver for the Winbond chip alludes
+ * to some sort of flaw in the chip's design that seems to mandate some
+ * drastic workaround which signigicantly impairs transmit performance.
+ * I have no idea what he's on about: transmit performance with all
+ * three of my test boards seems fine.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/device.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_types.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <net/if_media.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <vm/vm.h>		/* for vtophys */
+#include <vm/pmap.h>		/* for vtophys */
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#define WB_USEIOSPACE
+
+/* #define WB_BACKGROUND_AUTONEG */
+
+#include <dev/pci/if_wbreg.h>
+
+/*
+ * Various supported PHY vendors/types and their names. Note that
+ * this driver will work with pretty much any MII-compliant PHY,
+ * so failure to positively identify the chip is not a fatal error.
+ */
+
+static struct wb_type wb_phys[] = {
+	{ TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
+	{ TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
+	{ NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
+	{ LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 
+	{ INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
+	{ SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
+	{ 0, 0, "<MII-compliant physical interface>" }
+};
+
+static int wb_probe	__P((struct device *, void *, void *));
+static void wb_attach	__P((struct device *, struct device *, void *));
+
+static int wb_newbuf		__P((struct wb_softc *,
+						struct wb_chain_onefrag *));
+static int wb_encap		__P((struct wb_softc *, struct wb_chain *,
+						struct mbuf *));
+
+static void wb_rxeof		__P((struct wb_softc *));
+static void wb_rxeoc		__P((struct wb_softc *));
+static void wb_txeof		__P((struct wb_softc *));
+static void wb_txeoc		__P((struct wb_softc *));
+static int wb_intr		__P((void *));
+static void wb_start		__P((struct ifnet *));
+static int wb_ioctl		__P((struct ifnet *, u_long, caddr_t));
+static void wb_init		__P((void *));
+static void wb_stop		__P((struct wb_softc *));
+static void wb_watchdog		__P((struct ifnet *));
+static void wb_shutdown		__P((void *));
+static int wb_ifmedia_upd	__P((struct ifnet *));
+static void wb_ifmedia_sts	__P((struct ifnet *, struct ifmediareq *));
+
+static void wb_eeprom_putbyte	__P((struct wb_softc *, int));
+static void wb_eeprom_getword	__P((struct wb_softc *, int, u_int16_t *));
+static void wb_read_eeprom	__P((struct wb_softc *, caddr_t, int,
+							int, int));
+static void wb_mii_sync		__P((struct wb_softc *));
+static void wb_mii_send		__P((struct wb_softc *, u_int32_t, int));
+static int wb_mii_readreg	__P((struct wb_softc *, struct wb_mii_frame *));
+static int wb_mii_writereg	__P((struct wb_softc *, struct wb_mii_frame *));
+static u_int16_t wb_phy_readreg	__P((struct wb_softc *, int));
+static void wb_phy_writereg	__P((struct wb_softc *, int, int));
+
+static void wb_autoneg_xmit	__P((struct wb_softc *));
+static void wb_autoneg_mii	__P((struct wb_softc *, int, int));
+static void wb_setmode_mii	__P((struct wb_softc *, int));
+static void wb_getmode_mii	__P((struct wb_softc *));
+static void wb_setcfg		__P((struct wb_softc *, int));
+static u_int8_t wb_calchash	__P((caddr_t));
+static void wb_setmulti		__P((struct wb_softc *));
+static void wb_reset		__P((struct wb_softc *));
+static int wb_list_rx_init	__P((struct wb_softc *));
+static int wb_list_tx_init	__P((struct wb_softc *));
+
+#define WB_SETBIT(sc, reg, x)				\
+	CSR_WRITE_4(sc, reg,				\
+		CSR_READ_4(sc, reg) | x)
+
+#define WB_CLRBIT(sc, reg, x)				\
+	CSR_WRITE_4(sc, reg,				\
+		CSR_READ_4(sc, reg) & ~x)
+
+#define SIO_SET(x)					\
+	CSR_WRITE_4(sc, WB_SIO,				\
+		CSR_READ_4(sc, WB_SIO) | x)
+
+#define SIO_CLR(x)					\
+	CSR_WRITE_4(sc, WB_SIO,				\
+		CSR_READ_4(sc, WB_SIO) & ~x)
+
+/*
+ * Send a read command and address to the EEPROM, check for ACK.
+ */
+static void wb_eeprom_putbyte(sc, addr)
+	struct wb_softc		*sc;
+	int			addr;
+{
+	register int		d, i;
+
+	d = addr | WB_EECMD_READ;
+
+	/*
+	 * Feed in each bit and stobe the clock.
+	 */
+	for (i = 0x400; i; i >>= 1) {
+		if (d & i) {
+			SIO_SET(WB_SIO_EE_DATAIN);
+		} else {
+			SIO_CLR(WB_SIO_EE_DATAIN);
+		}
+		DELAY(100);
+		SIO_SET(WB_SIO_EE_CLK);
+		DELAY(150);
+		SIO_CLR(WB_SIO_EE_CLK);
+		DELAY(100);
+	}
+
+	return;
+}
+
+/*
+ * Read a word of data stored in the EEPROM at address 'addr.'
+ */
+static void wb_eeprom_getword(sc, addr, dest)
+	struct wb_softc		*sc;
+	int			addr;
+	u_int16_t		*dest;
+{
+	register int		i;
+	u_int16_t		word = 0;
+
+	/* Enter EEPROM access mode. */
+	CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
+
+	/*
+	 * Send address of word we want to read.
+	 */
+	wb_eeprom_putbyte(sc, addr);
+
+	CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
+
+	/*
+	 * Start reading bits from EEPROM.
+	 */
+	for (i = 0x8000; i; i >>= 1) {
+		SIO_SET(WB_SIO_EE_CLK);
+		DELAY(100);
+		if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
+			word |= i;
+		SIO_CLR(WB_SIO_EE_CLK);
+		DELAY(100);
+	}
+
+	/* Turn off EEPROM access mode. */
+	CSR_WRITE_4(sc, WB_SIO, 0);
+
+	*dest = word;
+
+	return;
+}
+
+/*
+ * Read a sequence of words from the EEPROM.
+ */
+static void wb_read_eeprom(sc, dest, off, cnt, swap)
+	struct wb_softc		*sc;
+	caddr_t			dest;
+	int			off;
+	int			cnt;
+	int			swap;
+{
+	int			i;
+	u_int16_t		word = 0, *ptr;
+
+	for (i = 0; i < cnt; i++) {
+		wb_eeprom_getword(sc, off + i, &word);
+		ptr = (u_int16_t *)(dest + (i * 2));
+		if (swap)
+			*ptr = ntohs(word);
+		else
+			*ptr = word;
+	}
+
+	return;
+}
+
+/*
+ * Sync the PHYs by setting data bit and strobing the clock 32 times.
+ */
+static void wb_mii_sync(sc)
+	struct wb_softc		*sc;
+{
+	register int		i;
+
+	SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
+
+	for (i = 0; i < 32; i++) {
+		SIO_SET(WB_SIO_MII_CLK);
+		DELAY(1);
+		SIO_CLR(WB_SIO_MII_CLK);
+		DELAY(1);
+	}
+
+	return;
+}
+
+/*
+ * Clock a series of bits through the MII.
+ */
+static void wb_mii_send(sc, bits, cnt)
+	struct wb_softc		*sc;
+	u_int32_t		bits;
+	int			cnt;
+{
+	int			i;
+
+	SIO_CLR(WB_SIO_MII_CLK);
+
+	for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
+                if (bits & i) {
+			SIO_SET(WB_SIO_MII_DATAIN);
+                } else {
+			SIO_CLR(WB_SIO_MII_DATAIN);
+                }
+		DELAY(1);
+		SIO_CLR(WB_SIO_MII_CLK);
+		DELAY(1);
+		SIO_SET(WB_SIO_MII_CLK);
+	}
+}
+
+/*
+ * Read an PHY register through the MII.
+ */
+static int wb_mii_readreg(sc, frame)
+	struct wb_softc		*sc;
+	struct wb_mii_frame	*frame;
+	
+{
+	int			i, ack, s;
+
+	s = splimp();
+
+	/*
+	 * Set up frame for RX.
+	 */
+	frame->mii_stdelim = WB_MII_STARTDELIM;
+	frame->mii_opcode = WB_MII_READOP;
+	frame->mii_turnaround = 0;
+	frame->mii_data = 0;
+	
+	CSR_WRITE_4(sc, WB_SIO, 0);
+
+	/*
+ 	 * Turn on data xmit.
+	 */
+	SIO_SET(WB_SIO_MII_DIR);
+
+	wb_mii_sync(sc);
+
+	/*
+	 * Send command/address info.
+	 */
+	wb_mii_send(sc, frame->mii_stdelim, 2);
+	wb_mii_send(sc, frame->mii_opcode, 2);
+	wb_mii_send(sc, frame->mii_phyaddr, 5);
+	wb_mii_send(sc, frame->mii_regaddr, 5);
+
+	/* Idle bit */
+	SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
+	DELAY(1);
+	SIO_SET(WB_SIO_MII_CLK);
+	DELAY(1);
+
+	/* Turn off xmit. */
+	SIO_CLR(WB_SIO_MII_DIR);
+	/* Check for ack */
+	SIO_CLR(WB_SIO_MII_CLK);
+	DELAY(1);
+	SIO_SET(WB_SIO_MII_CLK);
+	DELAY(1);
+	ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
+	SIO_CLR(WB_SIO_MII_CLK);
+	DELAY(1);
+	SIO_SET(WB_SIO_MII_CLK);
+	DELAY(1);
+
+	/*
+	 * Now try reading data bits. If the ack failed, we still
+	 * need to clock through 16 cycles to keep the PHY(s) in sync.
+	 */
+	if (ack) {
+		for(i = 0; i < 16; i++) {
+			SIO_CLR(WB_SIO_MII_CLK);
+			DELAY(1);
+			SIO_SET(WB_SIO_MII_CLK);
+			DELAY(1);
+		}
+		goto fail;
+	}
+
+	for (i = 0x8000; i; i >>= 1) {
+		SIO_CLR(WB_SIO_MII_CLK);
+		DELAY(1);
+		if (!ack) {
+			if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
+				frame->mii_data |= i;
+			DELAY(1);
+		}
+		SIO_SET(WB_SIO_MII_CLK);
+		DELAY(1);
+	}
+
+fail:
+
+	SIO_CLR(WB_SIO_MII_CLK);
+	DELAY(1);
+	SIO_SET(WB_SIO_MII_CLK);
+	DELAY(1);
+
+	splx(s);
+
+	if (ack)
+		return(1);
+	return(0);
+}
+
+/*
+ * Write to a PHY register through the MII.
+ */
+static int wb_mii_writereg(sc, frame)
+	struct wb_softc		*sc;
+	struct wb_mii_frame	*frame;
+	
+{
+	int			s;
+
+	s = splimp();
+	/*
+	 * Set up frame for TX.
+	 */
+
+	frame->mii_stdelim = WB_MII_STARTDELIM;
+	frame->mii_opcode = WB_MII_WRITEOP;
+	frame->mii_turnaround = WB_MII_TURNAROUND;
+	
+	/*
+ 	 * Turn on data output.
+	 */
+	SIO_SET(WB_SIO_MII_DIR);
+
+	wb_mii_sync(sc);
+
+	wb_mii_send(sc, frame->mii_stdelim, 2);
+	wb_mii_send(sc, frame->mii_opcode, 2);
+	wb_mii_send(sc, frame->mii_phyaddr, 5);
+	wb_mii_send(sc, frame->mii_regaddr, 5);
+	wb_mii_send(sc, frame->mii_turnaround, 2);
+	wb_mii_send(sc, frame->mii_data, 16);
+
+	/* Idle bit. */
+	SIO_SET(WB_SIO_MII_CLK);
+	DELAY(1);
+	SIO_CLR(WB_SIO_MII_CLK);
+	DELAY(1);
+
+	/*
+	 * Turn off xmit.
+	 */
+	SIO_CLR(WB_SIO_MII_DIR);
+
+	splx(s);
+
+	return(0);
+}
+
+static u_int16_t wb_phy_readreg(sc, reg)
+	struct wb_softc		*sc;
+	int			reg;
+{
+	struct wb_mii_frame	frame;
+
+	bzero((char *)&frame, sizeof(frame));
+
+	frame.mii_phyaddr = sc->wb_phy_addr;
+	frame.mii_regaddr = reg;
+	wb_mii_readreg(sc, &frame);
+
+	return(frame.mii_data);
+}
+
+static void wb_phy_writereg(sc, reg, data)
+	struct wb_softc		*sc;
+	int			reg;
+	int			data;
+{
+	struct wb_mii_frame	frame;
+
+	bzero((char *)&frame, sizeof(frame));
+
+	frame.mii_phyaddr = sc->wb_phy_addr;
+	frame.mii_regaddr = reg;
+	frame.mii_data = data;
+
+	wb_mii_writereg(sc, &frame);
+
+	return;
+}
+
+static u_int8_t wb_calchash(addr)
+	caddr_t			addr;
+{
+	u_int32_t		crc, carry;
+	int			i, j;
+	u_int8_t		c;
+
+	/* Compute CRC for the address value. */
+	crc = 0xFFFFFFFF; /* initial value */
+
+	for (i = 0; i < 6; i++) {
+		c = *(addr + i);
+		for (j = 0; j < 8; j++) {
+			carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
+			crc <<= 1;
+			c >>= 1;
+			if (carry)
+				crc = (crc ^ 0x04c11db6) | carry;
+		}
+	}
+
+	/*
+	 * return the filter bit position
+	 * Note: I arrived at the following nonsense
+	 * through experimentation. It's not the usual way to
+	 * generate the bit position but it's the only thing
+	 * I could come up with that works.
+	 */
+	return(~(crc >> 26) & 0x0000003F);
+}
+
+/*
+ * Program the 64-bit multicast hash filter.
+ */
+static void wb_setmulti(sc)
+	struct wb_softc		*sc;
+{
+	struct ifnet		*ifp;
+	int			h = 0;
+	u_int32_t		hashes[2] = { 0, 0 };
+	struct arpcom		*ac = &sc->arpcom;
+	struct ether_multi	*enm;
+	struct ether_multistep	step;
+	u_int32_t		rxfilt;
+	int			mcnt = 0;
+
+	ifp = &sc->arpcom.ac_if;
+
+	rxfilt = CSR_READ_4(sc, WB_NETCFG);
+
+	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
+		rxfilt |= WB_NETCFG_RX_MULTI;
+		CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
+		CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
+		CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
+		return;
+	}
+
+	/* first, zot all the existing hash bits */
+	CSR_WRITE_4(sc, WB_MAR0, 0);
+	CSR_WRITE_4(sc, WB_MAR1, 0);
+
+	/* now program new ones */
+	ETHER_FIRST_MULTI(step, ac, enm);
+	while (enm != NULL) {
+		h = wb_calchash(enm->enm_addrlo);
+		if (h < 32)
+			hashes[0] |= (1 << h);
+		else
+			hashes[1] |= (1 << (h - 32));
+		mcnt++;
+		ETHER_NEXT_MULTI(step, enm);
+	}
+
+	if (mcnt)
+		rxfilt |= WB_NETCFG_RX_MULTI;
+	else
+		rxfilt &= ~WB_NETCFG_RX_MULTI;
+
+	CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
+	CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
+	CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
+
+	return;
+}
+
+/*
+ * Initiate an autonegotiation session.
+ */
+static void wb_autoneg_xmit(sc)
+	struct wb_softc		*sc;
+{
+	u_int16_t		phy_sts;
+
+	wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
+	DELAY(500);
+	while(wb_phy_readreg(sc, PHY_BMCR)
+			& PHY_BMCR_RESET);
+
+	phy_sts = wb_phy_readreg(sc, PHY_BMCR);
+	phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
+	wb_phy_writereg(sc, PHY_BMCR, phy_sts);
+
+	return;
+}
+
+/*
+ * Invoke autonegotiation on a PHY.
+ */
+static void wb_autoneg_mii(sc, flag, verbose)
+	struct wb_softc		*sc;
+	int			flag;
+	int			verbose;
+{
+	u_int16_t		phy_sts = 0, media, advert, ability;
+	struct ifnet		*ifp;
+	struct ifmedia		*ifm;
+
+	ifm = &sc->ifmedia;
+	ifp = &sc->arpcom.ac_if;
+
+	ifm->ifm_media = IFM_ETHER | IFM_AUTO;
+
+	/*
+	 * The 100baseT4 PHY on the 3c905-T4 has the 'autoneg supported'
+	 * bit cleared in the status register, but has the 'autoneg enabled'
+	 * bit set in the control register. This is a contradiction, and
+	 * I'm not sure how to handle it. If you want to force an attempt
+	 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
+	 * and see what happens.
+	 */
+#ifndef FORCE_AUTONEG_TFOUR
+	/*
+	 * First, see if autoneg is supported. If not, there's
+	 * no point in continuing.
+	 */
+	phy_sts = wb_phy_readreg(sc, PHY_BMSR);
+	if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
+		if (verbose)
+			printf("wb%d: autonegotiation not supported\n",
+							sc->wb_unit);
+		ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;	
+		return;
+	}
+#endif
+
+	switch (flag) {
+	case WB_FLAG_FORCEDELAY:
+		/*
+	 	 * XXX Never use this option anywhere but in the probe
+	 	 * routine: making the kernel stop dead in its tracks
+ 		 * for three whole seconds after we've gone multi-user
+		 * is really bad manners.
+	 	 */
+		wb_autoneg_xmit(sc);
+		DELAY(5000000);
+		break;
+	case WB_FLAG_SCHEDDELAY:
+		/*
+		 * Wait for the transmitter to go idle before starting
+		 * an autoneg session, otherwise wb_start() may clobber
+	 	 * our timeout, and we don't want to allow transmission
+		 * during an autoneg session since that can screw it up.
+	 	 */
+		if (sc->wb_cdata.wb_tx_head != NULL) {
+			sc->wb_want_auto = 1;
+			return;
+		}
+		wb_autoneg_xmit(sc);
+		ifp->if_timer = 5;
+		sc->wb_autoneg = 1;
+		sc->wb_want_auto = 0;
+		return;
+		break;
+	case WB_FLAG_DELAYTIMEO:
+		ifp->if_timer = 0;
+		sc->wb_autoneg = 0;
+		break;
+	default:
+		printf("wb%d: invalid autoneg flag: %d\n", sc->wb_unit, flag);
+		return;
+	}
+
+	if (wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
+		if (verbose)
+			printf("wb%d: autoneg complete, ", sc->wb_unit);
+		phy_sts = wb_phy_readreg(sc, PHY_BMSR);
+	} else {
+		if (verbose)
+			printf("wb%d: autoneg not complete, ", sc->wb_unit);
+	}
+
+	media = wb_phy_readreg(sc, PHY_BMCR);
+
+	/* Link is good. Report modes and set duplex mode. */
+	if (wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
+		if (verbose)
+			printf("link status good ");
+		advert = wb_phy_readreg(sc, PHY_ANAR);
+		ability = wb_phy_readreg(sc, PHY_LPAR);
+
+		if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
+			ifm->ifm_media = IFM_ETHER|IFM_100_T4;
+			media |= PHY_BMCR_SPEEDSEL;
+			media &= ~PHY_BMCR_DUPLEX;
+			printf("(100baseT4)\n");
+		} else if (advert & PHY_ANAR_100BTXFULL &&
+			ability & PHY_ANAR_100BTXFULL) {
+			ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
+			media |= PHY_BMCR_SPEEDSEL;
+			media |= PHY_BMCR_DUPLEX;
+			printf("(full-duplex, 100Mbps)\n");
+		} else if (advert & PHY_ANAR_100BTXHALF &&
+			ability & PHY_ANAR_100BTXHALF) {
+			ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
+			media |= PHY_BMCR_SPEEDSEL;
+			media &= ~PHY_BMCR_DUPLEX;
+			printf("(half-duplex, 100Mbps)\n");
+		} else if (advert & PHY_ANAR_10BTFULL &&
+			ability & PHY_ANAR_10BTFULL) {
+			ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
+			media &= ~PHY_BMCR_SPEEDSEL;
+			media |= PHY_BMCR_DUPLEX;
+			printf("(full-duplex, 10Mbps)\n");
+		} else /* if (advert & PHY_ANAR_10BTHALF &&
+			ability & PHY_ANAR_10BTHALF) */ {
+			ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
+			media &= ~PHY_BMCR_SPEEDSEL;
+			media &= ~PHY_BMCR_DUPLEX;
+			printf("(half-duplex, 10Mbps)\n");
+		}
+
+		media &= ~PHY_BMCR_AUTONEGENBL;
+
+		/* Set ASIC's duplex mode to match the PHY. */
+		wb_setcfg(sc, media);
+		wb_phy_writereg(sc, PHY_BMCR, media);
+	} else {
+		if (verbose)
+			printf("no carrier\n");
+	}
+
+	if (flag != WB_FLAG_FORCEDELAY)
+		wb_init(sc);
+
+	if (sc->wb_tx_pend) {
+		sc->wb_autoneg = 0;
+		sc->wb_tx_pend = 0;
+		wb_start(ifp);
+	}
+
+	return;
+}
+
+static void wb_getmode_mii(sc)
+	struct wb_softc		*sc;
+{
+	u_int16_t		bmsr;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	bmsr = wb_phy_readreg(sc, PHY_BMSR);
+
+	/* fallback */
+	sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
+
+	if (bmsr & PHY_BMSR_10BTHALF) {
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
+	}
+
+	if (bmsr & PHY_BMSR_10BTFULL) {
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
+	}
+
+	if (bmsr & PHY_BMSR_100BTXHALF) {
+		ifp->if_baudrate = 100000000;
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
+	}
+
+	if (bmsr & PHY_BMSR_100BTXFULL) {
+		ifp->if_baudrate = 100000000;
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
+	}
+
+	/* Some also support 100BaseT4. */
+	if (bmsr & PHY_BMSR_100BT4) {
+		ifp->if_baudrate = 100000000;
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
+#ifdef FORCE_AUTONEG_TFOUR
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
+#endif
+	}
+
+	if (bmsr & PHY_BMSR_CANAUTONEG) {
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
+	}
+
+	return;
+}
+
+/*
+ * Set speed and duplex mode.
+ */
+static void wb_setmode_mii(sc, media)
+	struct wb_softc		*sc;
+	int			media;
+{
+	u_int16_t		bmcr;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	/*
+	 * If an autoneg session is in progress, stop it.
+	 */
+	if (sc->wb_autoneg) {
+		printf("wb%d: canceling autoneg session\n", sc->wb_unit);
+		ifp->if_timer = sc->wb_autoneg = sc->wb_want_auto = 0;
+		bmcr = wb_phy_readreg(sc, PHY_BMCR);
+		bmcr &= ~PHY_BMCR_AUTONEGENBL;
+		wb_phy_writereg(sc, PHY_BMCR, bmcr);
+	}
+
+	printf("wb%d: selecting MII, ", sc->wb_unit);
+
+	bmcr = wb_phy_readreg(sc, PHY_BMCR);
+
+	bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
+			PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
+
+	if (IFM_SUBTYPE(media) == IFM_100_T4) {
+		printf("100Mbps/T4, half-duplex\n");
+		bmcr |= PHY_BMCR_SPEEDSEL;
+		bmcr &= ~PHY_BMCR_DUPLEX;
+	}
+
+	if (IFM_SUBTYPE(media) == IFM_100_TX) {
+		printf("100Mbps, ");
+		bmcr |= PHY_BMCR_SPEEDSEL;
+	}
+
+	if (IFM_SUBTYPE(media) == IFM_10_T) {
+		printf("10Mbps, ");
+		bmcr &= ~PHY_BMCR_SPEEDSEL;
+	}
+
+	if ((media & IFM_GMASK) == IFM_FDX) {
+		printf("full duplex\n");
+		bmcr |= PHY_BMCR_DUPLEX;
+	} else {
+		printf("half duplex\n");
+		bmcr &= ~PHY_BMCR_DUPLEX;
+	}
+
+	wb_setcfg(sc, bmcr);
+	wb_phy_writereg(sc, PHY_BMCR, bmcr);
+
+	return;
+}
+
+/*
+ * The Winbond manual states that in order to fiddle with the
+ * 'full-duplex' and '100Mbps' bits in the netconfig register, we
+ * first have to put the transmit and/or receive logic in the idle state.
+ */
+static void wb_setcfg(sc, bmcr)
+	struct wb_softc		*sc;
+	int			bmcr;
+{
+	int			i, restart = 0;
+
+	if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
+		restart = 1;
+		WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
+
+		for (i = 0; i < WB_TIMEOUT; i++) {
+			DELAY(10);
+			if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
+				(CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
+				break;
+		}
+
+		if (i == WB_TIMEOUT)
+			printf("wb%d: failed to force tx and "
+				"rx to idle state\n", sc->wb_unit);
+	}
+
+	if (bmcr & PHY_BMCR_SPEEDSEL)
+		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
+	else
+		WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
+
+	if (bmcr & PHY_BMCR_DUPLEX)
+		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
+	else
+		WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
+
+	if (restart)
+		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
+
+	return;
+}
+
+static void wb_reset(sc)
+	struct wb_softc		*sc;
+{
+	register int		i;
+
+	WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
+
+	for (i = 0; i < WB_TIMEOUT; i++) {
+		DELAY(10);
+		if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
+			break;
+	}
+	if (i == WB_TIMEOUT)
+		printf("wb%d: reset never completed!\n", sc->wb_unit);
+
+	/* Wait a little while for the chip to get its brains in order. */
+	DELAY(1000);
+
+	/* Reset the damn PHY too. */
+	if (sc->wb_pinfo != NULL)
+		wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
+
+        return;
+}
+
+/*
+ * Probe for a Winbond chip. Check the PCI vendor and device
+ * IDs against our list and return a device name if we find a match.
+ */
+static int
+wb_probe(parent, match, aux)
+	struct device *parent;
+	void *match, *aux;
+{
+	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
+
+	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_WINBOND) {
+		switch (PCI_PRODUCT(pa->pa_id)) {
+		case PCI_PRODUCT_WINBOND_W89C840F:
+			return (1);
+		}
+	}
+
+	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_COMPEX) {
+		switch (PCI_PRODUCT(pa->pa_id)) {
+		case PCI_PRODUCT_COMPEX_RL100ATX:
+			return (1);
+		}
+	}
+
+	return (0);
+}
+
+/*
+ * Attach the interface. Allocate softc structures, do ifmedia
+ * setup and ethernet/BPF attach.
+ */
+static void
+wb_attach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct wb_softc *sc = (struct wb_softc *)self;
+	struct pci_attach_args *pa = aux;
+	pci_chipset_tag_t pc = pa->pa_pc;
+	pci_intr_handle_t ih;
+	const char *intrstr = NULL;
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	bus_addr_t iobase;
+	bus_size_t iosize;
+	int i, media = IFM_ETHER|IFM_100_TX|IFM_FDX;
+	unsigned int round;
+	caddr_t roundptr;
+	u_int16_t phy_vid, phy_did, phy_sts;
+	struct wb_type		*p;
+	u_int32_t command;
+
+#if 0
+	s = splimp();
+#endif
+
+	sc->wb_unit = sc->sc_dev.dv_unit;
+
+	/*
+	 * Handle power management nonsense.
+	 */
+
+	command = pci_conf_read(pc, pa->pa_tag, WB_PCI_CAPID) & 0x000000FF;
+	if (command == 0x01) {
+
+		command = pci_conf_read(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL);
+		if (command & WB_PSTATE_MASK) {
+			u_int32_t		io, mem, irq;
+
+			/* Save important PCI config data. */
+			io = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOIO);
+			mem = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOMEM);
+			irq = pci_conf_read(pc, pa->pa_tag, WB_PCI_INTLINE);
+
+			/* Reset the power state. */
+			printf("%s: chip is in D%d power mode "
+			    "-- setting to D0\n", sc->sc_dev.dv_xname,
+			    command & WB_PSTATE_MASK);
+			command &= 0xFFFFFFFC;
+			pci_conf_write(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL,
+			    command);
+
+			/* Restore PCI config data. */
+			pci_conf_write(pc, pa->pa_tag, WB_PCI_LOIO, io);
+			pci_conf_write(pc, pa->pa_tag, WB_PCI_LOMEM, mem);
+			pci_conf_write(pc, pa->pa_tag, WB_PCI_INTLINE, irq);
+		}
+	}
+
+	/*
+	 * Map control/status registers.
+	 */
+	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
+	command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
+	    PCI_COMMAND_MASTER_ENABLE;
+	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
+	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
+
+#ifdef WB_USEIOSPACE
+	if (!(command & PCI_COMMAND_IO_ENABLE)) {
+		printf(": failed to enable I/O ports!\n");
+		goto fail;
+	}
+	if (pci_io_find(pc, pa->pa_tag, WB_PCI_LOIO, &iobase, &iosize)) {
+		printf(": can't find i/o space\n");
+		goto fail;
+	}
+	if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->wb_bhandle)) {
+		printf(": can't map i/o space\n");
+		goto fail;
+	}
+	sc->wb_btag = pa->pa_iot;
+#else
+	if (!(command & PCI_COMMAND_IO_ENABLE)) {
+		printf(": failed to enable memory mapping!\n");
+		goto fail;
+	}
+	if (pci_mem_find(pc, pa->pa_tag, WB_PCI_LOMEM, &iobase, &iosize, NULL)){
+		printf(": can't find mem space\n");
+		goto fail;
+	}
+	if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->wb_bhandle)) {
+		printf(": can't map mem space\n");
+		goto fail;
+	}
+	sc->wb_btag = pa->pa_memt;
+#endif
+
+	/* Allocate interrupt */
+	if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
+	    pa->pa_intrline, &ih)) {
+		printf(": couldn't map interrupt\n");
+		goto fail;
+	}
+	intrstr = pci_intr_string(pc, ih);
+	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wb_intr, sc,
+	    self->dv_xname);
+	if (sc->sc_ih == NULL) {
+		printf(": couldn't establish interrupt");
+		if (intrstr != NULL)
+			printf(" at %s", intrstr);
+		printf("\n");
+		goto fail;
+	}
+	printf(": %s", intrstr);
+
+	/* Reset the adapter. */
+	wb_reset(sc);
+
+	/*
+	 * Get station address from the EEPROM.
+	 */
+	wb_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0, 3, 0);
+	printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr));
+
+	sc->wb_ldata_ptr = malloc(sizeof(struct wb_list_data) + 8,
+				M_DEVBUF, M_NOWAIT);
+	if (sc->wb_ldata_ptr == NULL) {
+		printf("%s: no memory for list buffers!\n",sc->sc_dev.dv_xname);
+		return;
+	}
+
+	sc->wb_ldata = (struct wb_list_data *)sc->wb_ldata_ptr;
+	round = (unsigned int)sc->wb_ldata_ptr & 0xF;
+	roundptr = sc->wb_ldata_ptr;
+	for (i = 0; i < 8; i++) {
+		if (round % 8) {
+			round++;
+			roundptr++;
+		} else
+			break;
+	}
+	sc->wb_ldata = (struct wb_list_data *)roundptr;
+	bzero(sc->wb_ldata, sizeof(struct wb_list_data));
+
+	ifp->if_softc = sc;
+	ifp->if_mtu = ETHERMTU;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = wb_ioctl;
+	ifp->if_output = ether_output;
+	ifp->if_start = wb_start;
+	ifp->if_watchdog = wb_watchdog;
+	ifp->if_baudrate = 10000000;
+	ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
+	bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
+
+	for (i = WB_PHYADDR_MIN; i < WB_PHYADDR_MAX + 1; i++) {
+		sc->wb_phy_addr = i;
+		wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
+		DELAY(500);
+		while(wb_phy_readreg(sc, PHY_BMCR)
+				& PHY_BMCR_RESET);
+		if ((phy_sts = wb_phy_readreg(sc, PHY_BMSR)))
+			break;
+	}
+	if (phy_sts) {
+		phy_vid = wb_phy_readreg(sc, PHY_VENID);
+		phy_did = wb_phy_readreg(sc, PHY_DEVID);
+		p = wb_phys;
+		while(p->wb_vid) {
+			if (phy_vid == p->wb_vid &&
+				(phy_did | 0x000F) == p->wb_did) {
+				sc->wb_pinfo = p;
+				break;
+			}
+			p++;
+		}
+		if (sc->wb_pinfo == NULL)
+			sc->wb_pinfo = &wb_phys[PHY_UNKNOWN];
+	} else {
+		printf("wb%d: MII without any phy!\n", sc->wb_unit);
+		goto fail;
+	}
+
+	/*
+	 * Do ifmedia setup.
+	 */
+	ifmedia_init(&sc->ifmedia, 0, wb_ifmedia_upd, wb_ifmedia_sts);
+
+	wb_getmode_mii(sc);
+	wb_autoneg_mii(sc, WB_FLAG_FORCEDELAY, 1);
+	media = sc->ifmedia.ifm_media;
+	wb_stop(sc);
+
+	ifmedia_set(&sc->ifmedia, media);
+
+	/*
+	 * Call MI attach routines.
+	 */
+	if_attach(ifp);
+	ether_ifattach(ifp);
+
+#if NBPFILTER > 0
+	bpfattach(&sc->arpcom.ac_if.if_bpf, ifp,
+	    DLT_EN10MB, sizeof(struct ether_header));
+#endif
+	shutdownhook_establish(wb_shutdown, sc);
+
+fail:
+#if 0
+	splx(s);
+#endif
+	return;
+}
+
+/*
+ * Initialize the transmit descriptors.
+ */
+static int wb_list_tx_init(sc)
+	struct wb_softc		*sc;
+{
+	struct wb_chain_data	*cd;
+	struct wb_list_data	*ld;
+	int			i;
+
+	cd = &sc->wb_cdata;
+	ld = sc->wb_ldata;
+
+	for (i = 0; i < WB_TX_LIST_CNT; i++) {
+		cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
+		if (i == (WB_TX_LIST_CNT - 1)) {
+			cd->wb_tx_chain[i].wb_nextdesc =
+				&cd->wb_tx_chain[0];
+		} else {
+			cd->wb_tx_chain[i].wb_nextdesc =
+				&cd->wb_tx_chain[i + 1];
+		}
+	}
+
+	cd->wb_tx_free = &cd->wb_tx_chain[0];
+	cd->wb_tx_tail = cd->wb_tx_head = NULL;
+
+	return(0);
+}
+
+
+/*
+ * Initialize the RX descriptors and allocate mbufs for them. Note that
+ * we arrange the descriptors in a closed ring, so that the last descriptor
+ * points back to the first.
+ */
+static int wb_list_rx_init(sc)
+	struct wb_softc		*sc;
+{
+	struct wb_chain_data	*cd;
+	struct wb_list_data	*ld;
+	int			i;
+
+	cd = &sc->wb_cdata;
+	ld = sc->wb_ldata;
+
+	for (i = 0; i < WB_RX_LIST_CNT; i++) {
+		cd->wb_rx_chain[i].wb_ptr =
+			(struct wb_desc *)&ld->wb_rx_list[i];
+		if (wb_newbuf(sc, &cd->wb_rx_chain[i]) == ENOBUFS)
+			return(ENOBUFS);
+		if (i == (WB_RX_LIST_CNT - 1)) {
+			cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
+			ld->wb_rx_list[i].wb_next = 
+					vtophys(&ld->wb_rx_list[0]);
+		} else {
+			cd->wb_rx_chain[i].wb_nextdesc =
+					&cd->wb_rx_chain[i + 1];
+			ld->wb_rx_list[i].wb_next =
+					vtophys(&ld->wb_rx_list[i + 1]);
+		}
+	}
+
+	cd->wb_rx_head = &cd->wb_rx_chain[0];
+
+	return(0);
+}
+
+/*
+ * Initialize an RX descriptor and attach an MBUF cluster.
+ */
+static int wb_newbuf(sc, c)
+	struct wb_softc		*sc;
+	struct wb_chain_onefrag	*c;
+{
+	struct mbuf		*m_new = NULL;
+
+	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+	if (m_new == NULL)
+		return(ENOBUFS);
+
+	MCLGET(m_new, M_DONTWAIT);
+	if (!(m_new->m_flags & M_EXT)) {
+		m_freem(m_new);
+		return(ENOBUFS);
+	}
+
+	c->wb_mbuf = m_new;
+	c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
+	c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | (MCLBYTES - 1);
+	c->wb_ptr->wb_status = WB_RXSTAT;
+
+	return(0);
+}
+
+/*
+ * A frame has been uploaded: pass the resulting mbuf chain up to
+ * the higher level protocols.
+ */
+static void wb_rxeof(sc)
+	struct wb_softc		*sc;
+{
+        struct ether_header	*eh;
+        struct mbuf		*m;
+        struct ifnet		*ifp;
+	struct wb_chain_onefrag	*cur_rx;
+	int			total_len = 0;
+	u_int32_t		rxstat;
+
+	ifp = &sc->arpcom.ac_if;
+
+	while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
+							WB_RXSTAT_OWN)) {
+		cur_rx = sc->wb_cdata.wb_rx_head;
+		sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
+
+		if ((rxstat & WB_RXSTAT_MIIERR)
+			 || WB_RXBYTES(cur_rx->wb_ptr->wb_status) == 0) {
+			ifp->if_ierrors++;
+			wb_reset(sc);
+			printf("wb%x: receiver babbling: possible chip "
+				"bug, forcing reset\n", sc->wb_unit);
+			ifp->if_flags |= IFF_OACTIVE;
+			ifp->if_timer = 2;
+			return;
+		}
+
+		if (rxstat & WB_RXSTAT_RXERR) {
+			ifp->if_ierrors++;
+			cur_rx->wb_ptr->wb_ctl =
+				WB_RXCTL_RLINK | (MCLBYTES - 1);
+			cur_rx->wb_ptr->wb_status = WB_RXSTAT;
+			continue;
+		}
+
+		/* No errors; receive the packet. */	
+		total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
+
+		/*
+		 * XXX The Winbond chip includes the CRC with every
+		 * received frame, and there's no way to turn this
+		 * behavior off (at least, I can't find anything in
+	 	 * the manual that explains how to do it) so we have
+		 * to trim off the CRC manually.
+		 */
+		total_len -= ETHER_CRC_LEN;
+
+		if (total_len < MINCLSIZE) {
+			m = m_devget(mtod(cur_rx->wb_mbuf, char *),
+				total_len, 0, ifp, NULL);
+			cur_rx->wb_ptr->wb_ctl =
+				WB_RXCTL_RLINK | (MCLBYTES - 1);
+			cur_rx->wb_ptr->wb_status = WB_RXSTAT;
+			if (m == NULL) {
+				ifp->if_ierrors++;
+				continue;
+			}
+		} else {
+			m = cur_rx->wb_mbuf;
+		/*
+		 * Try to conjure up a new mbuf cluster. If that
+		 * fails, it means we have an out of memory condition and
+		 * should leave the buffer in place and continue. This will
+		 * result in a lost packet, but there's little else we
+		 * can do in this situation.
+		 */
+			if (wb_newbuf(sc, cur_rx) == ENOBUFS) {
+				ifp->if_ierrors++;
+				cur_rx->wb_ptr->wb_ctl =
+					WB_RXCTL_RLINK | (MCLBYTES - 1);
+				cur_rx->wb_ptr->wb_status = WB_RXSTAT;
+				continue;
+			}
+			m->m_pkthdr.rcvif = ifp;
+			m->m_pkthdr.len = m->m_len = total_len;
+		}
+
+		ifp->if_ipackets++;
+		eh = mtod(m, struct ether_header *);
+
+#if NBPFILTER > 0
+		/*
+		 * Handle BPF listeners. Let the BPF user see the packet.
+		 */
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m);
+#endif
+		/* Remove header from mbuf and pass it on. */
+		m_adj(m, sizeof(struct ether_header));
+		ether_input(ifp, eh, m);
+	}
+
+	return;
+}
+
+void wb_rxeoc(sc)
+	struct wb_softc		*sc;
+{
+	wb_rxeof(sc);
+
+	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
+	CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
+	WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
+	if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
+		CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
+
+	return;
+}
+
+/*
+ * A frame was downloaded to the chip. It's safe for us to clean up
+ * the list buffers.
+ */
+static void wb_txeof(sc)
+	struct wb_softc		*sc;
+{
+	struct wb_chain		*cur_tx;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	/* Clear the timeout timer. */
+	ifp->if_timer = 0;
+
+	if (sc->wb_cdata.wb_tx_head == NULL)
+		return;
+
+	/*
+	 * Go through our tx list and free mbufs for those
+	 * frames that have been transmitted.
+	 */
+	while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
+		u_int32_t		txstat;
+
+		cur_tx = sc->wb_cdata.wb_tx_head;
+		txstat = WB_TXSTATUS(cur_tx);
+
+		if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
+			break;
+
+		if (txstat & WB_TXSTAT_TXERR) {
+			ifp->if_oerrors++;
+			if (txstat & WB_TXSTAT_ABORT)
+				ifp->if_collisions++;
+			if (txstat & WB_TXSTAT_LATECOLL)
+				ifp->if_collisions++;
+		}
+
+		ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
+
+		ifp->if_opackets++;
+		m_freem(cur_tx->wb_mbuf);
+		cur_tx->wb_mbuf = NULL;
+
+		if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
+			sc->wb_cdata.wb_tx_head = NULL;
+			sc->wb_cdata.wb_tx_tail = NULL;
+			break;
+		}
+
+		sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
+	}
+
+	return;
+}
+
+/*
+ * TX 'end of channel' interrupt handler.
+ */
+static void wb_txeoc(sc)
+	struct wb_softc		*sc;
+{
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	ifp->if_timer = 0;
+
+	if (sc->wb_cdata.wb_tx_head == NULL) {
+		ifp->if_flags &= ~IFF_OACTIVE;
+		sc->wb_cdata.wb_tx_tail = NULL;
+		if (sc->wb_want_auto)
+			wb_autoneg_mii(sc, WB_FLAG_SCHEDDELAY, 1);
+	} else {
+		if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
+			WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
+			ifp->if_timer = 5;
+			CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
+		}
+	}
+
+	return;
+}
+
+static int wb_intr(arg)
+	void			*arg;
+{
+	struct wb_softc		*sc;
+	struct ifnet		*ifp;
+	u_int32_t		status;
+	int			r = 0;
+
+	sc = arg;
+	ifp = &sc->arpcom.ac_if;
+
+	if (!(ifp->if_flags & IFF_UP))
+		return (r);
+
+	/* Disable interrupts. */
+	CSR_WRITE_4(sc, WB_IMR, 0x00000000);
+
+	for (;;) {
+
+		status = CSR_READ_4(sc, WB_ISR);
+		if (status)
+			CSR_WRITE_4(sc, WB_ISR, status);
+
+		if ((status & WB_INTRS) == 0)
+			break;
+
+		r = 1;
+
+		if (status & WB_ISR_RX_OK)
+			wb_rxeof(sc);
+
+		if (status & WB_ISR_RX_IDLE)
+			wb_rxeoc(sc);
+
+		if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
+			ifp->if_ierrors++;
+#ifdef foo
+			wb_stop(sc);
+			wb_reset(sc);
+			wb_init(sc);
+#endif
+		}
+
+		if (status & WB_ISR_TX_OK)
+			wb_txeof(sc);
+
+		if (status & WB_ISR_TX_NOBUF)
+			wb_txeoc(sc);
+
+		if (status & WB_ISR_TX_IDLE) {
+			wb_txeof(sc);
+			if (sc->wb_cdata.wb_tx_head != NULL) {
+				WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
+				CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
+			}
+		}
+
+		if (status & WB_ISR_TX_UNDERRUN) {
+			ifp->if_oerrors++;
+			wb_txeof(sc);
+			WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
+			/* Jack up TX threshold */
+			sc->wb_txthresh += WB_TXTHRESH_CHUNK;
+			WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
+			WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
+			WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
+		}
+
+		if (status & WB_ISR_BUS_ERR) {
+			wb_reset(sc);
+			wb_init(sc);
+		}
+
+	}
+
+	/* Re-enable interrupts. */
+	CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
+
+	if (ifp->if_snd.ifq_head != NULL) {
+		wb_start(ifp);
+	}
+
+	return (r);
+}
+
+/*
+ * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
+ * pointers to the fragment pointers.
+ */
+static int wb_encap(sc, c, m_head)
+	struct wb_softc		*sc;
+	struct wb_chain		*c;
+	struct mbuf		*m_head;
+{
+	int			frag = 0;
+	struct wb_desc		*f = NULL;
+	int			total_len;
+	struct mbuf		*m;
+
+	/*
+ 	 * Start packing the mbufs in this chain into
+	 * the fragment pointers. Stop when we run out
+ 	 * of fragments or hit the end of the mbuf chain.
+	 */
+	m = m_head;
+	total_len = 0;
+
+	for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
+		if (m->m_len != 0) {
+			if (frag == WB_MAXFRAGS)
+				break;
+			total_len += m->m_len;
+			f = &c->wb_ptr->wb_frag[frag];
+			f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
+			if (frag == 0) {
+				f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
+				f->wb_status = 0;
+			} else
+				f->wb_status = WB_TXSTAT_OWN;
+			f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
+			f->wb_data = vtophys(mtod(m, vm_offset_t));
+			frag++;
+		}
+	}
+
+	/*
+	 * Handle special case: we used up all 16 fragments,
+	 * but we have more mbufs left in the chain. Copy the
+	 * data into an mbuf cluster. Note that we don't
+	 * bother clearing the values in the other fragment
+	 * pointers/counters; it wouldn't gain us anything,
+	 * and would waste cycles.
+	 */
+	if (m != NULL) {
+		struct mbuf		*m_new = NULL;
+
+		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+		if (m_new == NULL)
+			return(1);
+		if (m_head->m_pkthdr.len > MHLEN) {
+			MCLGET(m_new, M_DONTWAIT);
+			if (!(m_new->m_flags & M_EXT)) {
+				m_freem(m_new);
+				return(1);
+			}
+		}
+		m_copydata(m_head, 0, m_head->m_pkthdr.len,	
+					mtod(m_new, caddr_t));
+		m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
+		m_freem(m_head);
+		m_head = m_new;
+		f = &c->wb_ptr->wb_frag[0];
+		f->wb_status = 0;
+		f->wb_data = vtophys(mtod(m_new, caddr_t));
+		f->wb_ctl = total_len = m_new->m_len;
+		f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
+		frag = 1;
+	}
+
+	if (total_len < WB_MIN_FRAMELEN) {
+		f = &c->wb_ptr->wb_frag[frag];
+		f->wb_ctl = WB_MIN_FRAMELEN - total_len;
+		f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
+		f->wb_ctl |= WB_TXCTL_TLINK;
+		f->wb_status = WB_TXSTAT_OWN;
+		frag++;
+	}
+
+	c->wb_mbuf = m_head;
+	c->wb_lastdesc = frag - 1;
+	WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
+	WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
+
+	return(0);
+}
+
+/*
+ * Main transmit routine. To avoid having to do mbuf copies, we put pointers
+ * to the mbuf data regions directly in the transmit lists. We also save a
+ * copy of the pointers since the transmit list fragment pointers are
+ * physical addresses.
+ */
+
+static void wb_start(ifp)
+	struct ifnet		*ifp;
+{
+	struct wb_softc		*sc;
+	struct mbuf		*m_head = NULL;
+	struct wb_chain		*cur_tx = NULL, *start_tx;
+
+	sc = ifp->if_softc;
+
+	if (sc->wb_autoneg) {
+		sc->wb_tx_pend = 1;
+		return;
+	}
+
+	/*
+	 * Check for an available queue slot. If there are none,
+	 * punt.
+	 */
+	if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
+		ifp->if_flags |= IFF_OACTIVE;
+		return;
+	}
+
+	start_tx = sc->wb_cdata.wb_tx_free;
+
+	while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
+		IF_DEQUEUE(&ifp->if_snd, m_head);
+		if (m_head == NULL)
+			break;
+
+		/* Pick a descriptor off the free list. */
+		cur_tx = sc->wb_cdata.wb_tx_free;
+		sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
+
+		/* Pack the data into the descriptor. */
+		wb_encap(sc, cur_tx, m_head);
+
+		if (cur_tx != start_tx)
+			WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
+
+#if NBPFILTER > 0
+		/*
+		 * If there's a BPF listener, bounce a copy of this frame
+		 * to him.
+		 */
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, cur_tx->wb_mbuf);
+#endif
+	}
+
+	/*
+	 * If there are no packets queued, bail.
+	 */
+	if (cur_tx == NULL)
+		return;
+
+	/*
+	 * Place the request for the upload interrupt
+	 * in the last descriptor in the chain. This way, if
+	 * we're chaining several packets at once, we'll only
+	 * get an interupt once for the whole chain rather than
+	 * once for each packet.
+	 */
+	WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
+	cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
+	sc->wb_cdata.wb_tx_tail = cur_tx;
+
+	if (sc->wb_cdata.wb_tx_head == NULL) {
+		sc->wb_cdata.wb_tx_head = start_tx;
+		WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
+		CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
+	} else {
+		/*
+		 * We need to distinguish between the case where
+		 * the own bit is clear because the chip cleared it
+		 * and where the own bit is clear because we haven't
+		 * set it yet. The magic value WB_UNSET is just some
+		 * ramdomly chosen number which doesn't have the own
+	 	 * bit set. When we actually transmit the frame, the
+		 * status word will have _only_ the own bit set, so
+		 * the txeoc handler will be able to tell if it needs
+		 * to initiate another transmission to flush out pending
+		 * frames.
+		 */
+		WB_TXOWN(start_tx) = WB_UNSENT;
+	}
+
+	/*
+	 * Set a timeout in case the chip goes out to lunch.
+	 */
+	ifp->if_timer = 5;
+
+	return;
+}
+
+static void wb_init(xsc)
+	void			*xsc;
+{
+	struct wb_softc		*sc = xsc;
+	struct ifnet		*ifp = &sc->arpcom.ac_if;
+	int			s, i;
+	u_int16_t		phy_bmcr = 0;
+
+	if (sc->wb_autoneg)
+		return;
+
+	s = splimp();
+
+	if (sc->wb_pinfo != NULL)
+		phy_bmcr = wb_phy_readreg(sc, PHY_BMCR);
+
+	/*
+	 * Cancel pending I/O and free all RX/TX buffers.
+	 */
+	wb_stop(sc);
+	wb_reset(sc);
+
+	sc->wb_txthresh = WB_TXTHRESH_INIT;
+
+	/*
+	 * Set cache alignment and burst length.
+	 */
+	CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
+	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
+	WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
+
+	/* This doesn't tend to work too well at 100Mbps. */
+	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
+
+	wb_setcfg(sc, phy_bmcr);
+
+	/* Init our MAC address */
+	for (i = 0; i < ETHER_ADDR_LEN; i++) {
+		CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
+	}
+
+	/* Init circular RX list. */
+	if (wb_list_rx_init(sc) == ENOBUFS) {
+		printf("wb%d: initialization failed: no "
+			"memory for rx buffers\n", sc->wb_unit);
+		wb_stop(sc);
+		(void)splx(s);
+		return;
+	}
+
+	/* Init TX descriptors. */
+	wb_list_tx_init(sc);
+
+	/* If we want promiscuous mode, set the allframes bit. */
+	if (ifp->if_flags & IFF_PROMISC) {
+		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
+	} else {
+		WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
+	}
+
+	/*
+	 * Set capture broadcast bit to capture broadcast frames.
+	 */
+	if (ifp->if_flags & IFF_BROADCAST) {
+		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
+	} else {
+		WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
+	}
+
+	/*
+	 * Program the multicast filter, if necessary.
+	 */
+	wb_setmulti(sc);
+
+	/*
+	 * Load the address of the RX list.
+	 */
+	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
+	CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
+
+	/*
+	 * Enable interrupts.
+	 */
+	CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
+	CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
+
+	/* Enable receiver and transmitter. */
+	WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
+	CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
+
+	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
+	CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
+	WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
+
+	/* Restore state of BMCR */
+	if (sc->wb_pinfo != NULL)
+		wb_phy_writereg(sc, PHY_BMCR, phy_bmcr);
+
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	(void)splx(s);
+
+	return;
+}
+
+/*
+ * Set media options.
+ */
+static int wb_ifmedia_upd(ifp)
+	struct ifnet		*ifp;
+{
+	struct wb_softc		*sc;
+	struct ifmedia		*ifm;
+
+	sc = ifp->if_softc;
+	ifm = &sc->ifmedia;
+
+	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
+		return(EINVAL);
+
+	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
+		wb_autoneg_mii(sc, WB_FLAG_SCHEDDELAY, 1);
+	else
+		wb_setmode_mii(sc, ifm->ifm_media);
+
+	return(0);
+}
+
+/*
+ * Report current media status.
+ */
+static void wb_ifmedia_sts(ifp, ifmr)
+	struct ifnet		*ifp;
+	struct ifmediareq	*ifmr;
+{
+	struct wb_softc		*sc;
+	u_int16_t		advert = 0, ability = 0;
+
+	sc = ifp->if_softc;
+
+	ifmr->ifm_active = IFM_ETHER;
+
+	if (!(wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
+		if (wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
+			ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
+		else
+			ifmr->ifm_active = IFM_ETHER|IFM_10_T;
+		if (wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
+			ifmr->ifm_active |= IFM_FDX;
+		else
+			ifmr->ifm_active |= IFM_HDX;
+		return;
+	}
+
+	ability = wb_phy_readreg(sc, PHY_LPAR);
+	advert = wb_phy_readreg(sc, PHY_ANAR);
+	if (advert & PHY_ANAR_100BT4 &&
+		ability & PHY_ANAR_100BT4) {
+		ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
+	} else if (advert & PHY_ANAR_100BTXFULL &&
+		ability & PHY_ANAR_100BTXFULL) {
+		ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
+	} else if (advert & PHY_ANAR_100BTXHALF &&
+		ability & PHY_ANAR_100BTXHALF) {
+		ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
+	} else if (advert & PHY_ANAR_10BTFULL &&
+		ability & PHY_ANAR_10BTFULL) {
+		ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
+	} else if (advert & PHY_ANAR_10BTHALF &&
+		ability & PHY_ANAR_10BTHALF) {
+		ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
+	}
+
+	return;
+}
+
+static int wb_ioctl(ifp, command, data)
+	struct ifnet		*ifp;
+	u_long			command;
+	caddr_t			data;
+{
+	struct wb_softc		*sc = ifp->if_softc;
+	struct ifreq		*ifr = (struct ifreq *) data;
+	struct ifaddr		*ifa = (struct ifaddr *)data;
+	int			s, error = 0;
+
+	s = splimp();
+
+	if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
+		splx(s);
+		return (error);
+	}
+
+	switch(command) {
+	case SIOCSIFADDR:
+		ifp->if_flags |= IFF_UP;
+		switch (ifa->ifa_addr->sa_family) {
+#ifdef INET
+		case AF_INET:
+			wb_init(sc);
+			arp_ifinit(&sc->arpcom, ifa);
+			break;
+#endif /* INET */
+		default:
+			wb_init(sc);
+		}
+	case SIOCSIFFLAGS:
+		if (ifp->if_flags & IFF_UP) {
+			wb_init(sc);
+		} else {
+			if (ifp->if_flags & IFF_RUNNING)
+				wb_stop(sc);
+		}
+		error = 0;
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		wb_setmulti(sc);
+		error = 0;
+		break;
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
+		break;
+	default:
+		error = EINVAL;
+		break;
+	}
+
+	(void)splx(s);
+
+	return(error);
+}
+
+static void wb_watchdog(ifp)
+	struct ifnet		*ifp;
+{
+	struct wb_softc		*sc;
+
+	sc = ifp->if_softc;
+
+	if (sc->wb_autoneg) {
+		wb_autoneg_mii(sc, WB_FLAG_DELAYTIMEO, 1);
+		return;
+	}
+
+	ifp->if_oerrors++;
+	printf("wb%d: watchdog timeout\n", sc->wb_unit);
+
+	if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
+		printf("wb%d: no carrier - transceiver cable problem?\n",
+								sc->wb_unit);
+
+	wb_stop(sc);
+	wb_reset(sc);
+	wb_init(sc);
+
+	if (ifp->if_snd.ifq_head != NULL)
+		wb_start(ifp);
+
+	return;
+}
+
+/*
+ * Stop the adapter and free any mbufs allocated to the
+ * RX and TX lists.
+ */
+static void wb_stop(sc)
+	struct wb_softc		*sc;
+{
+	register int		i;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+	ifp->if_timer = 0;
+
+	WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
+	CSR_WRITE_4(sc, WB_IMR, 0x00000000);
+	CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
+	CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
+
+	/*
+	 * Free data in the RX lists.
+	 */
+	for (i = 0; i < WB_RX_LIST_CNT; i++) {
+		if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
+			m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
+			sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
+		}
+	}
+	bzero((char *)&sc->wb_ldata->wb_rx_list,
+		sizeof(sc->wb_ldata->wb_rx_list));
+
+	/*
+	 * Free the TX list buffers.
+	 */
+	for (i = 0; i < WB_TX_LIST_CNT; i++) {
+		if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
+			m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
+			sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
+		}
+	}
+
+	bzero((char *)&sc->wb_ldata->wb_tx_list,
+		sizeof(sc->wb_ldata->wb_tx_list));
+
+	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+
+	return;
+}
+
+/*
+ * Stop all chip I/O so that the kernel's probe routines don't
+ * get confused by errant DMAs when rebooting.
+ */
+static void wb_shutdown(arg)
+	void			*arg;
+{
+	struct wb_softc		*sc = (struct wb_softc *)arg;
+
+	wb_stop(sc);
+
+	return;
+}
+
+struct cfattach wb_ca = {
+	sizeof(struct wb_softc), wb_probe, wb_attach
+};
+
+struct cfdriver wb_cd = {
+	0, "wb", DV_IFNET
+};
diff --git a/sys/dev/pci/if_wbreg.h b/sys/dev/pci/if_wbreg.h
new file mode 100644
index 00000000000..6a51029125b
--- /dev/null
+++ b/sys/dev/pci/if_wbreg.h
@@ -0,0 +1,591 @@
+/*	$OpenBSD: if_wbreg.h,v 1.1 1999/03/11 18:20:13 jason Exp $	*/
+
+/*
+ * Copyright (c) 1997, 1998
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	$FreeBSD: if_wbreg.h,v 1.2 1999/01/16 06:25:59 wpaul Exp $
+ */
+
+/*
+ * Winbond register definitions.
+ */
+
+#define WB_BUSCTL		0x00	/* bus control */
+#define WB_TXSTART		0x04	/* tx start demand */
+#define WB_RXSTART		0x08	/* rx start demand */
+#define WB_RXADDR		0x0C	/* rx descriptor list start addr */
+#define WB_TXADDR		0x10	/* tx descriptor list start addr */
+#define WB_ISR			0x14	/* interrupt status register */
+#define WB_NETCFG		0x18	/* network config register */
+#define WB_IMR			0x1C	/* interrupt mask */
+#define WB_FRAMESDISCARDED	0x20	/* # of discarded frames */
+#define WB_SIO			0x24	/* MII and ROM/EEPROM access */
+#define WB_BOOTROMADDR		0x28
+#define WB_TIMER		0x2C	/* general timer */
+#define WB_CURRXCTL		0x30	/* current RX descriptor */
+#define WB_CURRXBUF		0x34	/* current RX buffer */
+#define WB_MAR0			0x38	/* multicast filter 0 */
+#define WB_MAR1			0x3C	/* multicast filter 1 */
+#define WB_NODE0		0x40	/* station address 0 */
+#define WB_NODE1		0x44	/* station address 1 */
+#define WB_BOOTROMSIZE		0x48	/* boot ROM size */
+#define WB_CURTXCTL		0x4C	/* current TX descriptor */
+#define WB_CURTXBUF		0x50	/* current TX buffer */
+
+/*
+ * Bus control bits.
+ */
+#define WB_BUSCTL_RESET		0x00000001
+#define WB_BUSCTL_ARBITRATION	0x00000002
+#define WB_BUSCTL_SKIPLEN	0x0000007C
+#define WB_BUSCTL_BUF_BIGENDIAN	0x00000080
+#define WB_BUSCTL_BURSTLEN	0x00003F00
+#define WB_BUSCTL_CACHEALIGN	0x0000C000
+#define WB_BUSCTL_DES_BIGENDIAN	0x00100000
+#define WB_BUSCTL_WAIT		0x00200000
+
+#define WB_SKIPLEN_1LONG	0x00000004
+#define WB_SKIPLEN_2LONG	0x00000008
+#define WB_SKIPLEN_3LONG	0x00000010
+#define WB_SKIPLEN_4LONG	0x00000020
+#define WB_SKIPLEN_5LONG	0x00000040
+
+#define WB_CACHEALIGN_8LONG	0x00004000
+#define WB_CACHEALIGN_16LONG	0x00008000
+#define WB_CACHEALIGN_32LONG	0x0000C000
+
+#define WB_BURSTLEN_USECA	0x00000000
+#define WB_BURSTLEN_1LONG	0x00000100
+#define WB_BURSTLEN_2LONG	0x00000200
+#define WB_BURSTLEN_4LONG	0x00000400
+#define WB_BURSTLEN_8LONG	0x00000800
+#define WB_BURSTLEN_16LONG	0x00001000
+#define WB_BURSTLEN_32LONG	0x00002000
+
+#define WB_BUSCTL_CONFIG	(WB_CACHEALIGN_8LONG|WB_SKIPLEN_3LONG| \
+					WB_BURSTLEN_8LONG)
+
+/*
+ * Interrupt status bits.
+ */
+#define WB_ISR_TX_OK		0x00000001
+#define WB_ISR_TX_IDLE		0x00000002
+#define WB_ISR_TX_NOBUF		0x00000004
+#define WB_ISR_RX_EARLY		0x00000008
+#define WB_ISR_RX_ERR		0x00000010
+#define WB_ISR_TX_UNDERRUN	0x00000020
+#define WB_ISR_RX_OK		0x00000040
+#define WB_ISR_RX_NOBUF		0x00000080
+#define WB_ISR_RX_IDLE		0x00000100
+#define WB_ISR_TX_EARLY		0x00000400
+#define WB_ISR_TIMER_EXPIRED	0x00000800
+#define WB_ISR_BUS_ERR		0x00002000
+#define WB_ISR_ABNORMAL		0x00008000
+#define WB_ISR_NORMAL		0x00010000
+#define WB_ISR_RX_STATE		0x000E0000
+#define WB_ISR_TX_STATE		0x00700000
+#define WB_ISR_BUSERRTYPE	0x03800000
+
+/*
+ * The RX_STATE and TX_STATE fields are not described anywhere in the
+ * Winbond datasheet, however it appears that the Winbond chip is an
+ * attempt at a DEC 'tulip' clone, hence the ISR register is identical
+ * to that of the tulip chip and we can steal the bit definitions from
+ * the tulip documentation.
+ */
+#define WB_RXSTATE_STOPPED	0x00000000	/* 000 - Stopped */
+#define WB_RXSTATE_FETCH	0x00020000	/* 001 - Fetching descriptor */
+#define WB_RXSTATE_ENDCHECK	0x00040000	/* 010 - check for rx end */
+#define WB_RXSTATE_WAIT		0x00060000	/* 011 - waiting for packet */
+#define WB_RXSTATE_SUSPEND	0x00080000	/* 100 - suspend rx */
+#define WB_RXSTATE_CLOSE	0x000A0000	/* 101 - close tx desc */
+#define WB_RXSTATE_FLUSH	0x000C0000	/* 110 - flush from FIFO */
+#define WB_RXSTATE_DEQUEUE	0x000E0000	/* 111 - dequeue from FIFO */
+
+#define WB_TXSTATE_RESET	0x00000000	/* 000 - reset */
+#define WB_TXSTATE_FETCH	0x00100000	/* 001 - fetching descriptor */
+#define WB_TXSTATE_WAITEND	0x00200000	/* 010 - wait for tx end */
+#define WB_TXSTATE_READING	0x00300000	/* 011 - read and enqueue */
+#define WB_TXSTATE_RSVD		0x00400000	/* 100 - reserved */
+#define WB_TXSTATE_SETUP	0x00500000	/* 101 - setup packet */
+#define WB_TXSTATE_SUSPEND	0x00600000	/* 110 - suspend tx */
+#define WB_TXSTATE_CLOSE	0x00700000	/* 111 - close tx desc */
+
+/*
+ * Network config bits.
+ */
+#define WB_NETCFG_RX_ON		0x00000002
+#define WB_NETCFG_RX_ALLPHYS	0x00000008
+#define WB_NETCFG_RX_MULTI	0x00000010
+#define WB_NETCFG_RX_BROAD	0x00000020
+#define WB_NETCFG_RX_RUNT	0x00000040
+#define WB_NETCFG_RX_ERR	0x00000080
+#define WB_NETCFG_FULLDUPLEX	0x00000200
+#define WB_NETCFG_LOOPBACK	0x00000C00
+#define WB_NETCFG_TX_ON		0x00002000
+#define WB_NETCFG_TX_THRESH	0x001FC000
+#define WB_NETCFG_RX_EARLYTHRSH	0x1FE00000
+#define WB_NETCFG_100MBPS	0x20000000
+#define WB_NETCFG_TX_EARLY_ON	0x40000000
+#define WB_NETCFG_RX_EARLY_ON	0x80000000
+
+/*
+ * The tx threshold can be adjusted in increments of 32 bytes.
+ */
+#define WB_TXTHRESH(x)		((x >> 5) << 14)
+#define WB_TXTHRESH_CHUNK	32
+#define WB_TXTHRESH_INIT	0 /*72*/
+ 
+/*
+ * Interrupt mask bits.
+ */
+#define WB_IMR_TX_OK		0x00000001
+#define WB_IMR_TX_IDLE		0x00000002
+#define WB_IMR_TX_NOBUF		0x00000004
+#define WB_IMR_RX_EARLY		0x00000008
+#define WB_IMR_RX_ERR		0x00000010
+#define WB_IMR_TX_UNDERRUN	0x00000020
+#define WB_IMR_RX_OK		0x00000040
+#define WB_IMR_RX_NOBUF		0x00000080
+#define WB_IMR_RX_IDLE		0x00000100
+#define WB_IMR_TX_EARLY		0x00000400
+#define WB_IMR_TIMER_EXPIRED	0x00000800
+#define WB_IMR_BUS_ERR		0x00002000
+#define WB_IMR_ABNORMAL		0x00008000
+#define WB_IMR_NORMAL		0x00010000
+
+#define WB_INTRS	\
+	(WB_IMR_RX_OK|WB_IMR_TX_OK|WB_IMR_RX_NOBUF|WB_IMR_RX_ERR|	\
+	WB_IMR_TX_NOBUF|WB_IMR_TX_UNDERRUN|WB_IMR_BUS_ERR|		\
+	WB_IMR_ABNORMAL|WB_IMR_NORMAL|WB_IMR_TX_EARLY)
+/*
+ * Serial I/O (EEPROM/ROM) bits.
+ */
+#define WB_SIO_EE_CS		0x00000001	/* EEPROM chip select */
+#define WB_SIO_EE_CLK		0x00000002	/* EEPROM clock */
+#define WB_SIO_EE_DATAIN	0x00000004	/* EEPROM data output */
+#define WB_SIO_EE_DATAOUT	0x00000008	/* EEPROM data input */
+#define WB_SIO_ROMDATA4		0x00000010
+#define WB_SIO_ROMDATA5		0x00000020
+#define WB_SIO_ROMDATA6		0x00000040
+#define WB_SIO_ROMDATA7		0x00000080
+#define WB_SIO_ROMCTL_WRITE	0x00000200
+#define WB_SIO_ROMCTL_READ	0x00000400
+#define WB_SIO_EESEL		0x00000800
+#define WB_SIO_MII_CLK		0x00010000	/* MDIO clock */
+#define WB_SIO_MII_DATAIN	0x00020000	/* MDIO data out */
+#define WB_SIO_MII_DIR		0x00040000	/* MDIO dir */
+#define WB_SIO_MII_DATAOUT	0x00080000	/* MDIO data in */
+
+#define WB_EECMD_WRITE		0x140
+#define WB_EECMD_READ		0x180
+#define WB_EECMD_ERASE		0x1c0
+
+/*
+ * Winbond TX/RX descriptor structure.
+ */
+
+struct wb_desc {
+	u_int32_t		wb_status;
+	u_int32_t		wb_ctl;
+	u_int32_t		wb_ptr1;
+	u_int32_t		wb_ptr2;
+};
+
+#define wb_data		wb_ptr1
+#define wb_next		wb_ptr2
+
+#define WB_RXSTAT_CRCERR	0x00000002
+#define WB_RXSTAT_DRIBBLE	0x00000004
+#define WB_RXSTAT_MIIERR	0x00000008
+#define WB_RXSTAT_LATEEVENT	0x00000040
+#define WB_RXSTAT_GIANT		0x00000080
+#define WB_RXSTAT_LASTFRAG	0x00000100
+#define WB_RXSTAT_FIRSTFRAG	0x00000200
+#define WB_RXSTAT_MULTICAST	0x00000400
+#define WB_RXSTAT_RUNT		0x00000800
+#define WB_RXSTAT_RXTYPE	0x00003000
+#define WB_RXSTAT_RXERR		0x00008000
+#define WB_RXSTAT_RXLEN		0x3FFF0000
+#define WB_RXSTAT_RXCMP		0x40000000
+#define WB_RXSTAT_OWN		0x80000000
+
+#define WB_RXBYTES(x)		((x & WB_RXSTAT_RXLEN) >> 16)
+#define WB_RXSTAT (WB_RXSTAT_FIRSTFRAG|WB_RXSTAT_LASTFRAG|WB_RXSTAT_OWN)
+
+#define WB_RXCTL_BUFLEN1	0x00000FFF
+#define WB_RXCTL_BUFLEN2	0x00FFF000
+#define WB_RXCTL_RLINK		0x01000000
+#define WB_RXCTL_RLAST		0x02000000
+
+#define WB_TXSTAT_DEFER		0x00000001
+#define WB_TXSTAT_UNDERRUN	0x00000002
+#define WB_TXSTAT_COLLCNT	0x00000078
+#define WB_TXSTAT_SQE		0x00000080
+#define WB_TXSTAT_ABORT		0x00000100
+#define WB_TXSTAT_LATECOLL	0x00000200
+#define WB_TXSTAT_NOCARRIER	0x00000400
+#define WB_TXSTAT_CARRLOST	0x00000800
+#define WB_TXSTAT_TXERR		0x00001000
+#define WB_TXSTAT_OWN		0x80000000
+
+#define WB_TXCTL_BUFLEN1	0x000007FF
+#define WB_TXCTL_BUFLEN2	0x003FF800
+#define WB_TXCTL_PAD		0x00800000
+#define WB_TXCTL_TLINK		0x01000000
+#define WB_TXCTL_TLAST		0x02000000
+#define WB_TXCTL_NOCRC		0x08000000
+#define WB_TXCTL_FIRSTFRAG	0x20000000
+#define WB_TXCTL_LASTFRAG	0x40000000
+#define WB_TXCTL_FINT		0x80000000
+
+#define WB_MAXFRAGS		16
+#define WB_RX_LIST_CNT		64
+#define WB_TX_LIST_CNT		64
+#define WB_MIN_FRAMELEN		60
+
+/*
+ * A transmit 'super descriptor' is actually WB_MAXFRAGS regular
+ * descriptors clumped together. The idea here is to emulate the
+ * multi-fragment descriptor layout found in devices such as the
+ * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips.
+ * The advantage to using this scheme is that it avoids buffer copies.
+ * The disadvantage is that there's a certain amount of overhead due
+ * to the fact that each 'fragment' is 16 bytes long. In my tests,
+ * this limits top speed to about 10.5MB/sec. It should be more like
+ * 11.5MB/sec. However, the upshot is that you can achieve better
+ * results on slower machines: a Pentium 200 can pump out packets at
+ * same speed as a PII 400.
+ */
+struct wb_txdesc {
+	struct wb_desc		wb_frag[WB_MAXFRAGS];
+};
+
+#define WB_TXNEXT(x)	x->wb_ptr->wb_frag[x->wb_lastdesc].wb_next
+#define WB_TXSTATUS(x)	x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status
+#define WB_TXCTL(x)	x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl
+#define WB_TXDATA(x)	x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data
+
+#define WB_TXOWN(x)	x->wb_ptr->wb_frag[0].wb_status
+
+#define WB_UNSENT	0x1234
+
+struct wb_list_data {
+	struct wb_desc		wb_rx_list[WB_RX_LIST_CNT];
+	struct wb_txdesc	wb_tx_list[WB_TX_LIST_CNT];
+};
+
+struct wb_chain {
+	struct wb_txdesc	*wb_ptr;
+	struct mbuf		*wb_mbuf;
+	struct wb_chain		*wb_nextdesc;
+	u_int8_t		wb_lastdesc;
+};
+
+struct wb_chain_onefrag {
+	struct wb_desc		*wb_ptr;
+	struct mbuf		*wb_mbuf;
+	struct wb_chain_onefrag	*wb_nextdesc;
+	u_int8_t		wb_rlast;
+};
+
+struct wb_chain_data {
+	u_int8_t		wb_pad[WB_MIN_FRAMELEN];
+	struct wb_chain_onefrag	wb_rx_chain[WB_RX_LIST_CNT];
+	struct wb_chain		wb_tx_chain[WB_TX_LIST_CNT];
+
+	struct wb_chain_onefrag	*wb_rx_head;
+
+	struct wb_chain		*wb_tx_head;
+	struct wb_chain		*wb_tx_tail;
+	struct wb_chain		*wb_tx_free;
+};
+
+struct wb_type {
+	u_int16_t		wb_vid;
+	u_int16_t		wb_did;
+	char			*wb_name;
+};
+
+struct wb_mii_frame {
+	u_int8_t		mii_stdelim;
+	u_int8_t		mii_opcode;
+	u_int8_t		mii_phyaddr;
+	u_int8_t		mii_regaddr;
+	u_int8_t		mii_turnaround;
+	u_int16_t		mii_data;
+};
+
+/*
+ * MII constants
+ */
+#define WB_MII_STARTDELIM	0x01
+#define WB_MII_READOP		0x02
+#define WB_MII_WRITEOP		0x01
+#define WB_MII_TURNAROUND	0x02
+
+#define WB_FLAG_FORCEDELAY	1
+#define WB_FLAG_SCHEDDELAY	2
+#define WB_FLAG_DELAYTIMEO	3	
+
+struct wb_softc {
+	struct device		sc_dev;		/* generic device structure */
+	void *			sc_ih;		/* interrupt handler cookie */
+	struct arpcom		arpcom;		/* interface info */
+	struct ifmedia		ifmedia;	/* media info */
+	bus_space_handle_t	wb_bhandle;
+	bus_space_tag_t		wb_btag;
+	struct wb_type		*wb_info;	/* 3Com adapter info */
+	struct wb_type		*wb_pinfo;	/* phy info */
+	u_int8_t		wb_unit;	/* interface number */
+	u_int8_t		wb_type;
+	u_int8_t		wb_phy_addr;	/* PHY address */
+	u_int8_t		wb_tx_pend;	/* TX pending */
+	u_int8_t		wb_want_auto;
+	u_int8_t		wb_autoneg;
+	u_int16_t		wb_txthresh;
+	caddr_t			wb_ldata_ptr;
+	struct wb_list_data	*wb_ldata;
+	struct wb_chain_data	wb_cdata;
+};
+
+/*
+ * register space access macros
+ */
+#define CSR_WRITE_4(sc, reg, val)	\
+	bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
+#define CSR_WRITE_2(sc, reg, val)	\
+	bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
+#define CSR_WRITE_1(sc, reg, val)	\
+	bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
+
+#define CSR_READ_4(sc, reg)	\
+	bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)
+#define CSR_READ_2(sc, reg)	\
+	bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)
+#define CSR_READ_1(sc, reg)	\
+	bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)
+
+#define WB_TIMEOUT		1000
+
+/*
+ * General constants that are fun to know.
+ *
+ * Winbond PCI vendor ID
+ */
+#define	WB_VENDORID		0x1050
+
+/*
+ * Winbond device IDs.
+ */
+#define	WB_DEVICEID_840F	0x0840
+
+/*
+ * Compex vendor ID.
+ */
+#define CP_VENDORID		0x11F6
+
+/*
+ * Compex device IDs.
+ */
+#define CP_DEVICEID_RL100	0x2011
+
+/*
+ * Texas Instruments PHY identifiers
+ */
+#define TI_PHY_VENDORID		0x4000
+#define TI_PHY_10BT		0x501F
+#define TI_PHY_100VGPMI		0x502F
+
+/*
+ * These ID values are for the NS DP83840A 10/100 PHY
+ */
+#define NS_PHY_VENDORID		0x2000
+#define NS_PHY_83840A		0x5C0F
+
+/*
+ * Level 1 10/100 PHY
+ */
+#define LEVEL1_PHY_VENDORID	0x7810
+#define LEVEL1_PHY_LXT970	0x000F
+
+/*
+ * Intel 82555 10/100 PHY
+ */
+#define INTEL_PHY_VENDORID	0x0A28
+#define INTEL_PHY_82555		0x015F
+
+/*
+ * SEEQ 80220 10/100 PHY
+ */
+#define SEEQ_PHY_VENDORID	0x0016
+#define SEEQ_PHY_80220		0xF83F
+
+
+/*
+ * PCI low memory base and low I/O base register, and
+ * other PCI registers. Note: some are only available on
+ * the 3c905B, in particular those that related to power management.
+ */
+
+#define WB_PCI_VENDOR_ID	0x00
+#define WB_PCI_DEVICE_ID	0x02
+#define WB_PCI_COMMAND		0x04
+#define WB_PCI_STATUS		0x06
+#define WB_PCI_CLASSCODE	0x09
+#define WB_PCI_LATENCY_TIMER	0x0D
+#define WB_PCI_HEADER_TYPE	0x0E
+#define WB_PCI_LOIO		0x10
+#define WB_PCI_LOMEM		0x14
+#define WB_PCI_BIOSROM		0x30
+#define WB_PCI_INTLINE		0x3C
+#define WB_PCI_INTPIN		0x3D
+#define WB_PCI_MINGNT		0x3E
+#define WB_PCI_MINLAT		0x0F
+#define WB_PCI_RESETOPT		0x48
+#define WB_PCI_EEPROM_DATA	0x4C
+
+/* power management registers */
+#define WB_PCI_CAPID		0xDC /* 8 bits */
+#define WB_PCI_NEXTPTR		0xDD /* 8 bits */
+#define WB_PCI_PWRMGMTCAP	0xDE /* 16 bits */
+#define WB_PCI_PWRMGMTCTRL	0xE0 /* 16 bits */
+
+#define WB_PSTATE_MASK		0x0003
+#define WB_PSTATE_D0		0x0000
+#define WB_PSTATE_D1		0x0002
+#define WB_PSTATE_D2		0x0002
+#define WB_PSTATE_D3		0x0003
+#define WB_PME_EN		0x0010
+#define WB_PME_STATUS		0x8000
+
+#define PHY_UNKNOWN		6
+
+#define WB_PHYADDR_MIN		0x00
+#define WB_PHYADDR_MAX		0x1F
+
+#define PHY_BMCR		0x00
+#define PHY_BMSR		0x01
+#define PHY_VENID		0x02
+#define PHY_DEVID		0x03
+#define PHY_ANAR		0x04
+#define PHY_LPAR		0x05
+#define PHY_ANEXP		0x06
+
+#define PHY_ANAR_NEXTPAGE	0x8000
+#define PHY_ANAR_RSVD0		0x4000
+#define PHY_ANAR_TLRFLT		0x2000
+#define PHY_ANAR_RSVD1		0x1000
+#define PHY_ANAR_RSVD2		0x0800
+#define PHY_ANAR_RSVD3		0x0400
+#define PHY_ANAR_100BT4		0x0200
+#define PHY_ANAR_100BTXFULL	0x0100
+#define PHY_ANAR_100BTXHALF	0x0080
+#define PHY_ANAR_10BTFULL	0x0040
+#define PHY_ANAR_10BTHALF	0x0020
+#define PHY_ANAR_PROTO4		0x0010
+#define PHY_ANAR_PROTO3		0x0008
+#define PHY_ANAR_PROTO2		0x0004
+#define PHY_ANAR_PROTO1		0x0002
+#define PHY_ANAR_PROTO0		0x0001
+
+/*
+ * These are the register definitions for the PHY (physical layer
+ * interface chip).
+ */
+/*
+ * PHY BMCR Basic Mode Control Register
+ */
+#define PHY_BMCR_RESET			0x8000
+#define PHY_BMCR_LOOPBK			0x4000
+#define PHY_BMCR_SPEEDSEL		0x2000
+#define PHY_BMCR_AUTONEGENBL		0x1000
+#define PHY_BMCR_RSVD0			0x0800	/* write as zero */
+#define PHY_BMCR_ISOLATE		0x0400
+#define PHY_BMCR_AUTONEGRSTR		0x0200
+#define PHY_BMCR_DUPLEX			0x0100
+#define PHY_BMCR_COLLTEST		0x0080
+#define PHY_BMCR_RSVD1			0x0040	/* write as zero, don't care */
+#define PHY_BMCR_RSVD2			0x0020	/* write as zero, don't care */
+#define PHY_BMCR_RSVD3			0x0010	/* write as zero, don't care */
+#define PHY_BMCR_RSVD4			0x0008	/* write as zero, don't care */
+#define PHY_BMCR_RSVD5			0x0004	/* write as zero, don't care */
+#define PHY_BMCR_RSVD6			0x0002	/* write as zero, don't care */
+#define PHY_BMCR_RSVD7			0x0001	/* write as zero, don't care */
+/*
+ * RESET: 1 == software reset, 0 == normal operation
+ * Resets status and control registers to default values.
+ * Relatches all hardware config values.
+ *
+ * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
+ *
+ * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
+ * Link speed is selected byt his bit or if auto-negotiation if bit
+ * 12 (AUTONEGENBL) is set (in which case the value of this register
+ * is ignored).
+ *
+ * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
+ * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
+ * determine speed and mode. Should be cleared and then set if PHY configured
+ * for no autoneg on startup.
+ *
+ * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
+ *
+ * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
+ *
+ * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
+ *
+ * COLLTEST: 1 == collision test enabled, 0 == normal operation
+ */
+
+/* 
+ * PHY, BMSR Basic Mode Status Register 
+ */   
+#define PHY_BMSR_100BT4			0x8000
+#define PHY_BMSR_100BTXFULL		0x4000
+#define PHY_BMSR_100BTXHALF		0x2000
+#define PHY_BMSR_10BTFULL		0x1000
+#define PHY_BMSR_10BTHALF		0x0800
+#define PHY_BMSR_RSVD1			0x0400	/* write as zero, don't care */
+#define PHY_BMSR_RSVD2			0x0200	/* write as zero, don't care */
+#define PHY_BMSR_RSVD3			0x0100	/* write as zero, don't care */
+#define PHY_BMSR_RSVD4			0x0080	/* write as zero, don't care */
+#define PHY_BMSR_MFPRESUP		0x0040
+#define PHY_BMSR_AUTONEGCOMP		0x0020
+#define PHY_BMSR_REMFAULT		0x0010
+#define PHY_BMSR_CANAUTONEG		0x0008
+#define PHY_BMSR_LINKSTAT		0x0004
+#define PHY_BMSR_JABBER			0x0002
+#define PHY_BMSR_EXTENDED		0x0001
+
+#ifndef ETHER_CRC_LEN
+#define	ETHER_CRC_LEN 4
+#endif