diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2007-04-26 17:04:40 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2007-04-26 17:04:40 +0000 |
| commit | c1ff300c4feff6e9f8c2c5b550f4f1cc02e027bd (patch) | |
| tree | 574d2b9c1f41df63067914f346f133f6a6c9345b | |
| parent | 9d95aa779435c2d53dd82d80f4d001cc35845543 (diff) | |
Be more careful when changing cop0 SR value; or flags in instead of setting
the SR value to them, and correctly propagate the SR to userland via proper
proc0 initialization and cpu_fork() care.
| -rw-r--r-- | sys/arch/mips64/mips64/lcore_float.S | 10 | ||||
| -rw-r--r-- | sys/arch/mips64/mips64/vm_machdep.c | 3 | ||||
| -rw-r--r-- | sys/arch/sgi/sgi/machdep.c | 5 |
3 files changed, 10 insertions, 8 deletions
diff --git a/sys/arch/mips64/mips64/lcore_float.S b/sys/arch/mips64/mips64/lcore_float.S index 05835b0506a..3d727e0d309 100644 --- a/sys/arch/mips64/mips64/lcore_float.S +++ b/sys/arch/mips64/mips64/lcore_float.S @@ -1,4 +1,4 @@ -/* $OpenBSD: lcore_float.S,v 1.11 2005/12/20 07:06:26 miod Exp $ */ +/* $OpenBSD: lcore_float.S,v 1.12 2007/04/26 17:04:32 miod Exp $ */ /* * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -62,7 +62,7 @@ */ LEAF(MipsSwitchFPState, 0) mfc0 t1, COP_0_STATUS_REG # Save old SR - li t0, SR_COP_1_BIT|SR_FR_32 # enable the coprocessor + or t0, t1, SR_COP_1_BIT|SR_FR_32 # enable the coprocessor mtc0 t0, COP_0_STATUS_REG ITLBNOPFIX @@ -166,7 +166,7 @@ END(MipsSwitchFPState) LEAF(MipsSwitchFPState16, 0) mfc0 t1, COP_0_STATUS_REG # Save old SR - li t0, SR_COP_1_BIT # enable the coprocessor + or t0, t1, SR_COP_1_BIT # enable the coprocessor mtc0 t0, COP_0_STATUS_REG ITLBNOPFIX @@ -288,7 +288,7 @@ END(MipsSwitchFPState16) LEAF(MipsSaveCurFPState, 0) PTR_L a0, P_ADDR(a0) # get pointer to pcb for proc mfc0 t1, COP_0_STATUS_REG # Disable interrupts and - li t0, SR_COP_1_BIT|SR_FR_32 # enable the coprocessor + or t0, t1, SR_COP_1_BIT|SR_FR_32 # enable the coprocessor mtc0 t0, COP_0_STATUS_REG ITLBNOPFIX PTR_S zero, machFPCurProcPtr # indicate state has been saved @@ -348,7 +348,7 @@ END(MipsSaveCurFPState) LEAF(MipsSaveCurFPState16, 0) PTR_L a0, P_ADDR(a0) # get pointer to pcb for proc mfc0 t1, COP_0_STATUS_REG # Disable interrupts and - li t0, SR_COP_1_BIT # enable the coprocessor + or t0, t1, SR_COP_1_BIT # enable the coprocessor mtc0 t0, COP_0_STATUS_REG ITLBNOPFIX PTR_S zero, machFPCurProcPtr # indicate state has been saved diff --git a/sys/arch/mips64/mips64/vm_machdep.c b/sys/arch/mips64/mips64/vm_machdep.c index 45ccc5c2383..1add229a76d 100644 --- a/sys/arch/mips64/mips64/vm_machdep.c +++ b/sys/arch/mips64/mips64/vm_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vm_machdep.c,v 1.9 2007/02/24 11:59:47 miod Exp $ */ +/* $OpenBSD: vm_machdep.c,v 1.10 2007/04/26 17:04:33 miod Exp $ */ /* * Copyright (c) 1988 University of Utah. * Copyright (c) 1992, 1993 @@ -98,6 +98,7 @@ cpu_fork(p1, p2, stack, stacksize, func, arg) pcb = &p2->p_addr->u_pcb; *pcb = p1->p_addr->u_pcb; + pcb->pcb_context.val[11] = (register_t)pcb->pcb_regs.sr; pcb->pcb_context.val[10] = (register_t)proc_trampoline; pcb->pcb_context.val[8] = (register_t)(caddr_t)pcb + USPACE - 64; pcb->pcb_context.val[0] = (register_t)func; diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c index a4a91d02845..edfedf57264 100644 --- a/sys/arch/sgi/sgi/machdep.c +++ b/sys/arch/sgi/sgi/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.36 2007/04/26 17:02:40 miod Exp $ */ +/* $OpenBSD: machdep.c,v 1.37 2007/04/26 17:04:39 miod Exp $ */ /* * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -241,7 +241,7 @@ bios_printf("SR=%08x\n", getsr()); /* leave this in for now. need to see sr */ /* R12K O2's must run with DSD on */ switch ((cp0_get_prid() >> 8) & 0xff) { case MIPS_R12000: - setsr(SR_DSD); + setsr(getsr() | SR_DSD); break; } break; @@ -531,6 +531,7 @@ bios_printf("SR=%08x\n", getsr()); /* leave this in for now. need to see sr */ * Turn off bootstrap exception vectors. */ setsr(getsr() & ~SR_BOOT_EXC_VEC); + proc0.p_md.md_regs->sr = getsr(); /* * Clear out the I and D caches. |