Remove the ioc interrupt probe code, the heuristic is correct; origin 300

is still unhappy due to ``interferences'' between the L1 console and the
brick's serial ports, unfortunately.

2 files changed, 4 insertions, 91 deletions

diff --git a/sys/arch/sgi/pci/ioc.c b/sys/arch/sgi/pci/ioc.c
index f8c3574cb46..01a21ea1e39 100644
--- a/sys/arch/sgi/pci/ioc.c
+++ b/sys/arch/sgi/pci/ioc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ioc.c,v 1.16 2009/05/27 19:04:45 miod Exp $	*/
+/*	$OpenBSD: ioc.c,v 1.17 2009/06/21 18:03:15 miod Exp $	*/
 
 /*
  * Copyright (c) 2008 Joel Sing.
@@ -268,7 +268,7 @@ unknown:
 	 *
 	 * Since our pci layer doesn't handle this, we have to compute
 	 * the superio interrupt cookie ourselves, with the help of the
-	 * pci bridge driver. This is ugly, and depends on xbridge knowledge.
+	 * pci bridge driver.
 	 *
 	 * (What the above means is that you should wear peril-sensitive
 	 * sunglasses from now on).
@@ -290,51 +290,6 @@ unknown:
 	 * slot.
 	 */
 	if (dual_irq) {
-		/*
-		 * First, try to get reliable interrupt information
-		 * from the pci bridge.
-		 *
-		 * In order to do this, we trigger the superio interrupt
-		 * and read a magic register in configuration space.
-		 * See the xbridge code for details.
-		 */
-
-		/* enable TX empty interrupt */
-		delay(20 * 1000);	/* let console output drain */
-		bus_space_write_4(sc->sc_memt, sc->sc_memh, IOC3_SIO_IEC, ~0x0);
-		bus_space_write_4(sc->sc_memt, sc->sc_memh, IOC3_SIO_IES,
-		    0x0201);
-
-		/* read pseudo interrupt register */
-		data = pci_conf_read(pa->pa_pc, pa->pa_tag,
-		    PCI_INTERRUPT_REG + 4);
-
-		/* disable interrupt again */
-		bus_space_write_4(sc->sc_memt, sc->sc_memh, IOC3_SIO_IEC,
-		    0x0201);
-
-		if (data != 0) {
-			/*
-			 * If the interrupt has been received as the
-			 * regular PCI interrupt, then we probably don't
-			 * have separate interrupts.
-			 */
-			if (PCI_INTERRUPT_LINE(data) == pa->pa_intrline)
-				goto single;
-
-			pa->pa_intrline = PCI_INTERRUPT_LINE(data);
-			pa->pa_rawintrpin = pa->pa_intrpin =
-			    PCI_INTERRUPT_PIN(data);
-
-			if (pci_intr_map(pa, &ih2) == 0)
-				goto establish;
-		}
-
-		/*
-		 * If there was no bridge hint or it did not work, use the
-		 * heuristic of picking the lowest free slot.
-		 */
-
 		for (dev = 0;
 		    dev < pci_bus_maxdevs(pa->pa_pc, pa->pa_bus); dev++) {
 			pcitag_t tag;
@@ -367,7 +322,6 @@ unknown:
 		 * situation, but it's probably safe to revert to
 		 * a shared, single interrupt.
 		 */
-single:
 		shared_handler = 1;
 		dual_irq = 0;
 	}
diff --git a/sys/arch/sgi/xbow/xbridge.c b/sys/arch/sgi/xbow/xbridge.c
index 5d8f5c729c0..804ac7fd6ce 100644
--- a/sys/arch/sgi/xbow/xbridge.c
+++ b/sys/arch/sgi/xbow/xbridge.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: xbridge.c,v 1.26 2009/06/13 21:48:03 miod Exp $	*/
+/*	$OpenBSD: xbridge.c,v 1.27 2009/06/21 18:03:16 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009  Miodrag Vallat.
@@ -81,7 +81,6 @@ struct xbridge_softc {
 	struct xbridge_intr	*sc_intr[BRIDGE_NINTRS];
 
 	pcireg_t	sc_devices[BRIDGE_NSLOTS];
-	pcireg_t	sc_ier_ignore;
 
 	struct mutex	sc_atemtx;
 	uint		sc_atecnt;
@@ -414,7 +413,6 @@ xbridge_conf_read(void *cookie, pcitag_t tag, int offset)
 {
 	struct xbridge_softc *sc = cookie;
 	pcireg_t data;
-	uint32_t ier;
 	int bus, dev, fn;
 	paddr_t pa;
 	int skip;
@@ -462,41 +460,6 @@ xbridge_conf_read(void *cookie, pcitag_t tag, int offset)
 			    (dev << PCI_INTERRUPT_LINE_SHIFT);
 			skip = 1;
 			break;
-		case PCI_INTERRUPT_REG + 4:
-			/*
-			 * This is a kluge to help the IOC driver figure
-			 * out which second interrupt line it uses.
-			 *
-			 * The ioc driver will attempt to trigger that
-			 * interrupt, and then read that sort-of second
-			 * interrupt register.  Here we check the pending
-			 * interrupts, and see if a bit has changed.
-			 *
-			 * Unfortunately, this does not work on all
-			 * platforms (e.g. IP30).  The ioc driver falls
-			 * back to heuristics in that case.
-			 */
-
-			ier = bus_space_read_4(sc->sc_iot, sc->sc_regh,
-			    BRIDGE_IER) & 0xff;
-			ier &= ~sc->sc_ier_ignore;
-			sc->sc_ier_ignore |= ier;
-
-			/* we expect only one bit to trigger */
-			if (ier != 0 && (ier & (ier - 1)) != 0)
-				ier = 0;
-
-			if (ier != 0) {
-				/* compute interrupt line */
-				for (data = 0; ier != 1; ier >>= 1, data++) ;
-
-				data = (PCI_INTERRUPT_PIN_A <<
-				    PCI_INTERRUPT_PIN_SHIFT) |
-				    (data << PCI_INTERRUPT_LINE_SHIFT);
-			} else
-				data = 0;
-			skip = 1;
-			break;
 		default:
 			/* These registers are not implemented. */
 			data = 0;
@@ -701,7 +664,6 @@ xbridge_intr_establish(void *cookie, pci_intr_handle_t ih, int level,
 		}
 
 		sc->sc_intrbit[intrbit] = intrsrc;
-		sc->sc_ier_ignore |= 1 << intrbit;
 	}
 
 	xi->xi_bridge = sc;
@@ -1552,7 +1514,7 @@ xbridge_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment,
     bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
     int flags)
 {
-	vaddr_t low, high;
+	paddr_t low, high;
 
 	/*
 	 * Limit bus_dma'able memory to the first 2GB of physical memory.
@@ -1687,9 +1649,6 @@ xbridge_setup(struct xbridge_softc *sc)
 
 	for (i = 0; i < BRIDGE_NINTRS; i++)
 		sc->sc_intrbit[i] = -1;
-
-	sc->sc_ier_ignore = bus_space_read_4(sc->sc_iot, sc->sc_regh,
-	    BRIDGE_IER) & 0xff;
 }
 
 /*