With the splx() changes, it is no longer necessary to remember which interrupt

sources were masked and saved in ci_ipending, as splx() will unmask what needs
to be unmasked anyway. ci_ipending only now needs to store pending soft
interrupts, so rename it to ci_softpending.

7 files changed, 15 insertions, 25 deletions

diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index 119b428aa1d..ad44f2270a2 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.39 2009/10/22 20:05:26 miod Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.40 2009/10/22 20:59:22 miod Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -375,7 +375,7 @@ struct cpu_info {
 	cpuid_t          ci_cpuid;              /* our CPU ID */
 	uint32_t	 ci_randseed;		/* per cpu random seed */
 	uint32_t	 ci_cpl;
-	uint32_t	 ci_ipending;
+	uint32_t	 ci_softpending;	/* pending soft interrupts */
 #ifdef MULTIPROCESSOR
 	u_long           ci_flags;		/* flags; see below */
 #endif
diff --git a/sys/arch/mips64/mips64/interrupt.c b/sys/arch/mips64/mips64/interrupt.c
index e7c6491383d..aa94dd46b3b 100644
--- a/sys/arch/mips64/mips64/interrupt.c
+++ b/sys/arch/mips64/mips64/interrupt.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: interrupt.c,v 1.47 2009/10/22 20:39:16 miod Exp $ */
+/*	$OpenBSD: interrupt.c,v 1.48 2009/10/22 20:59:24 miod Exp $ */
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -164,7 +164,7 @@ interrupt(struct trap_frame *trapframe)
 #endif
 
 	xcpl = splsoft();
-	if ((ci->ci_ipending & SINT_ALLMASK) & ~xcpl) {
+	if (ci->ci_softpending & ~xcpl) {
 		dosoftint(xcpl);
 	}
 
diff --git a/sys/arch/mips64/mips64/softintr.c b/sys/arch/mips64/mips64/softintr.c
index 764df17a3ed..748657f0ccd 100644
--- a/sys/arch/mips64/mips64/softintr.c
+++ b/sys/arch/mips64/mips64/softintr.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: softintr.c,v 1.3 2009/10/22 20:05:27 miod Exp $	*/
+/*	$OpenBSD: softintr.c,v 1.4 2009/10/22 20:59:24 miod Exp $	*/
 /*	$NetBSD: softintr.c,v 1.2 2003/07/15 00:24:39 lukem Exp $	*/
 
 /*
@@ -175,7 +175,7 @@ softintr_schedule(void *arg)
 	if (sih->sih_pending == 0) {
 		TAILQ_INSERT_TAIL(&siq->siq_list, sih, sih_list);
 		sih->sih_pending = 1;
-		atomic_setbits_int(&ci->ci_ipending, SINTMASK(siq->siq_si));
+		atomic_setbits_int(&ci->ci_softpending, SINTMASK(siq->siq_si));
 	}
 	mtx_leave(&siq->siq_mtx);
 }
@@ -205,8 +205,8 @@ dosoftint(uint32_t xcpl)
 	struct cpu_info *ci = curcpu();
 	int sir, q, mask;
 
-	while ((sir = (ci->ci_ipending & SINT_ALLMASK & ~xcpl)) != 0) {
-		atomic_clearbits_int(&ci->ci_ipending, sir);
+	while ((sir = (ci->ci_softpending & ~xcpl)) != 0) {
+		atomic_clearbits_int(&ci->ci_softpending, sir);
 
 		for (q = SI_NQUEUES - 1; q >= 0; q--) {
 			mask = SINTMASK(q);
diff --git a/sys/arch/sgi/localbus/macebus.c b/sys/arch/sgi/localbus/macebus.c
index 6bf83e7c4f4..39ff5fdc706 100644
--- a/sys/arch/sgi/localbus/macebus.c
+++ b/sys/arch/sgi/localbus/macebus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: macebus.c,v 1.49 2009/10/22 20:51:08 miod Exp $ */
+/*	$OpenBSD: macebus.c,v 1.50 2009/10/22 20:59:24 miod Exp $ */
 
 /*
  * Copyright (c) 2000-2004 Opsycon AB  (www.opsycon.se)
@@ -604,7 +604,7 @@ macebus_splx(int newcpl)
 	__asm__ (" sync\n .set reorder\n");
 	hw_setintrmask(newcpl);
 	/* If we still have softints pending trigger processing. */
-	if (ci->ci_ipending & SINT_ALLMASK & ~newcpl)
+	if (ci->ci_softpending & ~newcpl)
 		setsoftintr0();
 }
 
@@ -632,16 +632,13 @@ macebus_iointr(uint32_t hwpend, struct trap_frame *cf)
 
 	/* Mask off masked interrupts and save them as pending. */
 	if (intstat & cf->cpl) {
-		atomic_setbits_int(&ci->ci_ipending, intstat & cf->cpl);
 		mask = bus_space_read_8(&crimebus_tag, crime_h, CRIME_INT_MASK);
-		mask &= ~ci->ci_ipending;
 		bus_space_write_8(&crimebus_tag, crime_h, CRIME_INT_MASK, mask);
 		caught++;
 	}
 
 	/* Scan all unmasked. Scan the first 16 for now. */
 	pending = intstat & ~cf->cpl;
-	atomic_clearbits_int(&ci->ci_ipending, pending);
 
 	for (v = 0, vm = 1; pending != 0 && v < 16 ; v++, vm <<= 1) {
 		if (pending & vm) {
diff --git a/sys/arch/sgi/sgi/genassym.cf b/sys/arch/sgi/sgi/genassym.cf
index 35c17485e08..d619bccd0a6 100644
--- a/sys/arch/sgi/sgi/genassym.cf
+++ b/sys/arch/sgi/sgi/genassym.cf
@@ -1,4 +1,4 @@
-#	$OpenBSD: genassym.cf,v 1.15 2009/10/07 08:35:47 syuu Exp $
+#	$OpenBSD: genassym.cf,v 1.16 2009/10/22 20:59:24 miod Exp $
 #
 # Copyright (c) 1997 Per Fogelstrom / Opsycon AB
 #
@@ -59,7 +59,6 @@ struct	cpu_info
 member	ci_curproc
 member	ci_curprocpaddr
 member	ci_cpl
-member	ci_ipending
 
 export	VM_MIN_KERNEL_ADDRESS
 export	SIGFPE
diff --git a/sys/arch/sgi/sgi/ip27_machdep.c b/sys/arch/sgi/sgi/ip27_machdep.c
index f98901546d1..77d547a8758 100644
--- a/sys/arch/sgi/sgi/ip27_machdep.c
+++ b/sys/arch/sgi/sgi/ip27_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip27_machdep.c,v 1.26 2009/10/22 20:39:17 miod Exp $	*/
+/*	$OpenBSD: ip27_machdep.c,v 1.27 2009/10/22 20:59:24 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009 Miodrag Vallat.
@@ -729,7 +729,7 @@ ip27_hub_splx(int newcpl)
 	if (CPU_IS_PRIMARY(ci))
 		hw_setintrmask(newcpl);
 	/* If we still have softints pending trigger processing. */
-	if (ci->ci_ipending & SINT_ALLMASK & ~newcpl)
+	if (ci->ci_softpending & ~newcpl)
 		setsoftintr0();
 }
 
@@ -762,7 +762,6 @@ ip27_hub_intr_handler(uint32_t hwpend, struct trap_frame *frame)
 	 * If interrupts are spl-masked, mark them as pending only.
 	 */
 	if ((mask = isr & frame->cpl) != 0) {
-		atomic_setbits_int(&ci->ci_ipending, mask);
 		isr &= ~mask;
 		imr &= ~mask;
 	}
@@ -771,8 +770,6 @@ ip27_hub_intr_handler(uint32_t hwpend, struct trap_frame *frame)
 	 * Now process unmasked interrupts.
 	 */
 	if (isr != 0) {
-		atomic_clearbits_int(&ci->ci_ipending, isr);
-
 		__asm__ (" .set noreorder\n");
 		icpl = ci->ci_cpl;
 		__asm__ (" sync\n .set reorder\n");
diff --git a/sys/arch/sgi/xbow/xheart.c b/sys/arch/sgi/xbow/xheart.c
index 65b05c9d10f..34ba7f2b72d 100644
--- a/sys/arch/sgi/xbow/xheart.c
+++ b/sys/arch/sgi/xbow/xheart.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: xheart.c,v 1.11 2009/10/22 20:39:17 miod Exp $	*/
+/*	$OpenBSD: xheart.c,v 1.12 2009/10/22 20:59:24 miod Exp $	*/
 
 /*
  * Copyright (c) 2008 Miodrag Vallat.
@@ -401,7 +401,7 @@ xheart_splx(int newcpl)
 	if (CPU_IS_PRIMARY(ci))
 		hw_setintrmask(newcpl);
 	/* If we still have softints pending trigger processing. */
-	if (ci->ci_ipending & SINT_ALLMASK & ~newcpl)
+	if (ci->ci_softpending & ~newcpl)
 		setsoftintr0();
 }
 
@@ -434,7 +434,6 @@ xheart_intr_handler(uint32_t hwpend, struct trap_frame *frame)
 	 * If interrupts are spl-masked, mark them as pending only.
 	 */
 	if ((mask = isr & frame->cpl) != 0) {
-		atomic_setbits_int(&ci->ci_ipending, mask);
 		isr &= ~mask;
 	}
 
@@ -442,8 +441,6 @@ xheart_intr_handler(uint32_t hwpend, struct trap_frame *frame)
 	 * Now process unmasked interrupts.
 	 */
 	if (isr != 0) {
-		atomic_clearbits_int(&ci->ci_ipending, isr);
-
 		__asm__ (" .set noreorder\n");
 		icpl = ci->ci_cpl;
 		__asm__ (" sync\n .set reorder\n");