diff options
| author | Mike Belopuhov <mikeb@cvs.openbsd.org> | 2012-10-25 17:24:12 +0000 |
|---|---|---|
| committer | Mike Belopuhov <mikeb@cvs.openbsd.org> | 2012-10-25 17:24:12 +0000 |
| commit | 19aeecda5fabd6dc728259fa232b4e3a4451c146 (patch) | |
| tree | f61216c40de4a05543990a0433e2340faea2047c | |
| parent | 4d40c4e444a0b1996c6b021860aa5722a2216076 (diff) | |
cleanup interrupt register defines
| -rw-r--r-- | sys/dev/pci/if_oce.c | 10 | ||||
| -rw-r--r-- | sys/dev/pci/ocereg.h | 9 |
2 files changed, 9 insertions, 10 deletions
diff --git a/sys/dev/pci/if_oce.c b/sys/dev/pci/if_oce.c index 265842cf91c..79d9812f1f6 100644 --- a/sys/dev/pci/if_oce.c +++ b/sys/dev/pci/if_oce.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_oce.c,v 1.24 2012/10/25 16:47:30 mikeb Exp $ */ +/* $OpenBSD: if_oce.c,v 1.25 2012/10/25 17:24:11 mikeb Exp $ */ /* * Copyright (c) 2012 Mike Belopuhov @@ -619,9 +619,9 @@ oce_intr_enable(struct oce_softc *sc) { uint32_t reg; - reg = OCE_READ_REG32(sc, cfg, PCICFG_INTR_CTRL); + reg = OCE_READ_REG32(sc, cfg, PCI_INTR_CTRL); reg |= HOSTINTR_MASK; - OCE_WRITE_REG32(sc, cfg, PCICFG_INTR_CTRL, reg); + OCE_WRITE_REG32(sc, cfg, PCI_INTR_CTRL, reg); } void @@ -629,9 +629,9 @@ oce_intr_disable(struct oce_softc *sc) { uint32_t reg; - reg = OCE_READ_REG32(sc, cfg, PCICFG_INTR_CTRL); + reg = OCE_READ_REG32(sc, cfg, PCI_INTR_CTRL); reg &= ~HOSTINTR_MASK; - OCE_WRITE_REG32(sc, cfg, PCICFG_INTR_CTRL, reg); + OCE_WRITE_REG32(sc, cfg, PCI_INTR_CTRL, reg); } void diff --git a/sys/dev/pci/ocereg.h b/sys/dev/pci/ocereg.h index 992da6c3acc..c03475abebf 100644 --- a/sys/dev/pci/ocereg.h +++ b/sys/dev/pci/ocereg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: ocereg.h,v 1.5 2012/10/25 16:47:30 mikeb Exp $ */ +/* $OpenBSD: ocereg.h,v 1.6 2012/10/25 17:24:11 mikeb Exp $ */ /*- * Copyright (C) 2012 Emulex @@ -51,10 +51,9 @@ #define MPU_EP_SEMAPHORE_XE201 0x400 #define MPU_EP_SEMAPHORE(sc) \ ((IS_BE(sc)) ? MPU_EP_SEMAPHORE_BE3 : MPU_EP_SEMAPHORE_XE201) -#define PCICFG_INTR_CTRL 0xfc -#define HOSTINTR_MASK (1 << 29) -#define HOSTINTR_PFUNC_SHIFT 26 -#define HOSTINTR_PFUNC_MASK 7 + +#define PCI_INTR_CTRL 0xfc +#define HOSTINTR_MASK (1<<29) /* POST status reg struct */ #define POST_STAGE_POWER_ON_RESET 0x00 |