Drivers for the FORCE CPU-5V:

o fga5000 vme-sbus bridge
o system config registers
o flash memory
and daadio VME board driver

16 files changed, 2357 insertions, 15 deletions

diff --git a/sys/arch/sparc/conf/files.sparc b/sys/arch/sparc/conf/files.sparc
index e47bfc2e4d8..c82567d2d20 100644
--- a/sys/arch/sparc/conf/files.sparc
+++ b/sys/arch/sparc/conf/files.sparc
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.sparc,v 1.30 1999/06/06 04:48:24 jason Exp $
+#	$OpenBSD: files.sparc,v 1.31 1999/07/23 19:11:23 jason Exp $
 #	$NetBSD: files.sparc,v 1.44 1997/08/31 21:29:16 pk Exp $
 
 # @(#)files.sparc	8.1 (Berkeley) 7/19/93
@@ -303,7 +303,28 @@ file	arch/sparc/dev/spif.c		spif | stty | sbpp needs-flag
 
 device bpp {}
 attach bpp at sbus
-file    arch/sparc/dev/bpp.c          bpp needs-flag
+file    arch/sparc/dev/bpp.c		bpp needs-flag
 
 attach xbox at sbus
 file	arch/sparc/dev/xbox.c		xbox
+
+# sysconfig registers on Force CPU-5V
+device scf {}
+attach scf at mainbus
+file	arch/sparc/dev/scf.c		scf needs-flag
+
+# flash memory on Force CPU-5V
+device flash {}
+attach flash at obio
+file	arch/sparc/dev/flash.c		flash needs-flag
+
+# VME/SBus bridge on Force CPU-5V
+device fga {}
+attach fga at iommu
+device fvme { [addr = -1], [level = -1], [vect = -1] }
+attach fvme at fga
+file	arch/sparc/dev/fga.c		fga needs-flag
+
+device daadio {}
+attach daadio at fvme
+file	arch/sparc/dev/daadio.c		daadio
diff --git a/sys/arch/sparc/dev/daadio.c b/sys/arch/sparc/dev/daadio.c
new file mode 100644
index 00000000000..6ff4ba3757e
--- /dev/null
+++ b/sys/arch/sparc/dev/daadio.c
@@ -0,0 +1,170 @@
+/*	$OpenBSD: daadio.c,v 1.1 1999/07/23 19:11:24 jason Exp $	*/
+
+/*
+ * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * This software was developed by Jason L. Wright under contract with
+ * RTMX Incorporated (http://www.rtmx.com).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Jason L. Wright for
+ *	RTMX Incorporated.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the MATRIX Corporation MD-DAADIO digital->analog,
+ * analog->digial, parallel i/o VME board.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/errno.h>
+#include <sys/ioctl.h>
+#include <sys/syslog.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <machine/autoconf.h>
+#include <sparc/cpu.h>
+#include <sparc/sparc/cpuvar.h>
+#include <sparc/dev/sbusvar.h>
+#include <sparc/dev/dmareg.h>	/* for SBUS_BURST_* */
+
+#include <sparc/dev/fgareg.h>
+#include <sparc/dev/fgavar.h>
+#include <sparc/dev/daadioreg.h>
+
+int	daadiomatch	__P((struct device *, void *, void *));
+void	daadioattach	__P((struct device *, struct device *, void *));
+int	daadiointr	__P((void *));
+
+struct daadio_softc {
+	struct		device sc_dv;		/* base device */
+	struct		daadioregs *sc_regs;	/* registers */
+	struct		intrhand sc_ih;		/* interrupt vectoring */
+	u_int8_t	sc_ier;			/* software copy of ier */
+};
+
+struct cfattach daadio_ca = {
+	sizeof (struct daadio_softc), daadiomatch, daadioattach
+};
+
+struct cfdriver daadio_cd = {
+	NULL, "daadio", DV_DULL
+};
+
+void	daadio_ier_setbit __P((struct daadio_softc *, u_int8_t));
+void	daadio_ier_clearbit __P((struct daadio_softc *, u_int8_t));
+
+int
+daadiomatch(parent, vcf, aux)
+	struct device *parent;
+	void *vcf, *aux;
+{
+	struct cfdata *cf = vcf;
+	struct confargs *ca = aux;
+	struct daadioregs *regs;
+
+	if (ca->ca_bustype != BUS_FGA_A16D16)
+		return (0);
+
+	if (strcmp(ca->ca_ra.ra_name, cf->cf_driver->cd_name))
+		return (0);
+
+	if (ca->ca_ra.ra_reg[0].rr_len < sizeof(struct daadioboard))
+		return (0);
+
+	regs = ca->ca_ra.ra_reg[0].rr_paddr;
+	if (probeget((caddr_t)&regs->sid, 1) != -1)
+		return (1);
+
+	return (0);
+}
+
+void    
+daadioattach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct confargs *ca = aux;
+	struct daadio_softc *sc = (struct daadio_softc *)self;
+
+	sc->sc_regs = mapiodev(&(ca->ca_ra.ra_reg[0]), 0,
+	    sizeof(struct daadioboard));
+
+	sc->sc_regs->pio_pattern = sc->sc_regs->pio_porta;
+	sc->sc_regs->sid = ca->ca_ra.ra_intr[0].int_vec;
+	sc->sc_regs->gvrilr &= ~ILR_IRQ_MASK;
+	sc->sc_regs->gvrilr |= (ca->ca_ra.ra_intr[0].int_pri << ILR_IRQ_SHIFT)
+	    & ILR_IRQ_MASK;
+	sc->sc_ih.ih_fun = daadiointr;
+	sc->sc_ih.ih_arg = sc;
+	fvmeintrestablish(parent, ca->ca_ra.ra_intr[0].int_vec,
+	    ca->ca_ra.ra_intr[0].int_pri, &sc->sc_ih);
+	daadio_ier_setbit(sc, IER_PIOEVENT);
+
+	printf(": level %d vec 0x%x\n",
+	    ca->ca_ra.ra_intr[0].int_pri, ca->ca_ra.ra_intr[0].int_vec);
+}
+
+int
+daadiointr(vsc)
+	void *vsc;
+{
+	struct daadio_softc *sc = vsc;
+	struct daadioregs *regs = sc->sc_regs;
+	u_int8_t val;
+	int r = 0;
+
+	if (regs->isr & ISR_PIOEVENT) {
+		val = regs->pio_porta;
+		printf("pio value: %x\n", val);
+		r |= 1;
+		regs->pio_pattern = val;
+	}
+
+	return (r);
+}
+
+void
+daadio_ier_setbit(sc, v)
+	struct daadio_softc *sc;
+	u_int8_t v;
+{
+	sc->sc_ier |= v;
+	sc->sc_regs->ier = sc->sc_ier;
+}
+
+void
+daadio_ier_clearbit(sc, v)
+	struct daadio_softc *sc;
+	u_int8_t v;
+{
+	sc->sc_ier &= ~v;
+	sc->sc_regs->ier = sc->sc_ier;
+}
diff --git a/sys/arch/sparc/dev/daadioreg.h b/sys/arch/sparc/dev/daadioreg.h
new file mode 100644
index 00000000000..c8bf270e733
--- /dev/null
+++ b/sys/arch/sparc/dev/daadioreg.h
@@ -0,0 +1,131 @@
+/*	$OpenBSD: daadioreg.h,v 1.1 1999/07/23 19:11:24 jason Exp $	*/
+
+/*
+ * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * This software was developed by Jason L. Wright under contract with
+ * RTMX Incorporated (http://www.rtmx.com).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Jason L. Wright for
+ *	RTMX Incorporated.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Register definitions for Matrix Corporation MD-DAADIO VME
+ * digital/analog, analog/digitial, parallel i/o board.
+ * Definitions from "MD-DAADIO User's Manual" revision B.3
+ */
+
+struct daadioregs {
+	volatile u_int8_t	_unused0[32];	/* reserved */
+	/* PIO module: 0x20-0x27 */
+	volatile u_int8_t	pio_portb;	/* port b */
+	volatile u_int8_t	pio_porta;	/* port a */
+	volatile u_int8_t	pio_portd;	/* port d */
+	volatile u_int8_t	pio_portc;	/* port c */
+	volatile u_int8_t	pio_portf;	/* port f */
+	volatile u_int8_t	pio_porte;	/* port e */
+	volatile u_int8_t	_unused1[1];	/* reserved */
+	volatile u_int8_t	pio_oc;		/* output control */
+
+	volatile u_int8_t	_unused2[24];	/* reserved */
+
+	/* DAC module: 0x40-0x4f */
+	volatile u_int16_t	dac_channel[8];	/* dac channels 0-7 */
+
+	volatile u_int8_t	_unused3[16];	/* reserved */
+
+	/* Miscellaneous: 0x60-0x69 */
+	volatile u_int8_t	_unused4;	/* reserved */
+	volatile u_int8_t	gvrilr;		/* gain value/irq level */
+	volatile u_int8_t	_unused5;	/* reserved */
+	volatile u_int8_t	ier;		/* irq enable (wo) */
+	volatile u_int8_t	_unused6;	/* reserved */
+	volatile u_int8_t	pio_pattern;	/* pio pattern */
+	volatile u_int8_t	_unused7;	/* reserved */
+	volatile u_int8_t	sid;		/* status/id */
+	volatile u_int8_t	_unused8;	/* reserved */
+	volatile u_int8_t	isr;		/* interrupt status */
+
+	volatile u_int8_t	_unused9[22];	/* reserved */
+
+	/* ADC module: 0x80-0xff */
+	volatile u_int16_t	adc12bit[32];	/* adc 12 bit channels 0-31 */
+	volatile u_int16_t	adc8bit[32];	/* adc 8 bit channels 0-31 */
+};
+
+/*
+ * The board occupies the space from 0 - 3ff (from some board configured
+ * offset). There are four register mappings (the last three are redundant
+ * mappings of the first)
+ */
+struct daadioboard {
+	struct daadioregs	regs0;
+	struct daadioregs	regs1;
+	struct daadioregs	regs2;
+	struct daadioregs	regs3;
+};
+
+/* gain value register/irq level register (gvr/ilr) */
+#define ILR_TRIGGER		0x80		/* 0=internal,1=external */
+#define	ILR_IRQ_MASK		0x70		/* IRQ level */
+#define	ILR_IRQ_SHIFT		4		/* irq shift to/from lsbits */
+#define	ILR_ADC_GAINMASK	0x07		/* adc gain select bits */
+#define	ILR_ADC_GAIN1		0x00		/* 1x adc gain */
+#define	ILR_ADC_GAIN2		0x01		/* 2x adc gain */
+#define	ILR_ADC_GAIN4		0x02		/* 4x adc gain */
+#define	ILR_ADC_GAIN8		0x03		/* 8x adc gain */
+#define	ILR_ADC_GAIN16		0x04		/* 16x adc gain */
+
+/* interrupt enable register (ier): WRITE ONLY */
+#define	IER_MASK		0x07		/* interrupt bits */
+#define	IER_PIPELINE		0x04		/* adc pipeline empty */
+#define	IER_CONVERSION		0x02		/* adc conversion done */
+#define	IER_PIOEVENT		0x01		/* pio event triggered */
+
+/* interrupt status register (isr) */
+#define	ISR_MASK		0x07		/* interrupt bits */
+#define	ISR_PIPELINE		0x04		/* adc pipeline empty */
+#define	ISR_CONVERSION		0x02		/* adc conversion done */
+#define	ISR_PIOEVENT		0x01		/* pio event triggered */
+
+/* analog/digital data register */
+#define	ADC_IV			0x1000		/* invalid (out of range) */
+#define	ADC_PR			0x2000		/* pipeline empty */
+#define	ADC_DR			0x4000		/* data ready (valid) */
+#define	ADC_OW			0x8000		/* data overwritten */
+#define	ADC_DATAMASK		0x0fff		/* the actual data */
+
+/* output control register (pio_oc) */
+#define	PIOC_OCA		0x01		/* enable port A output */
+#define	PIOC_OCB		0x02		/* enable port B output */
+#define	PIOC_OCC		0x03		/* enable port C output */
+#define	PIOC_OCD		0x04		/* enable port D output */
+#define	PIOC_OCE		0x05		/* enable port E output */
+#define	PIOC_OCF		0x06		/* enable port F output */
+
diff --git a/sys/arch/sparc/dev/fga.c b/sys/arch/sparc/dev/fga.c
new file mode 100644
index 00000000000..b6d88026ce5
--- /dev/null
+++ b/sys/arch/sparc/dev/fga.c
@@ -0,0 +1,815 @@
+/*	$OpenBSD: fga.c,v 1.1 1999/07/23 19:11:25 jason Exp $	*/
+
+/*
+ * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * This software was developed by Jason L. Wright under contract with
+ * RTMX Incorporated (http://www.rtmx.com).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Jason L. Wright for
+ *	RTMX Incorporated.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the Force Gate Array 5000 (VME/SBus bridge) found
+ * on FORCE CPU-5V boards.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/errno.h>
+#include <sys/ioctl.h>
+#include <sys/syslog.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <vm/vm.h>
+#include <machine/pmap.h>
+
+#include <machine/autoconf.h>
+#include <sparc/cpu.h>
+#include <sparc/sparc/cpuvar.h>
+#include <sparc/dev/sbusvar.h>
+#include <sparc/dev/dmareg.h>	/* for SBUS_BURST_* */
+
+#include <sparc/dev/fgareg.h>
+#include <sparc/dev/fgavar.h>
+#include <sparc/dev/fgaio.h>
+#include <sparc/dev/daadioreg.h>
+
+int	fgamatch	__P((struct device *, void *, void *));
+void	fgaattach	__P((struct device *, struct device *, void *));
+int	fvmematch	__P((struct device *, void *, void *));
+void	fvmeattach	__P((struct device *, struct device *, void *));
+int	fgaprint	__P((void *, const char *));
+int	fvmeprint	__P((void *, const char *));
+int	fvmescan	__P((struct device *parent, void *, void *));
+
+struct fga_softc {
+	struct		device sc_dev;		/* base device */
+	int		sc_node;		/* prom node */
+	struct		fga_regs *sc_regs;	/* registers */
+	struct		intrhand sc_ih1;	/* level 1 handler */
+	struct		intrhand sc_ih2;	/* level 2 handler */
+	struct		intrhand sc_ih3;	/* level 3 handler */
+	struct		intrhand sc_ih4;	/* level 4 handler */
+	struct		intrhand sc_ih5;	/* level 5 handler */
+	struct		intrhand sc_ih6;	/* level 6 handler */
+	struct		intrhand sc_ih7;	/* level 7 handler */
+	struct		intrhand **sc_vmevec;	/* vectored handlers */
+#ifdef DDB
+	int		sc_abort;		/* abort switch enabled? */
+#endif
+	int		sc_nrange;		/* number of sbus ranges */
+	struct		rom_range *sc_range;	/* sbus range data */
+	u_int8_t	sc_established;		/* which hw intrs installed */
+};
+
+int	fgaopen		__P((dev_t, int, int, struct proc *));
+int	fgaclose	__P((dev_t, int, int, struct proc *));
+int	fgaioctl	__P((dev_t, u_long, caddr_t, int, struct proc *));
+
+int	fga_vmerangemap	__P((struct fga_softc *, u_int32_t, u_int32_t,
+    int, int, u_int32_t, struct confargs *));
+int	fga_intr_establish __P((struct fga_softc *, int, int,
+    struct intrhand *));
+int	fga_hwintr_establish __P((struct fga_softc *, u_int8_t));
+
+int	fga_hwintr1 __P((void *));
+int	fga_hwintr2 __P((void *));
+int	fga_hwintr3 __P((void *));
+int	fga_hwintr4 __P((void *));
+int	fga_hwintr5 __P((void *));
+int	fga_hwintr6 __P((void *));
+int	fga_hwintr7 __P((void *));
+int	fga_intrvec __P((struct fga_softc *, int));
+
+struct cfattach fga_ca = {
+	sizeof (struct fga_softc), fgamatch, fgaattach
+};
+
+struct cfdriver fga_cd = {
+	NULL, "fga", DV_DULL
+};
+
+struct fvme_softc {
+	struct		device sc_dv;
+	u_int32_t	sc_vmeoffset;		/* vme range offset */
+	u_int32_t	sc_len;			/* length of range */
+	u_int32_t	sc_sbusoffset;		/* sbus phys address */
+	u_int32_t	sc_type;		/* amcode type */
+};
+
+struct cfattach fvme_ca = {
+	sizeof (struct fvme_softc), fvmematch, fvmeattach
+};
+
+struct cfdriver fvme_cd = {
+	NULL, "fvme", DV_DULL
+};
+
+int
+fgamatch(parent, vcf, aux)
+	struct device *parent;
+	void *vcf, *aux;
+{
+	struct confargs *ca = aux;
+	struct romaux *ra = &ca->ca_ra;
+
+	if (strcmp("VME", ra->ra_name))
+		return (0);
+	return (1);
+}
+
+void    
+fgaattach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct confargs *ca = aux, oca[FVME_MAX_RANGES];
+	struct fga_softc *sc = (struct fga_softc *)self;
+	char *s;
+	int i, rlen;
+
+	if (sc->sc_dev.dv_unit > 0) {
+		printf(" unsupported\n");
+		return;
+	}
+
+	/* map registers */
+	if (ca->ca_ra.ra_nreg != 1) {
+		printf(": expected 1 register, got %d\n", ca->ca_ra.ra_nreg);
+		return;
+	}
+	sc->sc_regs = mapiodev(&(ca->ca_ra.ra_reg[0]), 0,
+	    ca->ca_ra.ra_reg[0].rr_len);
+
+	sc->sc_node = ca->ca_ra.ra_node;
+
+	i = opennode("/iommu/sbus");
+	if (i == 0) {
+		printf(": no iommu or sbus found, unconfigured\n");
+		return;
+	}
+	rlen = getproplen(i, "ranges");
+	sc->sc_range =
+	    (struct rom_range *)malloc(rlen, M_DEVBUF, M_NOWAIT);
+	if (sc->sc_range == NULL) {
+		printf(": PROM ranges too large: %d\n", rlen);
+		return;
+	}
+	sc->sc_nrange = rlen / sizeof(struct rom_range);
+	(void)getprop(i, "ranges", sc->sc_range, rlen);
+
+	s = getpropstring(sc->sc_node, "model");
+	printf(": model %s id %c%c%c\n", s,
+	    sc->sc_regs->id[0], sc->sc_regs->id[1], sc->sc_regs->id[2]);
+
+	/*
+	 * The prom leaves at least one of the ranges "on", so make sure
+	 * they are all off.
+	 */
+	for (i = 0; i < 16; i++)
+		sc->sc_regs->vme_range[i] |= VME_RANGE_DECEN;
+
+	sc->sc_regs->sbus_ssel[0] &= ~(SBUS_SSEL_Y);
+	sc->sc_regs->sbus_ssel[0] |= SBUS_SSEL_Y_SLOT4;
+	sc->sc_regs->sbus_ssel[1] &= ~(SBUS_SSEL_X | SBUS_SSEL_Y);
+	sc->sc_regs->sbus_ssel[1] |= SBUS_SSEL_X_SLOT5 | SBUS_SSEL_Y_SLOT5;
+	sc->sc_regs->sbus_ssel[2] &= ~(SBUS_SSEL_X | SBUS_SSEL_Y);
+	sc->sc_regs->sbus_ssel[2] |= SBUS_SSEL_X_SLOT5 | SBUS_SSEL_Y_SLOT1;
+	sc->sc_regs->sbus_ssel[3] &= ~(SBUS_SSEL_X | SBUS_SSEL_Y);
+	sc->sc_regs->sbus_ssel[3] |= SBUS_SSEL_X_SLOT1 | SBUS_SSEL_Y_SLOT1;
+
+	/*
+	 * Map and attach vme<->sbus master ranges
+	 */
+	fga_vmerangemap(sc, 0xf0000000, 0x10000000,
+	    VME_MASTER_CAP_D32 | VME_MASTER_CAP_A32, 1, 0, oca);
+	fga_vmerangemap(sc, 0xf0000000, 0x10000000,
+	    VME_MASTER_CAP_D16 | VME_MASTER_CAP_A32, 4, 0, oca);
+	fga_vmerangemap(sc, 0x00000000, 0x01000000,
+	    VME_MASTER_CAP_D16 | VME_MASTER_CAP_A24, 5, 0xe000000, oca);
+	fga_vmerangemap(sc, 0x00000000, 0x00010000,
+	    VME_MASTER_CAP_D8 | VME_MASTER_CAP_A16, 5, 0x0ffc0000, oca);
+	fga_vmerangemap(sc, 0x00000000, 0x00010000,
+	    VME_MASTER_CAP_D16 | VME_MASTER_CAP_A16, 5, 0x0ffd0000, oca);
+	fga_vmerangemap(sc, 0x00000000, 0x00010000,
+	    VME_MASTER_CAP_D32 | VME_MASTER_CAP_A16, 5, 0x0ffe0000, oca);
+
+#ifdef DDB
+	s = getpropstring(optionsnode, "abort-ena?");
+	if (s && strcmp(s, "true") == 0) {
+		sc->sc_abort = 1;
+		fga_hwintr_establish(sc, IRQ_MAP_SINT7);
+		sc->sc_regs->abort_irq_map &= ~IRQ_MAP_INT_MASK;
+		sc->sc_regs->abort_irq_map |= IRQ_MAP_SINT7;
+		sc->sc_regs->abort_irq_map &= ~IRQ_MAP_ENABLE;
+	}
+#endif
+}
+
+int
+fgaprint(args, name)
+	void *args;
+	const char *name;
+{
+	struct confargs *ca = args;
+
+	if (name)
+		printf("%s at %s", ca->ca_ra.ra_name, name);
+	printf(" slot %d addr 0x%x", ca->ca_slot, ca->ca_offset);
+	return (UNCONF);
+}
+
+/*
+ * Map a region of VME space to a sbus slot/offset.
+ */
+int
+fga_vmerangemap(sc, vmebase, vmelen, vmecap, sbusslot, sbusoffset, oca)
+	struct fga_softc *sc;
+	u_int32_t vmebase, vmelen;
+	int vmecap;
+	int sbusslot;
+	u_int32_t sbusoffset;
+	struct confargs *oca;
+{
+	struct fga_regs *regs = sc->sc_regs;
+	u_int32_t rval;
+	u_int8_t sval;
+	int range, i, srange;
+
+	for (i = 0; i < FVME_MAX_RANGES; i++) {
+		if (regs->vme_range[i] & VME_RANGE_DECEN)
+			break;
+	}
+	if (i == FVME_MAX_RANGES)
+		return (-1);
+	range = i;
+
+	for (srange = 0; srange < sc->sc_nrange; srange++) {
+		if (sbusslot == sc->sc_range[srange].cspace)
+			break;
+	}
+	if (srange == sc->sc_nrange)
+		return (-1);
+
+	oca[range].ca_bustype = BUS_FGA;
+	oca[range].ca_slot = sbusslot;
+	oca[range].ca_offset = sc->sc_range[srange].poffset | sbusoffset;
+	oca[range].ca_ra.ra_name = "fvme";
+	oca[range].ca_ra.ra_nreg = 2;
+	oca[range].ca_ra.ra_reg[0].rr_len = vmelen;
+	oca[range].ca_ra.ra_reg[0].rr_paddr =
+	    (void *)(sc->sc_range[srange].poffset | sbusoffset);
+	oca[range].ca_ra.ra_reg[0].rr_iospace = sbusslot;
+	oca[range].ca_ra.ra_reg[1].rr_iospace = vmecap;
+	oca[range].ca_ra.ra_reg[1].rr_paddr = (void*)vmebase;
+	oca[range].ca_ra.ra_reg[1].rr_len = vmelen;
+
+	/* 1. Setup slot select register for this range. */
+	switch (sbusslot) {
+	case 1:
+		sval = SBUS_SSEL_Y_SLOT1;
+		break;
+	case 2:
+		sval = SBUS_SSEL_Y_SLOT2;
+		break;
+	case 3:
+		sval = SBUS_SSEL_Y_SLOT3;
+		break;
+	case 4:
+		sval = SBUS_SSEL_Y_SLOT4;
+		break;
+	case 5:
+		sval = SBUS_SSEL_Y_SLOT5;
+		break;
+	default:
+		return (-1);
+	}
+
+	if (range & 1) {
+		regs->sbus_ssel[range >> 1] &= ~SBUS_SSEL_Y;
+		regs->sbus_ssel[range >> 1] |= sval;
+	}
+	else {
+		regs->sbus_ssel[range >> 1] &= ~SBUS_SSEL_X;
+		regs->sbus_ssel[range >> 1] |= sval << 4;
+	}
+
+	/* 2. Setup and enable the VME master range. */
+	rval = regs->vme_range[range];
+	rval &= ~(VME_RANGE_VMAE | VME_RANGE_VMAT);
+	rval |= (vmebase >> 13) & (VME_RANGE_VMAE | VME_RANGE_VMAT);
+	rval &= ~VME_RANGE_VMRCC;
+	rval |= ((sbusoffset << 4) | (vmelen << 3)) & VME_RANGE_VMRCC;
+	rval &= ~VME_RANGE_DECEN;
+	regs->vme_range[range] = rval;
+
+	/* 3. Setup addr/data capabilities for the range. */
+	regs->vme_master_cap[range] &=
+	    ~(VME_MASTER_CAP_DATA | VME_MASTER_CAP_ADDR);
+	regs->vme_master_cap[range] |= vmecap;
+
+	(void)config_found(&sc->sc_dev, (void *)&oca[range], fgaprint);
+
+	return (0);
+}
+
+int
+fga_hwintr1(v)
+	void *v;
+{
+	struct fga_softc *sc = v;
+	struct fga_regs *regs = sc->sc_regs;
+	u_int32_t bits = 0, stat;
+	int r = 0, s;
+
+	s = splhigh();
+	stat = regs->intr_stat;
+	splx(s);
+
+	if ((stat & INTR_STAT_VMEIRQ1) == 0) {
+		bits |= INTR_STAT_VMEIRQ1;
+		r |= fga_intrvec(sc, regs->viack_emu1);
+	}
+
+	s = splhigh();
+	regs->intr_stat &= ~bits;
+	splx(s);
+
+	return (r);
+}
+
+int
+fga_hwintr2(v)
+	void *v;
+{
+	struct fga_softc *sc = v;
+	struct fga_regs *regs = sc->sc_regs;
+	int r = 0;
+
+	if ((regs->intr_stat & INTR_STAT_VMEIRQ2) == 0)
+		r |= fga_intrvec(sc, regs->viack_emu2);
+
+	return (r);
+}
+
+int
+fga_hwintr3(v)
+	void *v;
+{
+	struct fga_softc *sc = v;
+	struct fga_regs *regs = sc->sc_regs;
+	int r = 0;
+
+	/* vme irq 3 */
+	if ((regs->intr_stat & INTR_STAT_VMEIRQ3) == 0)
+		r |= fga_intrvec(sc, regs->viack_emu3);
+
+	return (r);
+}
+
+int
+fga_hwintr4(v)
+	void *v;
+{
+	struct fga_softc *sc = v;
+	struct fga_regs *regs = sc->sc_regs;
+	int r = 0;
+
+	if ((regs->intr_stat & INTR_STAT_VMEIRQ4) == 0)
+		r |= fga_intrvec(sc, regs->viack_emu4);
+
+	return (r);
+}
+
+int
+fga_hwintr5(v)
+	void *v;
+{
+	struct fga_softc *sc = v;
+	struct fga_regs *regs = sc->sc_regs;
+	int r = 0;
+
+	if ((regs->intr_stat & INTR_STAT_VMEIRQ5) == 0)
+		r |= fga_intrvec(sc, regs->viack_emu5);
+
+	return (r);
+}
+
+int
+fga_hwintr6(v)
+	void *v;
+{
+	struct fga_softc *sc = v;
+	struct fga_regs *regs = sc->sc_regs;
+	int r = 0;
+
+	if ((regs->intr_stat & INTR_STAT_VMEIRQ6) == 0)
+		r |= fga_intrvec(sc, regs->viack_emu6);
+
+	return (r);
+}
+
+int
+fga_hwintr7(v)
+	void *v;
+{
+	struct fga_softc *sc = v;
+	struct fga_regs *regs = sc->sc_regs;
+	int r = 0, s;
+	u_int32_t bits = 0, stat;
+
+	s = splhigh();
+	stat = regs->intr_stat;
+	splx(s);
+
+#ifdef DDB
+	if (sc->sc_abort && (stat & INTR_STAT_ABORT) == 0) {
+		bits |= INTR_STAT_ABORT;
+		r |= 1;
+		Debugger();
+	}
+#endif
+
+	if ((regs->intr_stat & INTR_STAT_VMEIRQ7) == 0) {
+		bits |= INTR_STAT_VMEIRQ7;
+		r |= fga_intrvec(sc, regs->viack_emu7);
+	}
+
+	s = splhigh();
+	regs->intr_stat &= ~bits;
+	splx(s);
+
+	return (r);
+}
+
+/*
+ * Handle a VME vectored interrupt.
+ */
+int
+fga_intrvec(sc, vec)
+	struct fga_softc *sc;
+	u_int8_t vec;
+{
+	struct intrhand *ih;
+	int r, s = 0;
+
+	if (sc->sc_vmevec == NULL)
+		return (0);
+
+	for (ih = sc->sc_vmevec[vec]; ih; ih = ih->ih_next) {
+		r = (*ih->ih_fun)(ih->ih_arg);
+		if (r > 0)
+			return (r);
+		s |= r;
+	}
+
+	return (s);
+}
+
+/*
+ * Establish a VME level/vector interrupt.
+ */
+int
+fga_intr_establish(sc, vec, level, ih)
+	struct fga_softc *sc;
+	int vec, level;
+	struct intrhand *ih;
+{
+	struct intrhand *ihs;
+	u_int8_t level_to_sint[] = {
+		IRQ_MAP_INT,
+		IRQ_MAP_SINT1,
+		IRQ_MAP_SINT2,
+		IRQ_MAP_SINT3,
+		IRQ_MAP_SINT4,
+		IRQ_MAP_SINT5,
+		IRQ_MAP_SINT6,
+		IRQ_MAP_SINT7
+	};
+	u_int8_t level_to_irqmap[] = {0xff, 6, 5, 4, 3, 2, 1, 0};
+
+	if (level < 1 || level > 7)
+		panic("fga_level");
+
+	/* setup vector handler */
+	if (sc->sc_vmevec == NULL) {
+		sc->sc_vmevec = (struct intrhand **)malloc(256 *
+		    sizeof(struct intrhand *), M_DEVBUF, M_NOWAIT);
+		if (sc->sc_vmevec == NULL)
+			panic("fga_addirq");
+		bzero(sc->sc_vmevec, 256 * sizeof(struct intrhand));
+	}
+	if (sc->sc_vmevec[vec] == NULL)
+		sc->sc_vmevec[vec] = ih;
+	else {
+		ihs = sc->sc_vmevec[vec];
+		while (ihs->ih_next)
+			ihs = ihs->ih_next;
+		ih->ih_next = ih;
+	}
+
+	/* setup hardware handler */
+	fga_hwintr_establish(sc, level_to_sint[level]);
+
+	/* setup/enable vme -> sbus irq mapping */
+	sc->sc_regs->virq_map[level_to_irqmap[level]] &= ~IRQ_MAP_INT_MASK;
+	sc->sc_regs->virq_map[level_to_irqmap[level]] |= level_to_sint[level];
+	sc->sc_regs->virq_map[level_to_irqmap[level]] &= ~IRQ_MAP_ENABLE;
+
+	return (0);
+}
+
+/*
+ * Establish a hardware interrupt, making sure we're not there already.
+ */
+int
+fga_hwintr_establish(sc, sint)
+	struct fga_softc *sc;
+	u_int8_t sint;
+{
+	int sint_to_pri[] = {0, 2, 3, 5, 6, 7, 8, 9};
+
+	if (sc->sc_established & (1 << sint))
+		return (0);
+
+	switch (sint) {
+	case 1:
+		sc->sc_ih1.ih_fun = fga_hwintr1;
+		sc->sc_ih1.ih_arg = sc;
+		intr_establish(sint_to_pri[sint], &sc->sc_ih1);
+		break;
+	case 2:
+		sc->sc_ih2.ih_fun = fga_hwintr2;
+		sc->sc_ih2.ih_arg = sc;
+		intr_establish(sint_to_pri[sint], &sc->sc_ih2);
+		break;
+	case 3:
+		sc->sc_ih3.ih_fun = fga_hwintr3;
+		sc->sc_ih3.ih_arg = sc;
+		intr_establish(sint_to_pri[sint], &sc->sc_ih3);
+		break;
+	case 4:
+		sc->sc_ih4.ih_fun = fga_hwintr4;
+		sc->sc_ih4.ih_arg = sc;
+		intr_establish(sint_to_pri[sint], &sc->sc_ih4);
+		break;
+	case 5:
+		sc->sc_ih5.ih_fun = fga_hwintr5;
+		sc->sc_ih5.ih_arg = sc;
+		intr_establish(sint_to_pri[sint], &sc->sc_ih5);
+		break;
+	case 6:
+		sc->sc_ih6.ih_fun = fga_hwintr6;
+		sc->sc_ih6.ih_arg = sc;
+		intr_establish(sint_to_pri[sint], &sc->sc_ih6);
+		break;
+	case 7:
+		sc->sc_ih7.ih_fun = fga_hwintr7;
+		sc->sc_ih7.ih_arg = sc;
+		intr_establish(sint_to_pri[sint], &sc->sc_ih7);
+		break;
+	default:
+		panic("fga_sint");
+	}
+
+	sc->sc_established |= 1 << sint;
+	return (0);
+}
+
+int
+fgaopen(dev, flags, mode, p)
+	dev_t dev;
+	int flags, mode;
+	struct proc *p;
+{
+	if (fga_cd.cd_ndevs == 0 || fga_cd.cd_ndevs != 0)
+		return (ENXIO);
+	return (0);
+}
+
+int
+fgaclose(dev, flags, mode, p)
+	dev_t dev;
+	int flags, mode;
+	struct proc *p;
+{
+	return (0);
+}
+
+int
+fgaioctl(dev, cmd, data, flags, p)
+	dev_t dev;
+	u_long cmd;
+	caddr_t data;
+	int flags;
+	struct proc *p;
+{
+	struct fga_softc *sc = fga_cd.cd_devs[0];
+	struct fga_sem *fsem = (struct fga_sem *)data;
+	int error = 0;
+
+	switch (cmd) {
+	case FGAIOCSEM:
+		if (fsem->fgasem_num >= 48) {
+			error = ENOENT;
+			break;
+		}
+		sc->sc_regs->sem[fsem->fgasem_num] = 0xff;
+		break;
+	case FGAIOGSEM:
+		if (fsem->fgasem_num >= 48) {
+			error = ENOENT;
+			break;
+		}
+		fsem->fgasem_val =
+		    (sc->sc_regs->sem[fsem->fgasem_num] & MBOX_SEM) ? 0 : 1;
+		break;
+	case FGAIOCMBX:
+		if (fsem->fgasem_num >= 16) {
+			error = ENOENT;
+			break;
+		}
+		sc->sc_regs->mbox[fsem->fgasem_num] = 0xff;
+		break;
+	case FGAIOGMBX:
+		if (fsem->fgasem_num >= 16) {
+			error = ENOENT;
+			break;
+		}
+		fsem->fgasem_val =
+		    sc->sc_regs->mbox[fsem->fgasem_num] ? 0 : 1;
+		break;
+	default:
+		error = EINVAL;
+	}
+
+	return (error);
+}
+
+int
+fvmematch(parent, vcf, aux)
+	struct device *parent;
+	void *vcf, *aux;
+{
+	struct confargs *ca = aux;
+        struct romaux *ra = &ca->ca_ra;
+
+	if (strcmp("fvme", ra->ra_name) || ca->ca_bustype != BUS_FGA)
+		return (0);
+
+	return (1);
+}
+
+struct fvme_types {
+	int data_cap;
+	int addr_cap;
+	char *name;
+	int bustype;
+} fvme_types[] = {
+	{0, 0, "a16d8", BUS_FGA_A16D8},
+	{0, 1, "a24d8", BUS_FGA_A24D8},
+	{0, 2, "a32d8", BUS_FGA_A32D8},
+	{1, 0, "a16d16", BUS_FGA_A16D16},
+	{1, 1, "a24d16", BUS_FGA_A24D16},
+	{1, 2, "a32d16", BUS_FGA_A32D16},
+	{2, 0, "a16d32", BUS_FGA_A16D32},
+	{2, 1, "a24d32", BUS_FGA_A24D32},
+	{2, 2, "a32d32", BUS_FGA_A32D32},
+	{3, 0, "a16blt", -1},
+	{3, 1, "a24blt", -1},
+	{3, 2, "a32blt", -1},
+	{4, 0, "a16mblt", -1},
+	{4, 1, "a24mblt", -1},
+	{4, 2, "a32mblt", -1},
+	{-1, -1, "", -1},
+};
+
+void    
+fvmeattach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct confargs *ca = aux;
+	struct fvme_types *p;
+	int dtype, atype;
+
+	atype = (ca->ca_ra.ra_reg[1].rr_iospace & VME_MASTER_CAP_ADDR) >> 2;
+	dtype = (ca->ca_ra.ra_reg[1].rr_iospace & VME_MASTER_CAP_DATA) >> 5;
+	for (p = fvme_types; p->data_cap != -1; p++) {
+		if (p->data_cap == dtype && p->addr_cap == atype)
+			break;
+	}
+	if (p->data_cap == -1) {
+		printf(" unknown addr/data capability\n");
+		return;
+	}
+	printf(": %s", p->name);
+	if (p->bustype == -1) {
+		printf(" unsupported\n");
+		return;
+	}
+	ca->ca_ra.ra_reg[1].rr_iospace = p->bustype;
+
+	printf(" offset 0x%x len 0x%x\n", ca->ca_ra.ra_reg[1].rr_paddr,
+	   ca->ca_ra.ra_reg[1].rr_len);
+
+	(void)config_search(fvmescan, self, aux);
+}
+
+int
+fvmescan(parent, child, aux)
+	struct device *parent;
+	void *child, *aux;
+{
+	struct cfdata *cf = child;
+	struct confargs *ca = aux, oca;
+	int plen, paddr;
+
+	if (cf->cf_loc[0] == -1)
+		return (0);
+
+	if ((unsigned)cf->cf_loc[0] < (unsigned)ca->ca_ra.ra_reg[1].rr_paddr)
+		return (0);
+
+	paddr = cf->cf_loc[0] - (int)ca->ca_ra.ra_reg[1].rr_paddr;
+	paddr = (int)ca->ca_ra.ra_reg[0].rr_paddr + paddr;
+	plen = cf->cf_loc[0] - (int)ca->ca_ra.ra_reg[1].rr_paddr;
+	plen = ca->ca_ra.ra_reg[1].rr_len - plen;
+
+	oca.ca_bustype = ca->ca_ra.ra_reg[1].rr_iospace;
+	oca.ca_offset = cf->cf_loc[0];
+
+	oca.ca_ra.ra_nintr = 1;
+	oca.ca_ra.ra_intr[0].int_pri = cf->cf_loc[1];
+	oca.ca_ra.ra_intr[0].int_vec = cf->cf_loc[2];
+	oca.ca_ra.ra_name = cf->cf_driver->cd_name;
+
+	oca.ca_ra.ra_nreg = 1;
+	oca.ca_ra.ra_reg[0].rr_paddr = (void *)paddr;
+	oca.ca_ra.ra_reg[0].rr_iospace = ca->ca_ra.ra_reg[0].rr_iospace;
+	oca.ca_ra.ra_reg[0].rr_len = plen;
+	oca.ca_ra.ra_reg[0].rr_paddr =
+	    mapdev(&oca.ca_ra.ra_reg[0], TMPMAP_VA, 0, NBPG);
+
+	if ((*cf->cf_attach->ca_match)(parent, cf, &oca) == 0) {
+		pmap_remove(pmap_kernel(), TMPMAP_VA, TMPMAP_VA + NBPG);
+		return (0);
+	}
+	pmap_remove(pmap_kernel(), TMPMAP_VA, TMPMAP_VA + NBPG);
+
+	oca.ca_ra.ra_reg[0].rr_paddr = (void *)paddr;
+	config_attach(parent, cf, &oca, fvmeprint);
+	return (1);
+}
+
+int
+fvmeprint(args, name)
+	void *args;
+	const char *name;
+{
+	struct confargs *ca = args;
+
+	if (name)
+		printf("%s at %s", ca->ca_ra.ra_name, name);
+	printf(" addr 0x%x", ca->ca_offset);
+	return (UNCONF);
+}
+
+int
+fvmeintrestablish(dsc, vec, level, ih)
+	struct device *dsc;
+	int vec, level;
+	struct intrhand *ih;
+{
+	struct fga_softc *fsc = (struct fga_softc *)dsc->dv_parent;
+
+	return (fga_intr_establish(fsc, vec, level, ih));
+}
diff --git a/sys/arch/sparc/dev/fgaio.h b/sys/arch/sparc/dev/fgaio.h
new file mode 100644
index 00000000000..f139a29d450
--- /dev/null
+++ b/sys/arch/sparc/dev/fgaio.h
@@ -0,0 +1,50 @@
+/*	$OpenBSD: fgaio.h,v 1.1 1999/07/23 19:11:25 jason Exp $	*/
+
+/*
+ * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * This software was developed by Jason L. Wright under contract with
+ * RTMX Incorporated (http://www.rtmx.com).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Jason L. Wright for
+ *	RTMX Incorporated.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * ioctls and flags for FORCE Gate Array 5000
+ */
+
+struct fga_sem {
+	u_int8_t	fgasem_num;	/* which semaphore/mailbox? */
+	u_int8_t	fgasem_val;	/* value of semaphore/mailbox */
+};
+
+#define	FGAIOCSEM	_IOWR('F', 0x01, struct fga_sem) /* clear semaphore */
+#define	FGAIOGSEM	_IOWR('F', 0x02, struct fga_sem) /* get semaphore */
+#define	FGAIOCMBX	_IOWR('F', 0x03, struct fga_sem) /* clear mailbox */
+#define	FGAIOGMBX	_IOWR('F', 0x04, struct fga_sem) /* get mailbox */
diff --git a/sys/arch/sparc/dev/fgareg.h b/sys/arch/sparc/dev/fgareg.h
new file mode 100644
index 00000000000..ffc6cd7f410
--- /dev/null
+++ b/sys/arch/sparc/dev/fgareg.h
@@ -0,0 +1,397 @@
+/*	$OpenBSD: fgareg.h,v 1.1 1999/07/23 19:11:25 jason Exp $	*/
+
+/*
+ * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * This software was developed by Jason L. Wright under contract with
+ * RTMX Incorporated (http://www.rtmx.com).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Jason L. Wright for
+ *	RTMX Incorporated.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Register definitions for Force Gate Array 5000
+ * Definitions from: "Force Gate Array-5000 Technical Reference Manual"
+ * revision 1, April 1995, Force Computers, Inc./GmbH.
+ */
+
+/*
+ * FGA Register structure.
+ * The register set takes up 512 bytes and is found in to sbus slot 5's
+ * address space (you can change that).
+ * Most of the bit registers use a negative logic sense: ie. writing
+ * a zero means "setting the bit" and writing a one means "clearing"
+ * the bit.
+ */
+struct fga_regs {
+	volatile u_int32_t	sbus_base;	/* sbus base address reg */
+	volatile u_int32_t	vme_range[16];	/* master range registers */
+	volatile u_int8_t	_unused0[32];
+	volatile u_int8_t	vme_master_cap[16];/* master capability */
+	volatile u_int8_t	_unused1[8];
+	volatile u_int8_t	sbus_ssel[8];	/* sbus slot select */
+	volatile u_int8_t	_unused2[15];
+	volatile u_int8_t	viack_emu1;	/* vme intr ack emulation */
+	volatile u_int8_t	_unused3[1];
+	volatile u_int8_t	viack_emu2;
+	volatile u_int8_t	_unused4[1];
+	volatile u_int8_t	viack_emu3;
+	volatile u_int8_t	_unused5[1];
+	volatile u_int8_t	viack_emu4;
+	volatile u_int8_t	_unused6[1];
+	volatile u_int8_t	viack_emu5;
+	volatile u_int8_t	_unused7[1];
+	volatile u_int8_t	viack_emu6;
+	volatile u_int8_t	_unused8[1];
+	volatile u_int8_t	viack_emu7;
+	volatile u_int8_t	_unused9[16];
+	volatile u_int8_t	sbus_cap;	/* sbus capabilities */
+	volatile u_int8_t	sbus_retry_ctrl; /* sbus retry control */
+	volatile u_int8_t	sbus_rerun_ctrl; /* sbus rerun control */
+	volatile u_int8_t	sbus_cap2;	/* sbus capabilities 2 */
+	volatile u_int32_t	swpar;		/* sbus write post err addr */
+	volatile u_int32_t	slerr;		/* sbus late err addr */
+	volatile u_int32_t	_unused10;
+	volatile u_int8_t	vme_base;	/* vme slave base addr */
+	volatile u_int8_t	vme_ext[3];	/* vme slave addr extension */
+	volatile u_int32_t	sbus_range[3];	/* vme->sbus slave addr */
+	volatile u_int16_t	ibox_addr;	/* ibox address */
+	volatile u_int16_t	ibox_ctrl;	/* ibox control */
+	volatile u_int8_t	fmb_ctrl;	/* FMB control reg */
+	volatile u_int8_t	fmb_addr;	/* FMB addresss reg */
+	volatile u_int8_t	_unused11[10];
+	volatile u_int8_t	vme_cap;	/* vme capabilities */
+	volatile u_int8_t	vmebus_handshake; /* vme handshake mode */
+	volatile u_int8_t	_unused12[2];
+	volatile u_int32_t	vwpar;		/* vme write post addr */
+	volatile u_int8_t	_unused13[8];
+	volatile u_int16_t	dma_ctrl;	/* dma control */
+	volatile u_int8_t	dma_mode;	/* dma mode */
+	volatile u_int8_t	dma_stat;	/* dma status */
+	volatile u_int32_t	dma_src;	/* dma source address */
+	volatile u_int32_t	dma_dst;	/* dma destination address */
+	volatile u_int32_t	dma_captl;	/* dma capabilities/length */
+	volatile u_int8_t	_unused14[32];
+	volatile u_int8_t	mbox[16];	/* mailboxes */
+	volatile u_int8_t	sem[48];	/* semaphores */
+	volatile u_int8_t	_unused15[32];
+	volatile u_int8_t	id[4];		/* revision/id register */
+	volatile u_int8_t	gcsr;		/* global control/status */
+	volatile u_int8_t	_unused16[3];
+	volatile u_int8_t	reset_stat;	/* reset status */
+	volatile u_int8_t	_unused17[24];
+	volatile u_int8_t	virq_map[7];	/* vme->sbus irq mapping */
+	volatile u_int8_t	mbox_irq_map[16];
+	volatile u_int8_t	acfail_irq_map;
+	volatile u_int8_t	sysfail_irq_map[2];
+	volatile u_int8_t	abort_irq_map;
+	volatile u_int8_t	dma_irq_map;
+	volatile u_int8_t	wpe_irq_map;
+	volatile u_int8_t	arb_irq_map;
+	volatile u_int8_t	wdt_irq_map;
+	volatile u_int8_t	slerr_irq_map;
+	volatile u_int8_t	fmb_irq_map[2];
+	volatile u_int8_t	ibox_irq_map;
+	volatile u_int8_t	_unused18[20];
+	volatile u_int16_t	mbox_stat;	/* mailbox status */
+	volatile u_int8_t	_unused19[2];
+	volatile u_int8_t	arb_ctrl;	/* arbitration control */
+	volatile u_int8_t	req_ctrl;	/* vme request control */
+	volatile u_int8_t	bus_ctrl;	/* vme bus control */
+	volatile u_int8_t	_unused20[1];
+	volatile u_int8_t	mcsr0;		/* misc control/status */
+	volatile u_int8_t	_unused21[3];
+	volatile u_int8_t	mcsr1;		/* misc control/status */
+	volatile u_int8_t	wdt_restart;	/* watchdog restart */
+	volatile u_int8_t	_unused22[2];
+	volatile u_int32_t	intr_stat;	/* interrupt status */
+	volatile u_int8_t	_unused23[20];
+};
+
+/* sbus_base: sbus base address register */
+#define	SBUS_BASE_RMBA		0xffffe000	/* reg map base address */
+#define	SBUS_BASE_RMSS		0x00000007	/* reg map slot select bits */
+
+/* vme_range0..15: master range registers */
+#define	VME_RANGE_VMRCC		0xfff80000	/* master range compare code */
+#define	VME_RANGE_VMAE		0x00078000	/* master adr extension bits */
+#define	VME_RANGE_VMAT		0x00007ff8	/* master adr xlation bits */
+#define	VME_RANGE_WPEN		0x00000002	/* write posting enable */
+#define	VME_RANGE_DECEN		0x00000001	/* range decoding enable */
+
+/* vme_master_map0..15: master capability registers */
+#define	VME_MASTER_CAP_DATA	0xe0		/* data capabilities */
+#define	VME_MASTER_CAP_D8	0x00		/* vmebus D8 */
+#define	VME_MASTER_CAP_D16	0x20		/* vmebus D16 */
+#define	VME_MASTER_CAP_D32	0x40		/* vmebus D32 */
+#define	VME_MASTER_CAP_DBLT	0x60		/* vmebus BLT */
+#define	VME_MASTER_CAP_DMBLT	0x80		/* vmebus MBLT */
+#define	VME_MASTER_CAP_ADDR	0x1c		/* addr capabilities */
+#define	VME_MASTER_CAP_A16	0x00		/* vmebus A16 */
+#define	VME_MASTER_CAP_A24	0x04		/* vmebus A24 */
+#define	VME_MASTER_CAP_A32	0x08		/* vmebus A32 */
+#define	FVME_MAX_RANGES		16		/* number of ranges avail */
+
+/* sbus_ssel0..15: sbus slot select registers */
+#define	SBUS_SSEL_X		0x70		/* slot select pins range X */
+#define	SBUS_SSEL_X_SLOT1	0x00		/* sbus slot 1 */
+#define	SBUS_SSEL_X_SLOT2	0x10		/* sbus slot 2 */
+#define	SBUS_SSEL_X_SLOT3	0x20		/* sbus slot 3 */
+#define	SBUS_SSEL_X_SLOT4	0x30		/* sbus slot 4 */
+#define	SBUS_SSEL_X_SLOT5x	0x40		/* sbus slot 5? */
+#define	SBUS_SSEL_X_SLOT5	0x50		/* sbus slot 5 */
+#define	SBUS_SSEL_Y		0x07		/* slot select pins range X+1*/
+#define	SBUS_SSEL_Y_SLOT1	0x00		/* sbus slot 1 */
+#define	SBUS_SSEL_Y_SLOT2	0x01		/* sbus slot 2 */
+#define	SBUS_SSEL_Y_SLOT3	0x02		/* sbus slot 3 */
+#define	SBUS_SSEL_Y_SLOT4	0x03		/* sbus slot 4 */
+#define	SBUS_SSEL_Y_SLOT5x	0x04		/* sbus slot 5? */
+#define	SBUS_SSEL_Y_SLOT5	0x05		/* sbus slot 5 */
+
+/* viack_emu1..7: iack emulation registers */
+/* bits contain d00-d07 from VMEbus interrupter */
+
+/* sbus_cap: sbus capability register */
+#define	SBUS_CAP_BURSTMASK	0xc0		/* dma burst size mask */
+#define	SBUS_CAP_BURST_64	0xc0		/* 64 byte burst */
+#define	SBUS_CAP_BURST_32	0x80		/* 32 byte burst */
+#define	SBUS_CAP_BURST_16	0x40		/* 16 byte burst */
+#define	SBUS_CAP_BURST_8	0x00		/* 8 byte burst */
+#define	SBUS_CAP_READSTOPMASK	0x30		/* master read stop point */
+#define	SBUS_CAP_READSTOP_64	0x30		/* stop at 64 byte boundary */
+#define	SBUS_CAP_READSTOP_32	0x20		/* stop at 32 byte boundary */
+#define	SBUS_CAP_READSTOP_16	0x10		/* stop at 16 byte boundary */
+#define	SBUS_CAP_READSTOP_8	0x00		/* stop at 8 byte boundary */
+#define	SBUS_CAP_BURSTDIS	0x08		/* disable sbus bursts */
+#define	SBUS_CAP_HIDDENARBDIS	0x04		/* disable sbus hidden arb */
+#define	SBUS_CAP_SPLITFLOW	0x02		/* disable flow through */
+
+/* sbus_retry_ctrl: sbus retry register */
+/* clock cycles with no acknowledge */
+
+/* sbus_rerun_ctrl: sbus rerun limit register */
+/* number of times to reruns to try on the bus */
+
+/* swpar: sbus write posting error address register */
+/* virtual sbus transfer address that was ack'd with an error */
+
+/* slerr: sbus late error address register */
+/* virtual sbus address that resulted in a late transfer */
+
+/* vme_base: VMEbus base address register */
+#define VME_BASE_RMVBA		0xfe		/* reg map base address */
+#define	VME_BASE_RMACCEN	0x01		/* reg remote access enable */
+
+/* vme_ext0..2: slave address extension registers */
+/* extensions of A24 VMEbus address to 32bit sbus address (msb) */
+
+/* sbus_range0..2: slave range registers */
+#define	SBUS_RANGE_VSRCC	0xfff00000	/* slave range compare code */
+#define	SBUS_RANGE_VSAT		0x000ffe00	/* slave address translation */
+#define	SBUS_RANGE_A32DIS	0x00000004	/* disable A32 (enable A24) */
+#define	SBUS_RANGE_WPDIS	0x00000002	/* disable write posting */
+#define	SBUS_RANGE_DECDIS	0x00000001	/* disable encoding */
+
+/* ibox_addr: IBOX address register */
+/* address within VME A16 space where the IBOX is accessed */
+
+/* ibox_ctrl: IBOX control register */
+#define	IBOX_CTRL_DIS		0x01		/* disable ibox */
+
+/* fmb_ctrl: force message broadcast control register */
+#define	FMB_CTRL_SELAM		0x80		/* supervisor/user access */
+#define	FMB_CTRL_DISCH1		0x40		/* disable channel 1 */
+#define	FMB_CTRL_DISCH2		0x20		/* disable channel 2 */
+#define	FMB_CTRL_SLOTID		0x1f		/* slot id: 1-15 */
+
+/* vme_cap: global master capability register */
+#define	VME_CAP_NPRV		0x80		/* supervisor access */
+
+/* vmebus_handshake: VMEbus handshake configuration register */
+#define	VME_HANDSHAKE_DISSGLE	0x80		/* disable glitch filter */
+#define	VME_HANDSHAKE_DISASFAST	0x40		/* disable fast AS handshake */
+#define	VME_HANDSHAKE_DISDS	0x20		/* disable fast data strobe */
+
+/* vwpar: VMEbus write posting address register */
+/* contains address ack'd with a BERR from the VME bus */
+
+/* dma_ctrl: dma control register */
+#define	DMA_CTRL_DMAEN		0x80		/* enable (start) dma */
+#define	DMA_CTRL_DMADIS		0x40		/* disable dma transaction */
+#define	DMA_CTRL_DMAHLT		0x20		/* stop dma transaction */
+#define	DMA_CTRL_DMARESU	0x10		/* resume dma transaction */
+
+/* dma_mode: dma mode register */
+#define	DMA_MODE_DMASB		0x80		/* single buffer mode */
+#define	DMA_MODE_DMANRTRY	0x40		/* error on retry */
+
+/* dma_stat: dma status register */
+#define	DMA_STAT_DMARUN		0x80		/* dma task is running */
+#define	DMA_STAT_DMAWT		0x40		/* dma task is halted */
+#define	DMA_STAT_DMANT		0x20		/* dma task successful */
+#define	DMA_STAT_ERRMASK	0x18		/* dma error mask */
+#define	DMA_STAT_ERR_SRC	0x00		/* error on source bus */
+#define	DMA_STAT_ERR_DST	0x08		/* error on destination bus */
+#define	DMA_STAT_ERR_NONE	0x10		/* no error termination */
+#define	DMA_STAT_ERR_NOERROR	0x18		/* no error termination */
+
+/* dma_src: dma source address register */
+#define	DMA_SRC_ADDR		0xfffffffc	/* source address */
+#define	DMA_SRC_VME		0x00000002	/* 0=vme, 1=sbus */
+
+/* dma_dst: dma destination address register */
+#define	DMA_DST_ADDR		0xfffffffc	/* destination address */
+#define	DMA_DST_VME		0x00000002	/* 0=vme, 1=sbus */
+
+/* dma_captl: dma capability/transfer length */
+#define	DMA_CAPTL_SCAPD_MASK	0xe0000000	/* src data capability */
+#define	DMA_CAPTL_SCAPD_D8	0x00000000	/* D8 slave */
+#define	DMA_CAPTL_SCAPD_D16	0x20000000	/* D16 slave */
+#define	DMA_CAPTL_SCAPD_D32	0x40000000	/* D32 slave */
+#define	DMA_CAPTL_SCAPD_BLT	0x60000000	/* BLT slave */
+#define	DMA_CAPTL_SCAPD_MBLT	0x80000000	/* MBLT slave */
+#define	DMA_CAPTL_SCAPA_MASK	0x1c000000	/* src addr capability */
+#define	DMA_CAPTL_SCAPA_A16	0x00000000	/* A16 slave */
+#define	DMA_CAPTL_SCAPA_A24	0x04000000	/* A24 slave */
+#define	DMA_CAPTL_SCAPA_A32	0x08000000	/* A32 slave */
+#define	DMA_CAPTL_DCAPD_MASK	0x03800000	/* dst data capability */
+
+/* mbox0..15: mailbox registers */
+#define	MBOX_SEM		0x80		/* semaphore bit */
+
+/* sem0..47: semaphore registers */
+#define	SEM_SEM			0x80		/* semaphore bit */
+
+/* gcsr: global control and status register */
+#define	GCSR_SETSYSFAIL		0x80		/* assert SYSFAIL* signal */
+#define	GCSR_ENSYSFAIL		0x40		/* enable SYSFAIL* output */
+#define	GCSR_SYSFAIL		0x20		/* SYSFAIL* input status */
+#define	GCSR_RESET		0x10		/* software reset */
+#define	GCSR_ACFAIL		0x08		/* ACFAIL input status */
+#define	GCSR_DISVDR		0x04		/* disable VME DTB drivers */
+#define	GCSR_ENSYSCON		0x02		/* enable system controller */
+
+/* reset_stat: reset status register */
+#define	RESET_STAT_SBUS_RESET	0x80		/* sbus has been reset */
+#define	RESET_STAT_VME_SYSRES	0x40		/* vmebus has been reset */
+#define	RESET_STAT_WDT_RESET	0x20		/* watchdog has triggered */
+#define	RESET_STAT_SYSRES_CALL	0x04		/* sysreset in mcsr0 set */
+#define	RESET_STAT_RESET_CALL	0x02		/* reset in mcsr0 set */
+#define	RESET_STAT_LOCRES_CALL	0x01		/* reset in ccsr set */
+
+/* *irq_map: interrupt request mapping registers */
+#define	IRQ_MAP_ENABLE		0x08		/* enable irq */
+#define	IRQ_MAP_INT_MASK	0x07		/* irq mapping mask */
+#define	IRQ_MAP_INT		0x00		/* NMI */
+#define	IRQ_MAP_SINT1		0x01		/* sbus pri 1 */
+#define	IRQ_MAP_SINT2		0x02		/* sbus pri 2 */
+#define	IRQ_MAP_SINT3		0x03		/* sbus pri 3 */
+#define	IRQ_MAP_SINT4		0x04		/* sbus pri 4 */
+#define	IRQ_MAP_SINT5		0x05		/* sbus pri 5 */
+#define	IRQ_MAP_SINT6		0x06		/* sbus pri 6 */
+#define	IRQ_MAP_SINT7		0x07		/* sbus pri 7 */
+
+/* mbox_stat: mailbox status interrupt status register */
+/* 1 bit for each mailbox, 0 = interrupt pending, 1 = no interrupt pending */
+
+/* arb_ctrl: arbitration control register */
+#define	ARB_CTRL_MASK		0xc0		/* control mask */
+#define	ARB_CTRL_PRIORITY	0xc0		/* priority mode */
+#define	ARB_CTRL_ROBIN		0x40		/* round robin mode */
+#define	ARB_CTRL_PRIROBIN	0x80		/* priority round robin mode */
+
+/* req_ctrl: VMEbus request control register */
+#define	REQ_CTRL_FM		0x80		/* 0=fair,1=demand mode */
+#define	REQ_CTRL_RM_MASK	0x70		/* release mode mask */
+#define	REQ_CTRL_RM_ROR		0x30		/* release on request */
+#define	REQ_CTRL_RM_ROC		0x40		/* release on bus clear */
+#define	REQ_CTRL_RM_RAT		0x60		/* release after timeout */
+#define	REQ_CTRL_RM_RWD		0x70		/* release when done */
+#define	REQ_CTRL_REC		0x08		/* 0=begin,1=end of cycle */
+#define	REQ_CTRL_RL_MASK	0x06		/* request level mask */
+#define	REQ_CTRL_RL_BR3		0x06		/* br3 priority */
+#define	REQ_CTRL_RL_BR2		0x04		/* br2 priority */
+#define	REQ_CTRL_RL_BR1		0x02		/* br1 priority */
+#define	REQ_CTRL_RL_BR0		0x00		/* br0 priority */
+#define	REQ_CTRL_GLFI		0x01		/* enable bbsy glitch filter */
+
+/* bus_ctrl: VMEbus capture register */
+#define	BUS_CTRL_BCAP		0x80		/* request and keep bus */
+#define	BUS_CTRL_OWN		0x40		/* do we own the bus? */
+
+/* mcsr0: miscellaneous control and status register 0 */
+#define	MCSR0_ABORTSW		0x80		/* status of abort switch */
+#define	MCSR0_SCON		0x40		/* status of SCON input */
+#define	MCSR0_SYSRESET		0x20		/* assert SYSRESET* */
+#define	MCSR0_RESET		0x10		/* software reset fga5000 */
+#define	MCSR0_ENA_VME_TIMEOUT	0x08		/* enable VME timeout */
+#define	MCSR0_VME_TIMEOUT_MASK	0x06		/* VME transaction timeout */
+#define	MCSR0_VME_TIMEOUT_32	0x02		/* 32 usec */
+#define	MCSR0_VME_TIMEOUT_128	0x04		/* 128 usec */
+#define	MCSR0_VME_TIMEOUT_512	0x06		/* 512 usec */
+#define	MCSR0_SYSRESET_IN	0x01		/* enable SYSRESET input */
+
+/* mcsr1: miscellaneous control and status register 1 */
+#define	MCSR1_ENAWDT		0x80		/* enable watchdog timer */
+#define	MCSR1_TIMEOUT_MASK	0x70		/* watchdog timeout mask */
+#define	MCSR1_TIMEOUT_408MS	0x00		/* 408 msec */
+#define	MCSR1_TIMEOUT_168S	0x10		/* 1.68 sec */
+#define	MCSR1_TIMEOUT_67S	0x20		/* 6.7 sec */
+#define	MCSR1_TIMEOUT_268S	0x30		/* 26.8 sec */
+#define	MCSR1_TIMEOUT_1M48S	0x40		/* 1 min 48 sec */
+#define	MCSR1_TIMEOUT_7M9S	0x50		/* 7 min 9 sec */
+#define	MCSR1_TIMEOUT_28M38S	0x60		/* 28 min 38 sec */
+#define	MCSR1_TIMEOUT_1H54M	0x70		/* 1 hour 54 min */
+#define	MCSR1_IRQ_FREEZE	0x08		/* freeze irq map regs */
+
+/* wdt_restart: watchdog timer restart register */
+/* any read/write resets the watchdog timer */
+
+/* intr_stat: interrupt status register */
+#define	INTR_STAT_ACFAIL	0x80000000	/* acfail pending */
+#define	INTR_STAT_SYSFAILASSERT	0x40000000	/* sysfail assert pending */
+#define	INTR_STAT_SYSFAILNEGATE	0x20000000	/* sysfail negate pending */
+#define	INTR_STAT_ABORT		0x10000000	/* abort pending */
+#define	INTR_STAT_ARBTIMEOUT	0x08000000	/* arbitration timeout */
+#define	INTR_STAT_MAILBOX	0x04000000	/* mailbox intr pending */
+#define	INTR_STAT_SBUS_WPERR	0x02000000	/* sbus wperr pending */
+#define	INTR_STAT_VME_WPERR	0x01000000	/* vme wperr pending */
+#define	INTR_STAT_DMATERM	0x00800000	/* dma finished */
+#define	INTR_STAT_WDT		0x00400000	/* watchdog half timeout */
+#define	INTR_STAT_SLERR		0x00200000	/* sbus late error pending */
+#define	INTR_STAT_IBOX		0x00100000	/* ibox pending */
+#define	INTR_STAT_FMB0		0x00080000	/* fmb channel 0 pending */
+#define	INTR_STAT_FMB1		0x00040000	/* fmb channel 1 pending */
+#define	INTR_STAT_VMEIRQ7	0x00000080	/* vme irq 7 pending */
+#define	INTR_STAT_VMEIRQ6	0x00000040	/* vme irq 6 pending */
+#define	INTR_STAT_VMEIRQ5	0x00000020	/* vme irq 5 pending */
+#define	INTR_STAT_VMEIRQ4	0x00000010	/* vme irq 4 pending */
+#define	INTR_STAT_VMEIRQ3	0x00000008	/* vme irq 3 pending */
+#define	INTR_STAT_VMEIRQ2	0x00000004	/* vme irq 2 pending */
+#define	INTR_STAT_VMEIRQ1	0x00000002	/* vme irq 1 pending */
diff --git a/sys/arch/sparc/dev/fgavar.h b/sys/arch/sparc/dev/fgavar.h
new file mode 100644
index 00000000000..7edecd8ae3d
--- /dev/null
+++ b/sys/arch/sparc/dev/fgavar.h
@@ -0,0 +1,38 @@
+/*	$OpenBSD: fgavar.h,v 1.1 1999/07/23 19:11:25 jason Exp $	*/
+
+/*
+ * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * This software was developed by Jason L. Wright under contract with
+ * RTMX Incorporated (http://www.rtmx.com).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Jason L. Wright for
+ *	RTMX Incorporated.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+int fvmeintrestablish __P((struct device *, int, int, struct intrhand *));
diff --git a/sys/arch/sparc/dev/flash.c b/sys/arch/sparc/dev/flash.c
new file mode 100644
index 00000000000..e7b68f459a0
--- /dev/null
+++ b/sys/arch/sparc/dev/flash.c
@@ -0,0 +1,199 @@
+/*	$OpenBSD: flash.c,v 1.1 1999/07/23 19:11:26 jason Exp $	*/
+
+/*
+ * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Jason L. Wright
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the flash memory found on FORCE CPU-5V boards.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/errno.h>
+#include <sys/ioctl.h>
+#include <sys/syslog.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <machine/autoconf.h>
+#include <sparc/cpu.h>
+#include <sparc/sparc/cpuvar.h>
+
+int	flashmatch	__P((struct device *, void *, void *));
+void	flashattach	__P((struct device *, struct device *, void *));
+
+int	flashopen	__P((dev_t, int, int, struct proc *p));
+int	flashclose	__P((dev_t, int, int, struct proc *p));
+int	flashread	__P((dev_t, struct uio *, int));
+int	flashwrite	__P((dev_t, struct uio *, int));
+int	flashrw		__P((dev_t, struct uio *, int));
+int	flashioctl	__P((dev_t, u_long, caddr_t, int, struct proc *));
+
+/*
+ * We see the flash-memory in 512k windows.  The current window is
+ * changed in the sysconfig registers (FMPCR1), see scf.c.
+ */
+#define	FLASH_REGS_SIZE		0x80000
+
+struct flash_regs {
+	u_int8_t		regs[0x80000];
+};
+
+struct flash_softc {
+	struct device		sc_dv;
+	struct flash_regs	*sc_regs;
+	int			sc_node;
+	int			sc_open;
+};
+
+struct cfattach flash_ca = {
+	sizeof (struct flash_softc), flashmatch, flashattach
+};
+
+struct cfdriver flash_cd = {
+	NULL, "flash", DV_IFNET
+};
+
+int
+flashmatch(parent, vcf, aux)
+	struct device *parent;
+	void *vcf, *aux;
+{
+	struct confargs *ca = aux;
+	register struct romaux *ra = &ca->ca_ra;
+
+	if (strcmp("flash-memory", ra->ra_name))
+		return (0);
+	return (1);
+}
+
+void    
+flashattach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct confargs *ca = aux;
+	struct flash_softc *sc = (struct flash_softc *)self;
+
+	/* map registers */
+	if (ca->ca_ra.ra_nreg != 1) {
+		printf(": expected 1 register, got %d\n", ca->ca_ra.ra_nreg);
+		return;
+	}
+	sc->sc_regs = mapiodev(&(ca->ca_ra.ra_reg[0]), 0,
+			ca->ca_ra.ra_reg[0].rr_len);
+
+	sc->sc_node = ca->ca_ra.ra_node;
+
+	printf(": window 0x%x\n", ca->ca_ra.ra_reg[0].rr_len);
+}
+
+int
+flashopen(dev, flags, mode, p)
+	dev_t dev;
+	int flags;
+	int mode;
+	struct proc *p;
+{
+	struct flash_softc *sc;
+	int card = 0;
+
+	if (card >= flash_cd.cd_ndevs)
+		return (ENXIO);
+	sc = flash_cd.cd_devs[card];
+	if (sc->sc_open)
+		return (EBUSY);
+	sc->sc_open = 1;
+	return (0);
+}
+
+int
+flashclose(dev, flags, mode, p)
+	dev_t dev;
+	int flags;
+	int mode;
+	struct proc *p;
+{
+	struct flash_softc *sc = flash_cd.cd_devs[0];
+	sc->sc_open = 0;
+	return (0);
+}
+
+int
+flashwrite(dev, uio, flags)
+	dev_t dev;
+	struct uio *uio;
+	int flags;
+{
+	return (flashrw(dev, uio, flags));
+}
+
+int
+flashread(dev, uio, flags)
+	dev_t dev;
+	struct uio *uio;
+	int flags;
+{
+	return (flashrw(dev, uio, flags));
+}
+
+int
+flashrw(dev, uio, flags)
+	dev_t dev;
+	struct uio *uio;
+	int flags;
+{
+	struct flash_softc *sc = flash_cd.cd_devs[0];
+	u_int cnt;
+	int off;
+
+	off = uio->uio_offset;
+	if (off >= FLASH_REGS_SIZE)
+		return (EFAULT);
+
+	cnt = uio->uio_resid;
+	if (cnt > (FLASH_REGS_SIZE - off))
+		cnt = FLASH_REGS_SIZE - off;
+
+	return (uiomove(&sc->sc_regs->regs[0] + off, cnt, uio));
+}
+
+int
+flashioctl(dev, cmd, data, flags, p)
+	dev_t dev;
+	u_long cmd;
+	caddr_t data;
+	int flags;
+	struct proc *p;
+{
+	return (EINVAL);
+}
diff --git a/sys/arch/sparc/dev/scf.c b/sys/arch/sparc/dev/scf.c
new file mode 100644
index 00000000000..c7fe981784b
--- /dev/null
+++ b/sys/arch/sparc/dev/scf.c
@@ -0,0 +1,297 @@
+/*	$OpenBSD: scf.c,v 1.1 1999/07/23 19:11:26 jason Exp $	*/
+
+/*
+ * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * This software was developed by Jason L. Wright under contract with
+ * RTMX Incorporated (http://www.rtmx.com).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Jason L. Wright for
+ *	RTMX Incorporated.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the flash memory and sysconfig registers found on Force CPU-5V
+ * boards.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/errno.h>
+#include <sys/ioctl.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+#include <sys/syslog.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <machine/autoconf.h>
+#include <sparc/cpu.h>
+#include <sparc/sparc/cpuvar.h>
+#include <sparc/dev/scfio.h>
+#include <sparc/dev/scfreg.h>
+
+int	scfmatch	__P((struct device *, void *, void *));
+void	scfattach	__P((struct device *, struct device *, void *));
+
+int	scfopen	__P((dev_t, int, int, struct proc *));
+int	scfclose	__P((dev_t, int, int, struct proc *));
+int	scfioctl	__P((dev_t, u_long, caddr_t, int, struct proc *));
+
+struct scf_softc {
+	struct	device sc_dv;			/* base device */
+	struct	scf_regs *sc_regs;	/* our registers */
+	int	sc_open;
+	int	sc_tick;
+};
+
+struct cfattach scf_ca = {
+	sizeof (struct scf_softc), scfmatch, scfattach
+};
+
+struct cfdriver scf_cd = {
+	NULL, "sysconfig", DV_IFNET
+};
+
+extern int sparc_led_blink;
+
+static u_int8_t scf_pattern[] = {
+	SSLDCR_A|SSLDCR_B|SSLDCR_C|SSLDCR_D|SSLDCR_E|SSLDCR_F,
+	SSLDCR_B|SSLDCR_C,
+	SSLDCR_A|SSLDCR_B|SSLDCR_D|SSLDCR_E|SSLDCR_G,
+	SSLDCR_A|SSLDCR_B|SSLDCR_C|SSLDCR_D|SSLDCR_G,
+	SSLDCR_B|SSLDCR_C|SSLDCR_F|SSLDCR_G,
+	SSLDCR_A|SSLDCR_C|SSLDCR_D|SSLDCR_F|SSLDCR_G,
+	SSLDCR_A|SSLDCR_C|SSLDCR_D|SSLDCR_E|SSLDCR_F|SSLDCR_G,
+	SSLDCR_A|SSLDCR_B|SSLDCR_C,
+	SSLDCR_A|SSLDCR_B|SSLDCR_C|SSLDCR_D|SSLDCR_E|SSLDCR_F|SSLDCR_G,
+	SSLDCR_A|SSLDCR_B|SSLDCR_C|SSLDCR_D|SSLDCR_F|SSLDCR_G,
+	SSLDCR_A|SSLDCR_B|SSLDCR_C|SSLDCR_E|SSLDCR_F|SSLDCR_G,
+	SSLDCR_C|SSLDCR_D|SSLDCR_E|SSLDCR_F|SSLDCR_G,
+	SSLDCR_A|SSLDCR_D|SSLDCR_E|SSLDCR_F,
+	SSLDCR_B|SSLDCR_C|SSLDCR_D|SSLDCR_E|SSLDCR_G,
+	SSLDCR_A|SSLDCR_D|SSLDCR_E|SSLDCR_F|SSLDCR_G,
+	SSLDCR_A|SSLDCR_E|SSLDCR_F|SSLDCR_G,
+};
+
+int
+scfmatch(parent, vcf, aux)
+	struct device *parent;
+	void *vcf, *aux;
+{
+	struct confargs *ca = aux;
+	register struct romaux *ra = &ca->ca_ra;
+
+	if (strcmp("sysconfig", ra->ra_name))
+		return (0);
+
+	return (1);
+}
+
+void    
+scfattach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct confargs *ca = aux;
+	struct scf_softc *sc = (struct scf_softc *)self;
+	char *s;
+
+	/* map registers */
+	if (ca->ca_ra.ra_nreg != 1) {
+		printf(": expected 1 register, got %d\n", ca->ca_ra.ra_nreg);
+		return;
+	}
+
+	sc->sc_regs = mapiodev(&(ca->ca_ra.ra_reg[0]), 0,
+			ca->ca_ra.ra_reg[0].rr_len);
+
+	s = getpropstring(ca->ca_ra.ra_node, "model");
+	printf(": model %s\n", s);
+
+	sc->sc_regs->led1 &= ~LED_MASK;
+	sc->sc_regs->led1 &= ~LED_MASK;
+	sc->sc_regs->ssldcr = 0;
+
+	if (sparc_led_blink)
+		scfblink(0);
+}
+
+int
+scfopen(dev, flags, mode, p)
+	dev_t dev;
+	int flags;
+	int mode;
+	struct proc *p;
+{
+	struct scf_softc *sc;
+	int card = 0;
+
+	if (card >= scf_cd.cd_ndevs)
+		return (ENXIO);
+
+	sc = scf_cd.cd_devs[card];
+	if (sc->sc_open)
+		return (EBUSY);
+
+	sc->sc_open = 1;
+	return (0);
+}
+
+int
+scfclose(dev, flags, mode, p)
+	dev_t dev;
+	int flags;
+	int mode;
+	struct proc *p;
+{
+	struct scf_softc *sc;
+	int card = 0;
+
+	sc = scf_cd.cd_devs[card];
+	sc->sc_open = 0;
+	return (0);
+}
+
+int
+scfioctl(dev, cmd, data, flags, p)
+	dev_t dev;
+	u_long cmd;
+	caddr_t data;
+	int flags;
+	struct proc *p;
+{
+	struct scf_softc *sc = scf_cd.cd_devs[0];
+	u_int8_t *ptr = (u_int8_t *)data, c;
+	int error = 0;
+
+	switch (cmd) {
+	case SCFIOCSLED1:
+		sc->sc_regs->led1 = LED_MASK | (*ptr);
+		break;
+	case SCFIOCGLED1:
+		*ptr = sc->sc_regs->led1 & (LED_COLOR_MASK | LED_BLINK_MASK);
+		break;
+	case SCFIOCSLED2:
+		sc->sc_regs->led2 = LED_MASK | (*ptr);
+		break;
+	case SCFIOCGLED2:
+		*ptr = sc->sc_regs->led2 & (LED_COLOR_MASK | LED_BLINK_MASK);
+		break;
+	case SCFIOCSLED7:
+		sc->sc_regs->ssldcr = *ptr;
+		break;
+	case SCFIOCGLED7:
+		*ptr = sc->sc_regs->ssldcr;
+		break;
+	case SCFIOCGROT:
+		*ptr = sc->sc_regs->rssr;
+		break;
+	case SCFIOCSFMCTRL:
+		if ((*ptr) & SCF_FMCTRL_SELROM)
+			sc->sc_regs->fmpcr1 |= FMPCR1_SELROM;
+		else
+			sc->sc_regs->fmpcr1 &= ~FMPCR1_SELROM;
+
+		if ((*ptr) & SCF_FMCTRL_SELBOOT)
+			sc->sc_regs->fmpcr2 |= FMPCR2_SELBOOT;
+		else
+			sc->sc_regs->fmpcr2 &= ~FMPCR2_SELBOOT;
+
+		if ((*ptr) & SCF_FMCTRL_WRITEV)
+			sc->sc_regs->fmpvcr |= FMPVCR_VPP;
+		else
+			sc->sc_regs->fmpvcr &= ~FMPVCR_VPP;
+
+		c = ((*ptr) & SCF_FMCTRL_SELADDR) >> 3;
+		sc->sc_regs->fmpcr1 =
+		    (sc->sc_regs->fmpcr1 & ~FMPCR1_SELADDR) | (c << 1);
+
+		break;
+	case SCFIOCGFMCTRL:
+		c = (sc->sc_regs->fmpcr1 & FMPCR1_SELADDR) << 2;
+		if (sc->sc_regs->fmpcr1 & FMPCR1_SELROM)
+			c |= SCF_FMCTRL_SELROM;
+		if (sc->sc_regs->fmpcr2 & FMPCR2_SELBOOT)
+			c |= SCF_FMCTRL_SELBOOT;
+		if (sc->sc_regs->fmpvcr & FMPVCR_VPP)
+			c |= SCF_FMCTRL_WRITEV;
+		*ptr = c;
+		break;
+	default:
+		error = ENOTTY;
+	}
+
+	return (error);
+}
+
+void
+scfblink(v)
+        void *v;
+{
+	struct scf_softc *sc;
+	int s, avg, hi = 0;
+
+	if (scf_cd.cd_ndevs == 0)
+		return;
+
+	sc = scf_cd.cd_devs[0];
+	if (sc == NULL)
+		return;
+
+	if (sparc_led_blink == 0) {
+		sc->sc_regs->led1 &= ~LED_MASK;
+		sc->sc_regs->led2 &= ~LED_MASK;
+		sc->sc_regs->ssldcr = 0;
+		return;
+	}
+
+	avg = averunnable.ldavg[0] >> FSHIFT;
+	while (avg > 15) {
+		hi = 1;
+		avg >>= 4;
+	}
+
+	s = splhigh();
+	if (sc->sc_tick & 1) {
+		sc->sc_regs->led1 &= ~LED_MASK;
+		sc->sc_regs->led2 |= LED_COLOR_GREEN;
+	}
+	else {
+		sc->sc_regs->led1 |= LED_COLOR_YELLOW;
+		sc->sc_regs->led2 &= ~LED_MASK;
+	}
+	sc->sc_regs->ssldcr = scf_pattern[avg] | (hi ? SSLDCR_P : 0);
+	splx(s);
+
+	sc->sc_tick++;
+
+	s = ((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1);
+	timeout(scfblink, 0, s);
+}
diff --git a/sys/arch/sparc/dev/scfio.h b/sys/arch/sparc/dev/scfio.h
new file mode 100644
index 00000000000..117c88986b0
--- /dev/null
+++ b/sys/arch/sparc/dev/scfio.h
@@ -0,0 +1,78 @@
+/*	$OpenBSD: scfio.h,v 1.1 1999/07/23 19:11:26 jason Exp $	*/
+
+/*
+ * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * This software was developed by Jason L. Wright under contract with
+ * RTMX Incorporated (http://www.rtmx.com).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Jason L. Wright for
+ *	RTMX Incorporated.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * ioctls and flags for sysconfig registers on Force CPU-5V boards.
+ */
+
+/* led1/led2 */
+#define	SCF_LED_COLOR_MASK	0x03	/* color bits */
+#define	SCF_LED_COLOR_OFF	0x00	/* led off */
+#define	SCF_LED_COLOR_GREEN	0x01	/* green led */
+#define	SCF_LED_COLOR_RED	0x02	/* red led */
+#define	SCF_LED_COLOR_YELLOW	0x03	/* yellow led */
+#define	SCF_LED_BLINK_MASK	0x0c	/* blink bits */
+#define	SCF_LED_BLINK_NONE	0x00	/* steady led */
+#define	SCF_LED_BLINK_HALF	0x04	/* blink 1/2 hz */
+#define	SCF_LED_BLINK_ONE	0x08	/* blink 1 hz */
+#define	SCF_LED_BLINK_TWO	0x0c	/* blink 2 hz */
+
+/* 7 segment led */
+#define	SCF_7LED_A		0x01	/* Layout:	*/
+#define	SCF_7LED_B		0x02	/*	AAA	*/
+#define	SCF_7LED_C		0x04	/*     FF BB	*/
+#define	SCF_7LED_D		0x08	/*	GGG	*/
+#define	SCF_7LED_E		0x10	/*     EE CC	*/
+#define	SCF_7LED_F		0x20	/*      DDD  P	*/
+#define	SCF_7LED_G		0x40
+#define	SCF_7LED_P		0x80
+
+/* flash memory control */
+#define	SCF_FMCTRL_SELROM	0x01	/* select boot/user flash */
+#define	SCF_FMCTRL_SELBOOT	0x02	/* select 1st/2nd flash */
+#define	SCF_FMCTRL_WRITEV	0x04	/* turn on write voltage */
+#define	SCF_FMCTRL_SELADDR	0x38	/* address 21:19 bits */
+
+#define	SCFIOCSLED1	_IOW('S', 0x01, u_int8_t)	/* set led1 */
+#define	SCFIOCGLED1	_IOR('S', 0x02, u_int8_t)	/* get led1 */
+#define	SCFIOCSLED2	_IOW('S', 0x03, u_int8_t)	/* set led2 */
+#define	SCFIOCGLED2	_IOR('S', 0x04, u_int8_t)	/* get led2 */
+#define	SCFIOCSLED7	_IOW('S', 0x05, u_int8_t)	/* set 7-segment led */
+#define	SCFIOCGLED7	_IOW('S', 0x06, u_int8_t)	/* get 7-segment led */
+#define	SCFIOCGROT	_IOR('S', 0x07, u_int8_t)	/* get rotary sw */
+#define	SCFIOCSFMCTRL	_IOW('S', 0x08, u_int8_t)	/* set flash ctrl */
+#define	SCFIOCGFMCTRL	_IOR('S', 0x09, u_int8_t)	/* get flash ctrl */
diff --git a/sys/arch/sparc/dev/scfreg.h b/sys/arch/sparc/dev/scfreg.h
new file mode 100644
index 00000000000..882d09bc8f2
--- /dev/null
+++ b/sys/arch/sparc/dev/scfreg.h
@@ -0,0 +1,105 @@
+/*	$OpenBSD: scfreg.h,v 1.1 1999/07/23 19:11:26 jason Exp $	*/
+
+/*
+ * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * This software was developed by Jason L. Wright under contract with
+ * RTMX Incorporated (http://www.rtmx.com).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Jason L. Wright for
+ *	RTMX Incorporated.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+struct scf_regs {
+	volatile u_int8_t	led1;		/* user led 1 control */
+	volatile u_int8_t	led2;		/* user led 2 control */
+	volatile u_int8_t	fmpcr1;		/* flash prog control 1 */
+	volatile u_int8_t	rssr;		/* rotary switch status */
+	volatile u_int8_t	_reserved0[4];	/* unused */
+	volatile u_int8_t	brscr;		/* boot ROM size ctrl */
+	volatile u_int8_t	fmpcr2;		/* flash prog control reg 2 */
+	volatile u_int8_t	fmpvcr;		/* flash prog voltage ctrl */
+	volatile u_int8_t	ssldcr;		/* 7-segment led ctrl */
+	volatile u_int8_t	fmb0;		/* FMB chan 0 data discard */
+	volatile u_int8_t	fmb1;		/* FMB chan 1 data discard */
+	volatile u_int8_t	_reserved1[1];	/* unused */
+	volatile u_int8_t	lcaid;		/* LCA identification */
+};
+
+/* led1/led2: user led 1/led 2 control */
+#define	LED_MASK		0x0f
+#define	LED_COLOR_MASK		0x03	/* color mask */
+#define	LED_COLOR_OFF		0x00	/* led is off */
+#define	LED_COLOR_GREEN		0x01	/* led is green */
+#define	LED_COLOR_RED		0x02	/* led is red */
+#define	LED_COLOR_YELLOW	0x03	/* led is yellow */
+#define	LED_BLINK_MASK		0x0c	/* blink mask */
+#define	LED_BLINK_NONE		0x00	/* led does not blink */
+#define	LED_BLINK_HALF		0x04	/* led blinks at 0.5hz */
+#define	LED_BLINK_ONE		0x08	/* led blinks at 1.0hz */
+#define	LED_BLINK_TWO		0x0c	/* led blinks at 2.0hz */
+
+/* fmpcr1: flash memory programming control register 1 */
+#define	FMPCR1_MASK		0xf0	/* must be or'd with this on write */
+#define	FMPCR1_SELADDR		0x0e	/* address select */
+#define	FMPCR1_SELROM		0x01	/* 0=first,1=second flash memory */
+
+/* rssr: rotary switch status register */
+#define	RSSR_MASK		0x0f	/* value of user rotary switch */
+
+/* brscr: boot ROM size control register */
+/* ??? */
+
+/* fmpcr2: flash memory programming control register 2 */
+#define	FMPCR2_MASK		0xfe	/* must be or'd with this on write */
+#define	FMPCR2_SELBOOT		0x01	/* 0=USER,1=BOOT flash memory */
+
+/* fmpvcr: flash memory programming voltage control register */
+#define	FMPVCR_MASK		0xfe	/* must be or'd with this on write */
+#define	FMPVCR_VPP		0x01	/* 1=prog voltage on, 0 = off */
+
+/* fmb0/fmb1: FMB channel 0/1 data discard status register */
+#define	FMB_MSBVALID	0x01		/* (ro) whether to discard FMB data */
+
+/* ssldcr: seven segment LED display control register */
+/*
+ * Layout:
+ *          AAA
+ *         FF BB
+ *	    GGG
+ *	   EE CC
+ *	    DDD  P
+ */
+#define	SSLDCR_A	0x01
+#define	SSLDCR_B	0x02
+#define	SSLDCR_C	0x04
+#define	SSLDCR_D	0x08
+#define	SSLDCR_E	0x10
+#define	SSLDCR_F	0x20
+#define	SSLDCR_G	0x40
+#define	SSLDCR_P	0x80
diff --git a/sys/arch/sparc/include/autoconf.h b/sys/arch/sparc/include/autoconf.h
index c940919b78c..55b895a1f7a 100644
--- a/sys/arch/sparc/include/autoconf.h
+++ b/sys/arch/sparc/include/autoconf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: autoconf.h,v 1.6 1999/04/18 03:24:27 jason Exp $	*/
+/*	$OpenBSD: autoconf.h,v 1.7 1999/07/23 19:11:27 jason Exp $	*/
 /*	$NetBSD: autoconf.h,v 1.20 1997/05/24 20:03:03 pk Exp $ */
 
 /*
@@ -109,6 +109,16 @@ struct confargs {
 #define BUS_VME32	3
 #define BUS_SBUS	4
 #define BUS_XBOX	5
+#define BUS_FGA		6
+#define BUS_FGA_A16D8	7
+#define BUS_FGA_A16D16	8
+#define BUS_FGA_A16D32	9
+#define BUS_FGA_A24D8	10
+#define BUS_FGA_A24D16	11
+#define BUS_FGA_A24D32	12
+#define BUS_FGA_A32D8	13
+#define BUS_FGA_A32D16	14
+#define BUS_FGA_A32D32	15
 
 /*
  * mapiodev maps an I/O device to a virtual address, returning the address.
diff --git a/sys/arch/sparc/include/conf.h b/sys/arch/sparc/include/conf.h
index 77039f962ca..1dc3d00790e 100644
--- a/sys/arch/sparc/include/conf.h
+++ b/sys/arch/sparc/include/conf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: conf.h,v 1.9 1999/02/01 00:30:43 jason Exp $	*/
+/*	$OpenBSD: conf.h,v 1.10 1999/07/23 19:11:27 jason Exp $	*/
 /*	$NetBSD: conf.h,v 1.8 1996/12/31 07:12:43 mrg Exp $	*/
 
 /*
@@ -109,4 +109,26 @@ cdev_decl(mbpp);
 cdev_decl(stty);
 cdev_decl(sbpp);
 
+/* open, close, ioctl */
+#define	cdev_scf_init(c,n) { \
+	dev_init(c,n,open), dev_init(c,n,close), (dev_type_read((*))) enodev, \
+	(dev_type_write((*))) enodev, dev_init(c,n,ioctl), \
+	(dev_type_stop((*))) nullop, 0, seltrue, \
+	(dev_type_mmap((*))) enodev }
+cdev_decl(scf);
+
+/* open, close, ioctl, read, write */
+#define	cdev_flash_init(c,n) { \
+	dev_init(c,n,open), dev_init(c,n,close), dev_init(c,n,read),	\
+	dev_init(c,n,write), dev_init(c,n,ioctl),			\
+	(dev_type_stop((*))) nullop, 0, seltrue, (dev_type_mmap((*))) enodev }
+cdev_decl(flash);
+
+#define	cdev_fga_init(c,n) { \
+	dev_init(c,n,open), dev_init(c,n,close), (dev_type_read((*))) enodev, \
+	(dev_type_write((*))) enodev, dev_init(c,n,ioctl), \
+	(dev_type_stop((*))) nullop, 0, seltrue, \
+	(dev_type_mmap((*))) enodev }
+cdev_decl(fga);
+
 cdev_decl(ksyms);
diff --git a/sys/arch/sparc/include/cpu.h b/sys/arch/sparc/include/cpu.h
index 4220b274ef7..ce4679565d6 100644
--- a/sys/arch/sparc/include/cpu.h
+++ b/sys/arch/sparc/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.5 1999/01/10 13:34:20 niklas Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.6 1999/07/23 19:11:27 jason Exp $	*/
 /*	$NetBSD: cpu.h,v 1.24 1997/03/15 22:25:15 pk Exp $ */
 
 /*
@@ -176,6 +176,8 @@ void	intr_fasttrap __P((int level, void (*vec)(void)));
 
 /* auxreg.c */
 void led_blink __P((void *));
+/* scf.c */
+void scfblink __P((void *));
 /* disksubr.c */
 struct dkbad;
 int isbad __P((struct dkbad *bt, int, int, int));
diff --git a/sys/arch/sparc/sparc/conf.c b/sys/arch/sparc/sparc/conf.c
index 7ef3f7abcea..16c1ddd4568 100644
--- a/sys/arch/sparc/sparc/conf.c
+++ b/sys/arch/sparc/sparc/conf.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: conf.c,v 1.22 1999/07/18 17:07:49 deraadt Exp $	*/
+/*	$OpenBSD: conf.c,v 1.23 1999/07/23 19:11:27 jason Exp $	*/
 /*	$NetBSD: conf.c,v 1.40 1996/04/11 19:20:03 thorpej Exp $ */
 
 /*
@@ -85,6 +85,9 @@
 #include "bpp.h"
 #include "magma.h"		/* has NMTTY and NMBPP */
 #include "spif.h"		/* has NSTTY and NSBPP */
+#include "scf.h"
+#include "flash.h"
+#include "fga.h"
 
 #ifdef XFS
 #include <xfs/nxfs.h>
@@ -227,17 +230,17 @@ struct cdevsw	cdevsw[] =
 	cdev_notdef(),			/* 95 */
 	cdev_notdef(),			/* 96 */
 	cdev_notdef(),			/* 97 */
-	cdev_notdef(),			/* 98 */
+	cdev_fga_init(NFGA,fga),	/* 98 */
 	cdev_fb_init(NCGFOURTEEN,cgfourteen), /* 99: /dev/cgfourteen */
-	cdev_tty_init(NMTTY,mtty),	/* 100 */
-	cdev_gen_init(NMBPP,mbpp),	/* 101 */
-	cdev_tty_init(NSTTY,stty),	/* 102 */
-	cdev_gen_init(NSBPP,sbpp),	/* 103 */
+	cdev_tty_init(NMTTY,mtty),	/* 100: magma */
+	cdev_gen_init(NMBPP,mbpp),	/* 101: magma */
+	cdev_tty_init(NSTTY,stty),	/* 102: spif */
+	cdev_gen_init(NSBPP,sbpp),	/* 103: spif */
 	cdev_bpp_init(NBPP,bpp),	/* 104: bpp */
 	cdev_bpftun_init(NBPFILTER,bpf),/* 105: packet filter */
 	cdev_disk_init(NRD,rd),		/* 106: ram disk driver */
-	cdev_notdef(),			/* 107 */
-	cdev_notdef(),			/* 108 */
+	cdev_scf_init(NSCF,scf),	/* 107: sysconfig regs */
+	cdev_flash_init(NFLASH,flash),	/* 108: flash memory */
 	cdev_fb_init(NTCX,tcx),		/* 109: /dev/tcx */
 	cdev_disk_init(NVND,vnd),	/* 110: vnode disk driver */
 	cdev_bpftun_init(NTUN,tun),	/* 111: network tunnel */
diff --git a/sys/arch/sparc/sparc/machdep.c b/sys/arch/sparc/sparc/machdep.c
index 603338c2545..e2c5125dc54 100644
--- a/sys/arch/sparc/sparc/machdep.c
+++ b/sys/arch/sparc/sparc/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.37 1999/07/09 21:30:02 art Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.38 1999/07/23 19:11:28 jason Exp $	*/
 /*	$NetBSD: machdep.c,v 1.85 1997/09/12 08:55:02 pk Exp $ */
 
 /*
@@ -98,6 +98,7 @@
 #ifdef SUN4M
 #include <sparc/dev/power.h>
 #include "power.h"
+#include "scf.h"
 #endif
 
 #include "auxreg.h"
@@ -563,7 +564,7 @@ cpu_sysctl(name, namelen, oldp, oldlenp, newp, newlen, p)
 
 	switch (name[0]) {
 	case CPU_LED_BLINK:
-#if (NLED > 0) || (NAUXREG > 0)
+#if (NLED > 0) || (NAUXREG > 0) || (NSCF > 0)
 		oldval = sparc_led_blink;
 		ret = sysctl_int(oldp, oldlenp, newp, newlen,
 		    &sparc_led_blink);
@@ -579,6 +580,9 @@ cpu_sysctl(name, namelen, oldp, oldlenp, newp, newlen, p)
 #if NLED > 0
 			led_cycle((caddr_t *)led_sc);
 #endif
+#if NSCF > 0
+			scfblink((caddr_t *)0);
+#endif
 		}
 
 		return (ret);