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authorOwain Ainsworth <oga@cvs.openbsd.org>2008-11-17 00:45:40 +0000
committerOwain Ainsworth <oga@cvs.openbsd.org>2008-11-17 00:45:40 +0000
commit244fa5b1cfb494b6ab136ca8dda2b5919847ce14 (patch)
treee90fd65f978679429602edf1bd6382448f112368
parentfce1da5397e710f5ceb9ceaa074ba54129dc3117 (diff)
Don't put the buffer counter in a reserved part of the status page.
From intel.
-rw-r--r--sys/dev/pci/drm/i915_dma.c2
-rw-r--r--sys/dev/pci/drm/i915_drv.h17
2 files changed, 11 insertions, 8 deletions
diff --git a/sys/dev/pci/drm/i915_dma.c b/sys/dev/pci/drm/i915_dma.c
index 986d62d7ee4..fc5489a2e90 100644
--- a/sys/dev/pci/drm/i915_dma.c
+++ b/sys/dev/pci/drm/i915_dma.c
@@ -439,7 +439,7 @@ void i915_emit_breadcrumb(struct drm_device *dev)
BEGIN_LP_RING(4);
OUT_RING(MI_STORE_DWORD_INDEX);
- OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
+ OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
OUT_RING(dev_priv->counter);
OUT_RING(0);
ADVANCE_LP_RING();
diff --git a/sys/dev/pci/drm/i915_drv.h b/sys/dev/pci/drm/i915_drv.h
index 6d1d600d8a5..4196d877aeb 100644
--- a/sys/dev/pci/drm/i915_drv.h
+++ b/sys/dev/pci/drm/i915_drv.h
@@ -430,16 +430,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
* MI_STORE_DATA_IMM.
*
* The following dwords have a reserved meaning:
- * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
- * 4: ring 0 head pointer
- * 5: ring 1 head pointer (915-class)
- * 6: ring 2 head pointer (915-class)
+ * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
+ * 0x04: ring 0 head pointer
+ * 0x05: ring 1 head pointer (915-class)
+ * 0x06: ring 2 head pointer (915-class)
+ * 0x10-0x1b: Context status DWords (GM45)
+ * 0x1f: Last written status offset. (GM45)
*
- * The area from dword 0x10 to 0x3ff is available for driver usage.
+ * The area from dword 0x20 to 0x3ff is available for driver usage.
*/
#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
-#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
-#define I915_GEM_HWS_INDEX 0x10
+#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
+#define I915_GEM_HWS_INDEX 0x20
+#define I915_BREADCRUMB_INDEX 0x21
/*
* 3D instructions used by the kernel