a driver for the usb device controller. at the moment it only hardwires the

physical port on a zaurus to the host controller. needs lots of cleanup.

ok drahn@

5 files changed, 356 insertions, 38 deletions

diff --git a/sys/arch/arm/xscale/files.pxa2x0 b/sys/arch/arm/xscale/files.pxa2x0
index 88deff1cd21..0e3d4a1ba67 100644
--- a/sys/arch/arm/xscale/files.pxa2x0
+++ b/sys/arch/arm/xscale/files.pxa2x0
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.pxa2x0,v 1.7 2005/02/12 05:20:25 dlg Exp $
+#	$OpenBSD: files.pxa2x0,v 1.8 2005/02/17 22:10:35 dlg Exp $
 #	$NetBSD: files.pxa2x0,v 1.6 2004/05/01 19:09:14 thorpej Exp $
 #
 # Configuration info for Intel PXA2[51]0 CPU support
@@ -43,8 +43,13 @@ file arch/arm/xscale/pxa2x0_a4x_space.c		pxauart | obio
 file arch/arm/xscale/pxa2x0_a4x_io.S		pxauart | obio
 #defflag	opt_com.h	FFUARTCONSOLE STUARTCONSOLE BTUARTCONSOLE
 
+# PXA27x USB Device Controller
+device	pxaudc
+attach	pxaudc at pxaip
+file	arch/arm/xscale/pxa27x_udc.c		pxaudc
+
 # OHCI USB Controller
-attach ohci at pxaip with pxaohci
+attach	ohci at pxaip with pxaohci
 file	arch/arm/xscale/pxa2x0_ohci.c		pxaohci
 
 # LCD controller
diff --git a/sys/arch/arm/xscale/pxa27x_udc.c b/sys/arch/arm/xscale/pxa27x_udc.c
new file mode 100644
index 00000000000..3dfe4db2957
--- /dev/null
+++ b/sys/arch/arm/xscale/pxa27x_udc.c
@@ -0,0 +1,165 @@
+/*	$OpenBSD: pxa27x_udc.c,v 1.1 2005/02/17 22:10:35 dlg Exp $ */
+
+/*
+ * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/kthread.h>
+
+#include <machine/intr.h>
+#include <machine/bus.h>
+
+#include <arm/xscale/pxa2x0reg.h>
+#include <arm/xscale/pxa2x0var.h>
+#include <arm/xscale/pxa2x0_gpio.h>
+
+#include <arm/xscale/pxa27x_udcreg.h>
+
+int	pxaudc_match(struct device *, void *, void *);
+void	pxaudc_attach(struct device *, struct device *, void *);
+int	pxaudc_detach(struct device *, int);
+
+void	pxaudc_intr(void *);
+
+struct pxaudc_softc {
+	struct device		sc_dev;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+	bus_size_t		sc_size;
+	void			*sc_ih;
+	int			sc_intr;
+};
+
+struct cfattach pxaudc_ca = {
+        sizeof(struct pxaudc_softc), pxaudc_match, pxaudc_attach,
+	pxaudc_detach
+};
+
+struct cfdriver pxaudc_cd = {
+        NULL, "pxaudc", DV_DULL
+};
+
+int
+pxaudc_match(struct device *parent, void *match, void *aux)
+{
+	if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) != CPU_ID_PXA27X)
+		return (0);
+
+	return (1);
+}
+int pxaudc_intr2(void *);
+int
+pxaudc_intr2(void *arg)
+{
+	printf("thing: %d\n", pxa2x0_gpio_get_bit(41));
+	return (1);
+}
+
+void pxaudc_intr1(void *);
+void
+pxaudc_intr1(void *arg)
+{
+	while (1) {
+		printf("thingy: %d\n", pxa2x0_gpio_get_bit(41));
+		tsleep(arg, PZERO, "tsleep", hz);
+	}
+}
+void
+pxaudc_intr(void *arg)
+{
+//	struct pxaudc_softc		*sc = (struct pxaudc_softc *)arg;
+
+	kthread_create(pxaudc_intr1, arg, NULL, "pxausb");
+}
+
+void
+pxaudc_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct pxaudc_softc		*sc = (struct pxaudc_softc *)self;
+
+//	pxa2x0_gpio_set_function(41, GPIO_ALT_FN_2_IN);
+//	pxa2x0_gpio_set_dir(41, GPIO_OUT);
+//	printf("thing: %d\n", pxa2x0_gpio_get_bit(41));
+//	pxa2x0_gpio_set_function(41, GPIO_OUT);
+//	pxa2x0_gpio_intr_establish(41, IST_EDGE_BOTH, IPL_BIO,
+//	    pxaudc_intr2, sc, sc->sc_dev.dv_xname);
+
+//	kthread_create_deferred(pxaudc_intr, sc);
+
+
+	struct pxaip_attach_args	*pxa = aux;
+	u_int32_t			hr;
+
+	sc->sc_iot = pxa->pxa_iot;
+	sc->sc_intr = pxa->pxa_intr;
+	sc->sc_ih = NULL;
+	sc->sc_size = 0;
+
+	printf(": disabling USB Device Controller\n");
+
+	/* Map I/O space */
+	if (bus_space_map(sc->sc_iot, PXA2X0_USBDC_BASE, PXA2X0_USBDC_SIZE, 0,
+	    &sc->sc_ioh)) {
+		printf(": cannot map mem space\n");
+		return;
+	}
+	sc->sc_size = PXA2X0_USBDC_SIZE;
+
+	bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_size,
+	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
+
+	pxa2x0_clkman_config(CKEN_USBDC, 0);
+
+	/* disable the controller */
+	hr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, USBDC_UDCCR);
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, USBDC_UDCCR,
+	    hr & ~USBDC_UDCCR_UDE);
+
+	hr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, USBDC_UDCICR1);
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, USBDC_UDCICR1,
+	    hr | USBDC_UDCICR1_IERS);
+
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, USBDC_UP2OCR, 0);
+	hr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, USBDC_UP2OCR);
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, USBDC_UP2OCR,
+	    hr | USBDC_UP2OCR_HXS);
+	hr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, USBDC_UP2OCR);
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, USBDC_UP2OCR,
+	    hr | USBDC_UP2OCR_HXOE);
+	hr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, USBDC_UP2OCR);
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, USBDC_UP2OCR,
+	    hr | USBDC_UP2OCR_DPPDE|USBDC_UP2OCR_DMPDE);
+
+	pxa2x0_gpio_set_bit(37);
+
+	//pxa2x0_clkman_config(CKEN_USBHC, 0);
+}
+
+int
+pxaudc_detach(struct device *self, int flags)
+{
+	struct pxaudc_softc		*sc = (struct pxaudc_softc *)self;
+
+	if (sc->sc_size) {
+		bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size);
+		sc->sc_size = 0;
+	}
+
+	return (0);
+}
diff --git a/sys/arch/arm/xscale/pxa27x_udcreg.h b/sys/arch/arm/xscale/pxa27x_udcreg.h
new file mode 100644
index 00000000000..f54a0e42296
--- /dev/null
+++ b/sys/arch/arm/xscale/pxa27x_udcreg.h
@@ -0,0 +1,152 @@
+/*	$OpenBSD: pxa27x_udcreg.h,v 1.1 2005/02/17 22:10:35 dlg Exp $ */
+
+/*
+ * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Register Descriptions for the USB Device Controller 
+ *
+ * Reference:
+ *  Intel(r) PXA27x Processor Family
+ *   Developer's Manual
+ *  (2800002.pdf)
+ */
+
+#ifndef _ARM_XSCALE_PXA27X_UDCREG_H_
+#define _ARM_XSCALE_PXA27X_UDCREG_H_
+
+#define USBDC_UDCCR	0x0000  /* UDC Control Register */
+#define  USBDC_UDCCR_UDE	(1<<0)	/* UDC Enable */
+#define  USBDC_UDCCR_UDA	(1<<1)	/* UDC Active */
+#define  USBDC_UDCCR_UDR	(1<<2)	/* UDC Resume */
+#define  USBDC_UDCCR_EMCE	(1<<3)	/* Endpoint Mem Config Error */
+#define  USBDC_UDCCR_SMAC	(1<<4)	/* Switch EndPt Mem to Active Config */
+#define  USBDC_UDCCR_AAISN	(7<<5)	/* Active UDC Alt Iface Setting */
+#define  USBDC_UDCCR_AIN	(7<<8)	/* Active UDC Iface */
+#define  USBDC_UDCCR_ACN	(7<<11)	/* Active UDC Config */
+#define  USBDC_UDCCR_DWRE	(1<<16)	/* Device Remote Wake-Up Feature */
+#define  USBDC_UDCCR_BHNP	(1<<28)	/* B-Device Host Neg Proto Enable */
+#define  USBDC_UDCCR_AHNP	(1<<29)	/* A-Device Host NEg Proto Support */
+#define  USBDC_UDCCR_AALTHNP	(1<<30) /* A-Dev Alt Host Neg Proto Port Sup */
+#define  USBDC_UDCCR_OEN	(1<<31)	/* On-The-Go Enable */
+#define USBDC_UDCICR0	0x0004	/* UDC Interrupt Control Register 0 */
+#define  USBDC_UDCICR0_IE(n)	(3<<(n)) /* Interrupt Enables */
+#define USBDC_UDCICR1	0x0008	/* UDC Interrupt Control Register 1 */
+#define  USBDC_UDCICR1_IE(n)	(3<<(n)) /* Interrupt Enables */
+#define  USBDC_UDCICR1_IERS	(1<<27)	/* Interrupt Enable Reset */
+#define  USBDC_UDCICR1_IESU	(1<<28)	/* Interrupt Enable Suspend */
+#define  USBDC_UDCICR1_IERU	(1<<29)	/* Interrupt Enable Resume */
+#define  USBDC_UDCICR1_IESOF	(1<<30)	/* Interrupt Enable Start of Frame */
+#define  USBDC_UDCICR1_IECC	(1<<31)	/* Interrupt Enable Config Change */
+#define USBDC_UDCISR0	0x000c	/* UDC Interrupt Status Register 0 */
+#define  USBDC_UDCISR0_IR(n)	(3<<(n)) /* Interrupt Requests */
+#define USBDC_UDCISR1	0x0010	/* UDC Interrupt Status Register 1 */
+#define  USBDC_UDCISR1_IR(n)	(3<<(n)) /* Interrupt Requests */
+#define  USBDC_UDCISR1_IRRS	(1<<27)	/* Interrupt Enable Reset */
+#define  USBDC_UDCISR1_IRSU	(1<<28)	/* Interrupt Enable Suspend */
+#define  USBDC_UDCISR1_IRRU	(1<<29)	/* Interrupt Enable Resume */
+#define  USBDC_UDCISR1_IRSOF	(1<<30)	/* Interrupt Enable Start of Frame */
+#define  USBDC_UDCISR1_IRCC	(1<<31)	/* Interrupt Enable Config Change */
+#define USBDC_UDCFNR	0x0014	/* UDC Frame Number Register */
+#define  USBDC_UDCFNR_FN	(1023<<0) /* Frame Number */
+#define USBDC_UDCOTGICR	0x0018	/* UDC OTG Interrupt Control Register */
+#define  USBDC_UDCOTGICR_IEIDF	(1<<0)	/* OTG ID Change Fall Intr En */
+#define  USBDC_UDCOTGICR_IEIDR	(1<<1)	/* OTG ID Change Ris Intr En */
+#define  USBDC_UDCOTGICR_IESDF	(1<<2)	/* OTG A-Dev SRP Detect Fall Intr En */
+#define  USBDC_UDCOTGICR_IESDR	(1<<3)	/* OTG A-Dev SRP Detect Ris Intr En */
+#define  USBDC_UDCOTGICR_IESVF	(1<<4)	/* OTG Session Valid Fall Intr En */
+#define  USBDC_UDCOTGICR_IESVR	(1<<5)	/* OTG Session Valid Ris Intr En */
+#define  USBDC_UDCOTGICR_IEVV44F (1<<6)	/* OTG Vbus Valid 4.4V Fall Intr En */
+#define  USBDC_UDCOTGICR_IEVV44R (1<<7)	/* OTG Vbus Valid 4.4V Ris Intr En */
+#define  USBDC_UDCOTGICR_IEVV40F (1<<8)	/* OTG Vbus Valid 4.0V Fall Intr En */
+#define  USBDC_UDCOTGICR_IEVV40R (1<<9)	/* OTG Vbus Valid 4.0V Ris Intr En */
+#define  USBDC_UDCOTGICR_IEXF	(1<<16)	/* Extern Transceiver Intr Fall En */
+#define  USBDC_UDCOTGICR_IEXR	(1<<17)	/* Extern Transceiver Intr Ris En */
+#define  USBDC_UDCOTGICR_IESF	(1<<24)	/* OTG SET_FEATURE Command Recvd */
+#define USBDC_UDCOTGISR	0x001c	/* UDC OTG Interrupt Status Register */
+#define  USBDC_UDCOTGISR_IRIDF	(1<<0)	/* OTG ID Change Fall Intr Req */
+#define  USBDC_UDCOTGISR_IRIDR	(1<<1)	/* OTG ID Change Ris Intr Req */
+#define  USBDC_UDCOTGISR_IRSDF	(1<<2)	/* OTG A-Dev SRP Detect Fall Intr Req */
+#define  USBDC_UDCOTGISR_IRSDR	(1<<3)	/* OTG A-Dev SRP Detect Ris Intr Req */
+#define  USBDC_UDCOTGISR_IRSVF	(1<<4)	/* OTG Session Valid Fall Intr Req */
+#define  USBDC_UDCOTGISR_IRSVR	(1<<5)	/* OTG Session Valid Ris Intr Req */
+#define  USBDC_UDCOTGISR_IRVV44F (1<<6)	/* OTG Vbus Valid 4.4V Fall Intr Req */
+#define  USBDC_UDCOTGISR_IRVV44R (1<<7)	/* OTG Vbus Valid 4.4V Ris Intr Req */
+#define  USBDC_UDCOTGISR_IRVV40F (1<<8)	/* OTG Vbus Valid 4.0V Fall Intr Req */
+#define  USBDC_UDCOTGISR_IRVV40R (1<<9)	/* OTG Vbus Valid 4.0V Ris Intr Req */
+#define  USBDC_UDCOTGISR_IRXF	(1<<16)	/* Extern Transceiver Intr Fall Req */
+#define  USBDC_UDCOTGISR_IRXR	(1<<17)	/* Extern Transceiver Intr Ris Req */
+#define  USBDC_UDCOTGISR_IRSF	(1<<24)	/* OTG SET_FEATURE Command Recvd */
+#define USBDC_UP2OCR	0x0020	/* USB Port 2 Output Control Register */
+#define  USBDC_UP2OCR_CPVEN	(1<<0)	/* Charge Pump Vbus Enable */
+#define  USBDC_UP2OCR_CPVPE	(1<<1)	/* Charge Pump Vbus Pulse Enable */
+#define  USBDC_UP2OCR_DPPDE	(1<<2)	/* Host Transc D+ Pull Down En */
+#define  USBDC_UP2OCR_DMPDE	(1<<3)	/* Host Transc D- Pull Down En */
+#define  USBDC_UP2OCR_DPPUE	(1<<4)	/* Host Transc D+ Pull Up En */
+#define  USBDC_UP2OCR_DMPUE	(1<<5)	/* Host Transc D- Pull Up En */
+#define  USBDC_UP2OCR_DPPUBE	(1<<6)	/* Host Transc D+ Pull Up Bypass En */
+#define  USBDC_UP2OCR_DMPUBE	(1<<7)	/* Host Transc D- Pull Up Bypass En */
+#define  USBDC_UP2OCR_EXSP	(1<<8)	/* External Transc Speed Control */
+#define  USBDC_UP2OCR_EXSUS	(1<<9)	/* External Transc Suspend Control */
+#define  USBDC_UP2OCR_IDON	(1<<10)	/* OTG ID Read Enable */
+#define  USBDC_UP2OCR_HXS	(1<<16)	/* Host Transc Output Select */
+#define  USBDC_UP2OCR_HXOE	(1<<17)	/* Host Transc Output Enable */
+#define  USBDC_UP2OCR_SEOS	(7<<24)	/* Single-Ended Output Select */
+#define USBDC_UP3OCR	0x0024	/* USB Port 3 Output Control Register */
+#define  USBDC_UP3OCR_CFG	(3<<0)	/* Host Port Configuration */
+/* 0x0028 to 0x00fc is reserved */
+#define USBDC_UDCCSR0	0x0100	/* UDC Endpoint 0 Control/Status Registers */
+#define  USBDC_UDCCSR0_OPC	(1<<0)	/* OUT Packet Complete */
+#define  USBDC_UDCCSR0_IPR	(1<<1)	/* IN Packet Ready */
+#define  USBDC_UDCCSR0_FTF	(1<<2)	/* Flush Transmit FIFO */
+#define  USBDC_UDCCSR0_DME	(1<<3)	/* DMA Enable */
+#define  USBDC_UDCCSR0_SST	(1<<4)	/* Sent Stall */
+#define  USBDC_UDCCSR0_FST	(1<<5)	/* Force Stall */
+#define  USBDC_UDCCSR0_RNE	(1<<6)	/* Receive FIFO Not Empty */
+#define  USBDC_UDCCSR0_SA	(1<<7)	/* Setup Active */
+#define  USBDC_UDCCSR0_AREN	(1<<8)	/* ACK Response Enable */
+#define  USBDC_UDCCSR0_ACM	(1<<9)	/* ACK Control Mode */
+#define USBDC_UDCCSR(n)	(0x0100+4*(n)) /* UDC Control/Status Registers */
+#define  USBDC_UDCCSR_FS	(1<<0)	/* FIFO Needs Service */
+#define  USBDC_UDCCSR_PC	(1<<1)	/* Packet Complete */
+#define  USBDC_UDCCSR_TRN	(1<<2)	/* Tx/Rx NAK */
+#define  USBDC_UDCCSR_DME	(1<<3)	/* DMA Enable */
+#define  USBDC_UDCCSR_SST	(1<<4)	/* Sent STALL */
+#define  USBDC_UDCCSR_FST	(1<<5)	/* Force STALL */
+#define  USBDC_UDCCSR_BNE	(1<<6)	/* OUT: Buffer Not Empty */
+#define  USBDC_UDCCSR_BNF	(1<<6)	/* IN: Buffer Not Full */
+#define  USBDC_UDCCSR_SP	(1<<7)	/* Short Packet Control/Status */
+#define  USBDC_UDCCSR_FEF	(1<<8)	/* Flush Endpoint FIFO */
+#define  USBDC_UDCCSR_DPE	(1<<9)	/* Data Packet Empty (async EP only) */
+/* 0x0160 to 0x01fc is reserved */
+#define USBDC_UDCBCR(n)	(0x0200+4*(n)) /* UDC Byte Count Registers */
+#define  USBDC_UDCBCR_BC	(1023<<0) /* Byte Count */
+/* 0x0260 to 0x02fc is reserved */
+#define USBDC_UDCDR(n)	(0x0300+4*(n))	/* UDC Data Registers */
+/* 0x0360 to 0x03fc is reserved */
+/* 0x0400 is reserved */
+#define USBDC_UDCECR(n)	(0x0400+4*(n)) /* UDC Configuration Registers */
+#define  USBDC_UDCECR_EE	(1<<0)	/* Endpoint Enable */
+#define  USBDC_UDCECR_DE	(1<<1)	/* Double-Buffering Enable */
+#define  USBDC_UDCECR_MPE	(1023<<2) /* Maximum Packet Size */
+#define  USBDC_UDCECR_ED	(1<<12)	/* USB Endpoint Direction */
+#define  USBDC_UDCECR_ET	(3<<13)	/* USB Enpoint Type */
+#define  USBDC_UDCECR_EN	(15<<15) /* Endpoint Number */
+#define  USBDC_UDCECR_AISN	(7<<19)	/* Alternate Interface Number */
+#define  USBDC_UDCECR_IN	(7<<22)	/* Interface Number */
+#define  USBDC_UDCECR_CN	(3<<25)	/* Configuration Number */
+
+#endif /* _ARM_XSCALE_PXA27X_UDCREG_H_ */
diff --git a/sys/arch/arm/xscale/pxa2x0_ohci.c b/sys/arch/arm/xscale/pxa2x0_ohci.c
index 13954d31b4d..a8a321e3041 100644
--- a/sys/arch/arm/xscale/pxa2x0_ohci.c
+++ b/sys/arch/arm/xscale/pxa2x0_ohci.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0_ohci.c,v 1.8 2005/02/14 13:55:20 dlg Exp $ */
+/*	$OpenBSD: pxa2x0_ohci.c,v 1.9 2005/02/17 22:10:35 dlg Exp $ */
 
 /*
  * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
@@ -26,6 +26,7 @@
 
 #include <arm/xscale/pxa2x0reg.h>
 #include <arm/xscale/pxa2x0var.h>
+#include <arm/xscale/pxa2x0_gpio.h>
 
 #include <dev/usb/usb.h>
 #include <dev/usb/usbdi.h>
@@ -42,6 +43,7 @@ int	pxaohci_detach(struct device *, int);
 struct pxaohci_softc {
 	ohci_softc_t	sc;
 	void		*sc_ih;
+	void		*sc_gpioih;
 	int		sc_intr;
 };
 
@@ -59,6 +61,15 @@ pxaohci_match(struct device *parent, void *match, void *aux)
 	return (1);
 }
 
+int pxaohci_intr(void *);
+int
+pxaohci_intr(void *arg)
+{
+
+	printf("register: %d\n", pxa2x0_gpio_get_bit(41));
+	return (ohci_intr(arg));
+}
+
 void
 pxaohci_attach(struct device *parent, struct device *self, void *aux)
 {
@@ -112,14 +123,15 @@ pxaohci_attach(struct device *parent, struct device *self, void *aux)
 	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
 	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
 	    (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE));
+	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
+	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
+	    (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSEP2));
 
 	/* Disable interrupts, so we don't get any spurious ones. */
 	bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
 	    OHCI_MIE);
 
 	/* XXX splusb? */
-	sc->sc_ih = pxa2x0_intr_establish(sc->sc_intr, IPL_USB, ohci_intr, sc,
-	    sc->sc.sc_bus.bdev.dv_xname);
 
 	strlcpy(sc->sc.sc_vendor, "PXA27x", sizeof(sc->sc.sc_vendor));
 
@@ -136,6 +148,15 @@ pxaohci_attach(struct device *parent, struct device *self, void *aux)
 	}
 	/* XXX splx(s) usb? */
 
+	sc->sc_ih = pxa2x0_intr_establish(sc->sc_intr, IPL_USB, ohci_intr, sc,
+	    sc->sc.sc_bus.bdev.dv_xname);
+
+        pxa2x0_gpio_set_function(35, GPIO_ALT_FN_2_IN);
+        pxa2x0_gpio_set_function(37, GPIO_ALT_FN_1_OUT);
+        pxa2x0_gpio_set_function(41, GPIO_ALT_FN_2_IN);
+	sc->sc_gpioih = pxa2x0_gpio_intr_establish(41, IST_EDGE_BOTH, IPL_BIO,
+	    ohci_intr, sc, sc->sc.sc_bus.bdev.dv_xname);
+
 	sc->sc.sc_child = config_found((void *) sc, &sc->sc.sc_bus,
 	    usbctlprint);
 }
@@ -151,6 +172,11 @@ pxaohci_detach(struct device *self, int flags)
 	if (rv)
 		return (rv);
 
+	if (sc->sc_gpioih != NULL) {
+		pxa2x0_gpio_intr_disestablish(sc->sc_gpioih);
+		sc->sc_gpioih = NULL;
+	}
+
 	if (sc->sc_ih != NULL) {
 		pxa2x0_intr_disestablish(sc->sc_ih);
 		sc->sc_ih = NULL;
diff --git a/sys/arch/arm/xscale/pxa2x0reg.h b/sys/arch/arm/xscale/pxa2x0reg.h
index 2de12f77444..cd0c053c352 100644
--- a/sys/arch/arm/xscale/pxa2x0reg.h
+++ b/sys/arch/arm/xscale/pxa2x0reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0reg.h,v 1.10 2005/02/12 06:20:21 dlg Exp $ */
+/*	$OpenBSD: pxa2x0reg.h,v 1.11 2005/02/17 22:10:35 dlg Exp $ */
 /* $NetBSD: pxa2x0reg.h,v 1.4 2003/06/11 20:43:01 scw Exp $ */
 
 /*
@@ -93,7 +93,7 @@
 #define PXA2X0_AC97_BASE	0x40500000
 #define PXA2X0_AC97_SIZE	0x600
 #define PXA2X0_USBDC_BASE 	0x40600000 /* USB Client */
-#define PXA2X0_USBDC_SIZE 	0x0e04
+#define PXA2X0_USBDC_SIZE 	0x0460
 #define PXA2X0_STUART_BASE	0x40700000 /* Standard UART */
 #define PXA2X0_ICP_BASE 	0x40800000
 #define PXA2X0_RTC_BASE 	0x40900000
@@ -621,38 +621,8 @@ struct pxa2x0_dma_desc {
 #define	AC97_CODEC_BASE(c)	(AC97_PRIAUDIO + ((c) * 0x100))
 
 /*
- * USB device controller
+ * USB device controller differs between pxa255 and pxa27x, defined seperately
  */
-#define USBDC_UDCCR	0x0000  /* UDC control register    */
-#define USBDC_UDCCS(n)	(0x0010+4*(n))  /* Endpoint Control/Status Registers */
-#define USBDC_UICR0	0x0050  /* UDC Interrupt Control Register 0  */
-#define USBDC_UICR1	0x0054  /* UDC Interrupt Control Register 1  */
-#define USBDC_USIR0	0x0058  /* UDC Status Interrupt Register 0  */
-#define USBDC_USIR1	0x005C  /* UDC Status Interrupt Register 1  */
-#define USBDC_UFNHR	0x0060  /* UDC Frame Number Register High  */
-#define USBDC_UFNLR	0x0064  /* UDC Frame Number Register Low  */
-#define USBDC_UBCR2	0x0068  /* UDC Byte Count Register 2  */
-#define USBDC_UBCR4	0x006C  /* UDC Byte Count Register 4  */
-#define USBDC_UBCR7	0x0070  /* UDC Byte Count Register 7  */
-#define USBDC_UBCR9	0x0074  /* UDC Byte Count Register 9  */
-#define USBDC_UBCR12	0x0078  /* UDC Byte Count Register 12  */
-#define USBDC_UBCR14	0x007C  /* UDC Byte Count Register 14  */
-#define USBDC_UDDR0	0x0080  /* UDC Endpoint 0 Data Register  */
-#define USBDC_UDDR1	0x0100  /* UDC Endpoint 1 Data Register  */
-#define USBDC_UDDR2	0x0180  /* UDC Endpoint 2 Data Register  */
-#define USBDC_UDDR3	0x0200  /* UDC Endpoint 3 Data Register  */
-#define USBDC_UDDR4	0x0400  /* UDC Endpoint 4 Data Register  */
-#define USBDC_UDDR5	0x00A0  /* UDC Endpoint 5 Data Register  */
-#define USBDC_UDDR6	0x0600  /* UDC Endpoint 6 Data Register  */
-#define USBDC_UDDR7	0x0680  /* UDC Endpoint 7 Data Register  */
-#define USBDC_UDDR8	0x0700  /* UDC Endpoint 8 Data Register  */
-#define USBDC_UDDR9	0x0900  /* UDC Endpoint 9 Data Register  */
-#define USBDC_UDDR10	0x00C0  /* UDC Endpoint 10 Data Register  */
-#define USBDC_UDDR11	0x0B00  /* UDC Endpoint 11 Data Register  */
-#define USBDC_UDDR12	0x0B80  /* UDC Endpoint 12 Data Register  */
-#define USBDC_UDDR13	0x0C00  /* UDC Endpoint 13 Data Register  */
-#define USBDC_UDDR14	0x0E00  /* UDC Endpoint 14 Data Register  */
-#define USBDC_UDDR15	0x00E0  /* UDC Endpoint 15 Data Register  */
 
 /*
  * USB Host Controller