Add the remaining support code for 4th gen Intel Core/Haswell graphics

and match the same pci devices Linux does.  Untested for lack of
hardware but should work.  Note that 3D/OpenGL won't work until
we update to a newer version of Mesa, which can't happen until
the Radeon KMS work is ready.

ok deraadt@

2 files changed, 259 insertions, 2 deletions

diff --git a/sys/dev/pci/agp_i810.c b/sys/dev/pci/agp_i810.c
index 76af84f37cc..2e288ceefb6 100644
--- a/sys/dev/pci/agp_i810.c
+++ b/sys/dev/pci/agp_i810.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: agp_i810.c,v 1.77 2013/05/15 10:24:36 jsg Exp $	*/
+/*	$OpenBSD: agp_i810.c,v 1.78 2013/06/06 16:14:26 jsg Exp $	*/
 
 /*-
  * Copyright (c) 2000 Doug Rabson
@@ -61,6 +61,7 @@
 #define	INTEL_COHERENT	0x6	
 
 #define GEN6_PTE_UNCACHED		(1 << 1)
+#define HSW_PTE_UNCACHED		(0)
 #define GEN6_PTE_CACHE_LLC		(2 << 1)
 #define GEN6_PTE_CACHE_LLC_MLC		(3 << 1)
 
@@ -77,6 +78,7 @@ enum {
 	CHIP_IRONLAKE	= 9,	/* Clarkdale/Arrandale */
 	CHIP_SANDYBRIDGE=10,	/* Sandybridge */
 	CHIP_IVYBRIDGE	=11,	/* Ivybridge */
+	CHIP_HASWELL	=12,	/* Haswell */
 };
 
 struct agp_i810_softc {
@@ -219,6 +221,67 @@ agp_i810_get_chiptype(struct pci_attach_args *pa)
 	case PCI_PRODUCT_INTEL_CORE3G_M_GT2:
 	case PCI_PRODUCT_INTEL_CORE3G_S_GT2:
 		return (CHIP_IVYBRIDGE);
+	case PCI_PRODUCT_INTEL_CORE4G_D_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_D_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_D_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_S_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_S_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_S_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_M_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_M_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_M_GT2_2:
+	case PCI_PRODUCT_INTEL_CORE4G_R_GT1_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_GT2_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_GT3_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_GT1_2:
+	case PCI_PRODUCT_INTEL_CORE4G_R_GT2_2:
+	case PCI_PRODUCT_INTEL_CORE4G_R_GT3_2:
+	case PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_2:
+	case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_2:
+	case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_2:
+	case PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_2:
+	case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_2:
+	case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_2:
+	case PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT1:
+	case PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT2:
+	case PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT3:
+	case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_1:
+	case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_2:
+	case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_2:
+	case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_2:
+		return (CHIP_HASWELL);
 		break;
 	}
 	
@@ -279,6 +342,7 @@ agp_i810_attach(struct device *parent, struct device *self, void *aux)
 	case CHIP_IRONLAKE:
 	case CHIP_SANDYBRIDGE:
 	case CHIP_IVYBRIDGE:
+	case CHIP_HASWELL:
 		gmaddr = AGP_I965_GMADR;
 		mmaddr = AGP_I965_MMADR;
 		memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT;
@@ -512,6 +576,7 @@ agp_i810_attach(struct device *parent, struct device *self, void *aux)
 
 	case CHIP_SANDYBRIDGE:
 	case CHIP_IVYBRIDGE:
+	case CHIP_HASWELL:
 		/*
 		 * Even though stolen memory exists on these machines,
 		 * it isn't necessarily mapped into the aperture.
@@ -580,6 +645,7 @@ agp_i810_activate(struct device *arg, int act)
 	case CHIP_IRONLAKE:
 	case CHIP_SANDYBRIDGE:
 	case CHIP_IVYBRIDGE:
+	case CHIP_HASWELL:
 		offset = AGP_G4X_GTT;
 		break;
 	default:
@@ -678,6 +744,15 @@ agp_i810_bind_page(void *sc, bus_addr_t offset, paddr_t physical, int flags)
 		if (flags & BUS_DMA_GTT_CACHE_LLC_MLC)
 			physical |= GEN6_PTE_CACHE_LLC_MLC;
 		break;
+	case CHIP_HASWELL:
+		if (flags & BUS_DMA_GTT_NOCACHE)
+			physical |= HSW_PTE_UNCACHED;
+		if (flags & BUS_DMA_GTT_CACHE_LLC)
+			physical |= GEN6_PTE_CACHE_LLC;
+		/* Haswell doesn't set L3 this way */
+		if (flags & BUS_DMA_GTT_CACHE_LLC_MLC)
+			physical |= GEN6_PTE_CACHE_LLC;
+		break;
 	default:
 		if (flags & BUS_DMA_COHERENT)
 			physical |= INTEL_COHERENT;
@@ -912,6 +987,7 @@ intagp_write_gtt(struct agp_i810_softc *isc, bus_size_t off, paddr_t v)
 		/* gen6+ can do 40 bit addressing */
 		case CHIP_SANDYBRIDGE:
 		case CHIP_IVYBRIDGE:
+		case CHIP_HASWELL:
 			pte |= (v & 0x000000ff00000000ULL) >> 28;
 			break;
 		}
@@ -934,6 +1010,7 @@ intagp_write_gtt(struct agp_i810_softc *isc, bus_size_t off, paddr_t v)
 	case CHIP_IRONLAKE:
 	case CHIP_SANDYBRIDGE:
 	case CHIP_IVYBRIDGE:
+	case CHIP_HASWELL:
 		baseoff = AGP_G4X_GTT;
 		break;
 	default:
diff --git a/sys/dev/pci/drm/i915/i915_drv.c b/sys/dev/pci/drm/i915/i915_drv.c
index ae5d214d42b..67b939f43e5 100644
--- a/sys/dev/pci/drm/i915/i915_drv.c
+++ b/sys/dev/pci/drm/i915/i915_drv.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: i915_drv.c,v 1.32 2013/06/01 02:03:30 kettenis Exp $ */
+/* $OpenBSD: i915_drv.c,v 1.33 2013/06/06 16:14:26 jsg Exp $ */
 /*
  * Copyright (c) 2008-2009 Owain G. Ainsworth <oga@openbsd.org>
  *
@@ -356,6 +356,66 @@ const static struct drm_pcidev inteldrm_pciidlist[] = {
 	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_D_GT2,	0 },
 	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_M_GT2,	0 },
 	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_S_GT2,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT2_2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT1_1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT2_1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT3_1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT1_2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT2_2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT3_2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_1,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_1,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_1,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_2,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_2,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_2,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_1,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_1,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_1,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_2,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_2,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_2,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT1,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT2,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT3,		0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_1,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_1,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_1,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_2,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_2,	0 },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_2,	0 },
 	{0, 0, 0}
 };
 
@@ -452,6 +512,126 @@ static const struct intel_gfx_device_id {
 	    &intel_ivybridge_m_info },
 	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_S_GT2,
 	    &intel_ivybridge_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT1, /* GT1 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT2, /* GT2 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT3, /* GT3 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT1, /* GT1 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT2, /* GT2 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT3, /* GT3 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT1, /* GT1 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT2, /* GT2 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT2_2, /* GT2 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT1_1, /* GT1 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT2_1, /* GT2 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT3_1, /* GT3 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT1_2, /* GT1 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT2_2, /* GT2 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT3_2, /* GT3 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT1, /* SDV GT1 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT2, /* SDV GT2 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT3, /* SDV GT3 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT1, /* SDV GT1 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT2, /* SDV GT2 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT3, /* SDV GT3 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT1, /* SDV GT1 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT2, /* SDV GT2 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT3, /* SDV GT3 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_1, /* SDV GT1 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_1, /* SDV GT2 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_1, /* SDV GT3 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_2, /* SDV GT1 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_2, /* SDV GT2 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_2, /* SDV GT3 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT1, /* ULT GT1 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT2, /* ULT GT2 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT3, /* ULT GT3 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT1, /* ULT GT1 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT2, /* ULT GT2 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT3, /* ULT GT3 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT1, /* ULT GT1 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT2, /* ULT GT2 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT3, /* ULT GT3 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_1, /* ULT GT1 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_1, /* ULT GT2 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_1, /* ULT GT3 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_2, /* ULT GT1 reserved */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_2, /* ULT GT2 reserved */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_2, /* ULT GT3 reserved */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT1, /* CRW GT1 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT2, /* CRW GT2 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT3, /* CRW GT3 desktop */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT1, /* CRW GT1 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT2, /* CRW GT2 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT3, /* CRW GT3 server */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT1, /* CRW GT1 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT2, /* CRW GT2 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT3, /* CRW GT3 mobile */
+	    &intel_haswell_m_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_1, /* CRW GT1 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_1, /* CRW GT2 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_1, /* CRW GT3 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_2, /* CRW GT1 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_2, /* CRW GT2 reserved */
+	    &intel_haswell_d_info },
+	{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_2, /* CRW GT3 reserved */
+	    &intel_haswell_d_info },
 	{0, 0, NULL}
 };