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authorDavid Gwynne <dlg@cvs.openbsd.org>2006-06-01 20:05:25 +0000
committerDavid Gwynne <dlg@cvs.openbsd.org>2006-06-01 20:05:25 +0000
commit3867065e49643137d0ce04043776039654c3ae36 (patch)
tree4f1e433ab63bf758f9678372632b3506fba26634
parent4c5f17da889d432d3ea461cdbf574141e513f32e (diff)
fix some macros
-rw-r--r--sys/dev/ic/mpireg.h28
1 files changed, 17 insertions, 11 deletions
diff --git a/sys/dev/ic/mpireg.h b/sys/dev/ic/mpireg.h
index 9a48e0b99d2..65db00327aa 100644
--- a/sys/dev/ic/mpireg.h
+++ b/sys/dev/ic/mpireg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: mpireg.h,v 1.7 2006/06/01 05:53:24 dlg Exp $ */
+/* $OpenBSD: mpireg.h,v 1.8 2006/06/01 20:05:24 dlg Exp $ */
/*
* Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
@@ -827,8 +827,10 @@ struct mpi_cfg_spi_port_pg0 {
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_PACKETIZED (1<<0)
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_DT (1<<1)
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_QAS (1<<2)
-#define MPI_CFG_SPI_PORT_0_CAPABILITIES_MIN_STP (0x0000ff00)
-#define MPI_CFG_SPI_PORT_0_CAPABILITIES_MAX_STP (0x00ff0000)
+#define MPI_CFG_SPI_PORT_0_CAPABILITIES_MIN_PERIOD(x) \
+ (((x) >> 8) & 0xff)
+#define MPI_CFG_SPI_PORT_0_CAPABILITIES_MAX_OFFSET(x) \
+ (((x) >> 16) & 0xff)
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_IDP (1<<27)
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH (1<<29)
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH_NARROW (0<<29)
@@ -857,8 +859,10 @@ struct mpi_cfg_spi_dev_pg0 {
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_RD_STRM (1<<5)
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_RTI (1<<6)
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_PCOMP_EN (1<<7)
-#define MPI_CFG_SPI_DEV_0_NEGPARAMS_XFER_PERIOD (0x0000ff00)
-#define MPI_CFG_SPI_DEV_0_NEGPARAMS_XFER_OFFSET (0x00ff0000)
+#define MPI_CFG_SPI_DEV_0_NEGPARAMS_XFER_PERIOD(x) \
+ (((x) >> 8) & 0xff)
+#define MPI_CFG_SPI_DEV_0_NEGPARAMS_XFER_OFFSET(x) \
+ (((x) >> 16) & 0xff)
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_IDP_EN (1<<27)
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH (1<<28)
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH_NARROW (0<<28)
@@ -884,8 +888,10 @@ struct mpi_cfg_spi_dev_pg1 {
#define MPI_CFG_SPI_DEV_1_REQPARAMS_RD_STRM (1<<5)
#define MPI_CFG_SPI_DEV_1_REQPARAMS_RTI (1<<6)
#define MPI_CFG_SPI_DEV_1_REQPARAMS_PCOMP_EN (1<<7)
-#define MPI_CFG_SPI_DEV_1_REQPARAMS_XFER_PERIOD (0x0000ff00)
-#define MPI_CFG_SPI_DEV_1_REQPARAMS_XFER_OFFSET (0x00ff0000)
+#define MPI_CFG_SPI_DEV_1_REQPARAMS_XFER_PERIOD(x) ((x) << 8)
+#define MPI_CFG_SPI_DEV_1_REQPARAMS_XFER_PERIOD_MASK (0xff<<8)
+#define MPI_CFG_SPI_DEV_1_REQPARAMS_XFER_OFFSET(x) ((x) << 16)
+#define MPI_CFG_SPI_DEV_1_REQPARAMS_XFER_OFFSET_MASK (0xff<<16)
#define MPI_CFG_SPI_DEV_1_REQPARAMS_IDP_EN (1<<27)
#define MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH (1<<28)
#define MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH_NARROW (0<<28)
@@ -895,10 +901,10 @@ struct mpi_cfg_spi_dev_pg1 {
u_int32_t reserved;
u_int32_t configuration;
-#define MPI_CFG_SPI_DEV_0_CONF_WDTR_DISALLOWED (1<<1)
-#define MPI_CFG_SPI_DEV_0_CONF_SDTR_DISALLOWED (1<<2)
-#define MPI_CFG_SPI_DEV_0_CONF_EXTPARAMS (1<<3)
-#define MPI_CFG_SPI_DEV_0_CONF_FORCE_PPR (1<<3)
+#define MPI_CFG_SPI_DEV_1_CONF_WDTR_DISALLOWED (1<<1)
+#define MPI_CFG_SPI_DEV_1_CONF_SDTR_DISALLOWED (1<<2)
+#define MPI_CFG_SPI_DEV_1_CONF_EXTPARAMS (1<<3)
+#define MPI_CFG_SPI_DEV_1_CONF_FORCE_PPR (1<<4)
} __packed;
struct mpi_cfg_manufacturing_pg0 {