Provide a specific delay() routine using separate timers for the two cpus

on MVME197DP boards running the MP kernel.

2 files changed, 48 insertions, 17 deletions

diff --git a/sys/arch/mvme88k/dev/busswreg.h b/sys/arch/mvme88k/dev/busswreg.h
index 817383b11c4..c806110c000 100644
--- a/sys/arch/mvme88k/dev/busswreg.h
+++ b/sys/arch/mvme88k/dev/busswreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: busswreg.h,v 1.11 2007/12/25 20:23:02 miod Exp $ */
+/*	$OpenBSD: busswreg.h,v 1.12 2009/02/13 23:28:05 miod Exp $ */
 
 /*
  * Memory map for BusSwitch chip found in mvme197 boards.
@@ -145,19 +145,18 @@
 #define BS_CPI_STAT	0x40	/* cpi interrupt status */
 #define BS_CPI_SCPI	0x80	/* send cross proc interrupt */
 
-/* Timer Interrupt 1 Register */
-#define BS_TINT1_ICLR	0x08	/* timer 1 interrupt clear */
-#define BS_TINT1_IEN	0x10	/* timer 1 interrupt enable */
-#define BS_TINT1_INT	0x20	/* timer 1 interrupt received */
-#define BS_TINT1_LM	0x07	/* timer 1 level mask */
-#define BS_TINT1_LEVEL(x)	(x & BS_TINT1_LM)
-
-/* Timer Interrupt 2 Register */
-#define BS_TINT2_ICLR	0x08	/* timer 1 interrupt clear */
-#define BS_TINT2_IEN	0x10	/* timer 1 interrupt enable */
-#define BS_TINT2_INT	0x20	/* timer 1 interrupt received */
-#define BS_TINT2_LM	0x07	/* timer 1 level mask */
-#define BS_TINT2_LEVEL(x)	(x & BS_TINT2_LM)
+/* Timer Control Register */
+#define BS_TCTRL_CEN	0x01	/* counter enable */
+#define BS_TCTRL_COC	0x02	/* clear on compare */
+#define BS_TCTRL_COVF	0x04	/* clear overflow counter */
+#define BS_TCTRL_OVF(x)		((x) >> 4)	/* overflow counter */
+
+/* Timer Interrupt Register */
+#define BS_TINT_ICLR	0x08	/* timer interrupt clear */
+#define BS_TINT_IEN	0x10	/* timer interrupt enable */
+#define BS_TINT_INT	0x20	/* timer interrupt received */
+#define BS_TINT_LM	0x07	/* timer level mask */
+#define BS_TINT_LEVEL(x)	(x & BS_TINT_LM)
 
 /* Write Post Control Register */
 #define BS_WPINT_ICLR	0x08	/* WPINT interrupt clear */
diff --git a/sys/arch/mvme88k/mvme88k/m197_machdep.c b/sys/arch/mvme88k/mvme88k/m197_machdep.c
index 71bba99f357..e9fb4d58207 100644
--- a/sys/arch/mvme88k/mvme88k/m197_machdep.c
+++ b/sys/arch/mvme88k/mvme88k/m197_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m197_machdep.c,v 1.29 2009/02/13 23:26:51 miod Exp $	*/
+/*	$OpenBSD: m197_machdep.c,v 1.30 2009/02/13 23:28:07 miod Exp $	*/
 /*
  * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -69,6 +69,7 @@
 
 void	m197_bootstrap(void);
 void	m197_clock_ipi_handler(struct trapframe *);
+void	m197_delay(int);
 void	m197_ext_int(u_int, struct trapframe *);
 u_int	m197_getipl(void);
 void	m197_ipi_handler(struct trapframe *);
@@ -392,8 +393,10 @@ m197_bootstrap()
 	md_init_clocks = m1x7_init_clocks;
 #ifdef MULTIPROCESSOR
 	md_send_ipi = m197_send_ipi;
-#endif
+	md_delay = m197_delay;
+#else
 	md_delay = m1x7_delay;
+#endif
 }
 
 #ifdef MULTIPROCESSOR
@@ -546,4 +549,33 @@ m197_clock_ipi_handler(struct trapframe *eframe)
 	splx(s);
 }
 
-#endif
+/*
+ * Special version of delay() for MP kernels.
+ * Processors need to use different timers, so we'll use the two
+ * BusSwitch timers for this purpose.
+ */
+void
+m197_delay(int us)
+{
+	if (CPU_IS_PRIMARY(curcpu())) {
+		*(volatile u_int32_t *)(BS_BASE + BS_TCOMP1) = 0xffffffff;
+		*(volatile u_int32_t *)(BS_BASE + BS_TCOUNT1) = 0;
+		*(volatile u_int8_t *)(BS_BASE + BS_TCTRL1) |= BS_TCTRL_CEN;
+
+		while ((*(volatile u_int32_t *)(BS_BASE + BS_TCOUNT1)) <
+		    (u_int32_t)us)
+			;
+		*(volatile u_int8_t *)(BS_BASE + BS_TCTRL1) &= ~BS_TCTRL_CEN;
+	} else {
+		*(volatile u_int32_t *)(BS_BASE + BS_TCOMP2) = 0xffffffff;
+		*(volatile u_int32_t *)(BS_BASE + BS_TCOUNT2) = 0;
+		*(volatile u_int8_t *)(BS_BASE + BS_TCTRL2) |= BS_TCTRL_CEN;
+
+		while ((*(volatile u_int32_t *)(BS_BASE + BS_TCOUNT2)) <
+		    (u_int32_t)us)
+			;
+		*(volatile u_int8_t *)(BS_BASE + BS_TCTRL2) &= ~BS_TCTRL_CEN;
+	}
+}
+
+#endif	/* MULTIPROCESSOR */