Support for 16KB page size kernels; page size is now set in <machine/param.h>

rather than <mips64/param.h>.

For now, kernels are kept at 4KB to give people some time to build 16KB
compatible binaries; this will change before the end of this release cycle.

Use of 16KB page size kernels yields a 18% speedup (which, offset by the
1.6% slowdown caused by the pmap changes, yields a 16.6% overall speedup).

7 files changed, 64 insertions, 38 deletions

diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index f17c7ffa028..8ef35ced8ef 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.46 2009/11/25 17:39:51 syuu Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.47 2009/12/07 19:05:57 miod Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -554,12 +554,13 @@ extern u_int	CpuOnboardCacheOn;	/* RM7K */
 struct tlb_entry;
 struct user;
 
-void	tlb_set_wired(int);
-void	tlb_set_pid(int);
-u_int	cp0_get_prid(void);
-u_int	cp1_get_prid(void);
 u_int	cp0_get_count(void);
+u_int	cp0_get_prid(void);
 void	cp0_set_compare(u_int);
+u_int	cp1_get_prid(void);
+void	tlb_set_page_mask(uint32_t);
+void	tlb_set_pid(int);
+void	tlb_set_wired(int);
 
 /*
  * Define soft selected cache functions.
diff --git a/sys/arch/mips64/include/param.h b/sys/arch/mips64/include/param.h
index ce39ab7c97b..1d100b85c00 100644
--- a/sys/arch/mips64/include/param.h
+++ b/sys/arch/mips64/include/param.h
@@ -1,4 +1,4 @@
-/*      $OpenBSD: param.h,v 1.21 2009/12/07 18:58:32 miod Exp $ */
+/*      $OpenBSD: param.h,v 1.22 2009/12/07 19:05:57 miod Exp $ */
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -53,35 +53,31 @@
 #define	ALIGN(p)	(((u_long)(p) + ALIGNBYTES) &~ ALIGNBYTES)
 #define ALIGNED_POINTER(p, t)  ((((u_long)(p)) & (sizeof (t) - 1)) == 0)
 
-#define	NBPG		4096		/* bytes/page */
-#define	PGOFSET		(NBPG-1)	/* byte offset into page */
-#define	PGSHIFT		12		/* LOG2(NBPG) */
-
-#define PAGE_SHIFT	12
+#ifndef	PAGE_SHIFT
+#error	PAGE_SHIFT is not defined
+#endif
 #define PAGE_SIZE	(1 << PAGE_SHIFT)
 #define PAGE_MASK	(PAGE_SIZE - 1)
 
+#define	NBPG		PAGE_SIZE
+#define	PGOFSET		PAGE_MASK
+#define	PGSHIFT		PAGE_SHIFT
 
-#ifdef __LP64__
 #define	KERNBASE	0xffffffff80000000L	/* start of kernel virtual */
-#else
-#define	KERNBASE	0x80000000	/* start of kernel virtual */
-#endif
 
 #define	DEV_BSHIFT	9		/* log2(DEV_BSIZE) */
 #define	DEV_BSIZE	(1 << DEV_BSHIFT)
 #define BLKDEV_IOSIZE	2048
 #define	MAXPHYS		(64 * 1024)	/* max raw I/O transfer size */
 
-#ifdef __LP64__
-#define	UPAGES		4		/* pages of u-area */
+#define USPACE		(16384)
+#define	UPAGES		(USPACE >> PAGE_SHIFT)
+#if PAGE_SHIFT > 12
+#define	USPACE_ALIGN	0
 #else
-#define	UPAGES		2		/* pages of u-area */
+#define	USPACE_ALIGN	(2 * PAGE_SIZE)	/* align to an even TLB boundary */
 #endif
 
-#define USPACE		(UPAGES*NBPG)	/* size of u-area in bytes */
-#define	USPACE_ALIGN	(2*NBPG)	/* u-area alignment 0-none */
-
 /*
  * Constants related to network buffer management.
  */
diff --git a/sys/arch/mips64/include/pte.h b/sys/arch/mips64/include/pte.h
index 1860aaa16ad..d1129832109 100644
--- a/sys/arch/mips64/include/pte.h
+++ b/sys/arch/mips64/include/pte.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pte.h,v 1.9 2009/12/07 18:58:32 miod Exp $	*/
+/*	$OpenBSD: pte.h,v 1.10 2009/12/07 19:05:57 miod Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -60,9 +60,15 @@ typedef u_int32_t pt_entry_t;	/* Mips page table entry */
 #endif /* _LOCORE */
 
 /* entryhi values */
+#if PAGE_SHIFT == 12
 #define	PG_SVPN		0xfffffffffffff000	/* Software page no mask */
 #define	PG_HVPN		0xffffffffffffe000	/* Hardware page no mask */
 #define	PG_ODDPG	0x0000000000001000	/* Odd even pte entry */
+#elif PAGE_SHIFT == 14
+#define	PG_SVPN		0xffffffffffffc000	/* Software page no mask */
+#define	PG_HVPN		0xffffffffffff8000	/* Hardware page no mask */
+#define	PG_ODDPG	0x0000000000004000	/* Odd even pte entry */
+#endif
 #define	PG_ASID		0x00000000000000ff	/* Address space ID */
 /* entrylo values */
 #define PG_RO		0x40000000	/* SW */
@@ -95,6 +101,12 @@ typedef u_int32_t pt_entry_t;	/* Mips page table entry */
 #define	PG_SIZE_4M	0x007fe000
 #define	PG_SIZE_16M	0x01ffe000
 
+#if PAGE_SHIFT == 12
+#define	TLB_PAGE_MASK	PG_SIZE_4K
+#elif PAGE_SHIFT == 14
+#define	TLB_PAGE_MASK	PG_SIZE_16K
+#endif
+
 #if defined(_KERNEL) && !defined(_LOCORE)
 
 /* Kernel virtual address to page table entry */
diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S
index 5adeb393ec7..94ec5879e65 100644
--- a/sys/arch/mips64/mips64/tlbhandler.S
+++ b/sys/arch/mips64/mips64/tlbhandler.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tlbhandler.S,v 1.23 2009/12/07 18:54:46 miod Exp $ */
+/*	$OpenBSD: tlbhandler.S,v 1.24 2009/12/07 19:05:59 miod Exp $ */
 
 /*
  * Copyright (c) 1995-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -387,10 +387,10 @@ END(k_tlb_miss)
  *	Write the given entry into the TLB at the given index.
  */
 LEAF(tlb_write_indexed, 0)
-	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
+	mfc0	v1, COP_0_STATUS_REG		# Save the status register.
 	ori	v0, v1, SR_INT_ENAB
 	xori	v0, v0, SR_INT_ENAB
-	mtc0	v0, COP_0_STATUS_REG	# Disable interrupts
+	mtc0	v0, COP_0_STATUS_REG		# Disable interrupts
 	ITLBNOPFIX
 	ld	a2, 16(a1)
 	ld	a3, 24(a1)
@@ -400,8 +400,8 @@ LEAF(tlb_write_indexed, 0)
 	dmtc0	a3, COP_0_TLB_LO1		# Set up entry low1.
 	ld	a2, 0(a1)
 	ld	a3, 8(a1)
-	mtc0	a0, COP_0_TLB_INDEX	# Set the index.
-	dmtc0	a2, COP_0_TLB_PG_MASK	# Set up entry mask.
+	mtc0	a0, COP_0_TLB_INDEX		# Set the index.
+	mtc0	a2, COP_0_TLB_PG_MASK		# Set up entry mask.
 	dmtc0	a3, COP_0_TLB_HI		# Set up entry high.
 	nop
 	nop
@@ -428,8 +428,9 @@ LEAF(tlb_write_indexed, 0)
 
 	dmtc0	ta0, COP_0_TLB_HI		# Restore the PID.
 	nop
-	dmtc0	zero, COP_0_TLB_PG_MASK	# Default mask value.
-	mtc0	v1, COP_0_STATUS_REG	# Restore the status register
+	li	a0, TLB_PAGE_MASK
+	mtc0	a0, COP_0_TLB_PG_MASK		# Restore default mask value.
+	mtc0	v1, COP_0_STATUS_REG		# Restore the status register
 	ITLBNOPFIX
 	j	ra
 	nop
@@ -484,6 +485,8 @@ LEAF(tlb_flush, 0)
 #endif
 
 	dmtc0	ta0, COP_0_TLB_HI	# Restore the PID
+	li	a0, TLB_PAGE_MASK
+	mtc0	a0, COP_0_TLB_PG_MASK	# Restore default mask value.
 	mtc0	v1, COP_0_STATUS_REG	# Restore the status register
 	ITLBNOPFIX
 	j	ra
@@ -565,6 +568,7 @@ LEAF(tlb_update, 0)
 	dmfc0	ta0, COP_0_TLB_HI	# Save current PID
 	dmtc0	a0, COP_0_TLB_HI	# Init high reg
 	and	a2, a1, PG_G		# Copy global bit
+	li	a3, TLB_PAGE_MASK
 	nop
 	nop
 	nop
@@ -590,7 +594,7 @@ LEAF(tlb_update, 0)
 	b	4f
 	li	v0, 1
 1:
-	mtc0	zero, COP_0_TLB_PG_MASK	# init mask.
+	mtc0	a3, COP_0_TLB_PG_MASK	# init mask.
 	dmtc0	a0, COP_0_TLB_HI	# init high reg.
 	dmtc0	a1, COP_0_TLB_LO0	# init low reg0.
 	dmtc0	a2, COP_0_TLB_LO1	# init low reg1.
@@ -620,7 +624,7 @@ LEAF(tlb_update, 0)
 	b	4f
 	li	v0, 1
 3:
-	mtc0	zero, COP_0_TLB_PG_MASK	# init mask.
+	mtc0	a3, COP_0_TLB_PG_MASK	# init mask.
 	dmtc0	a0, COP_0_TLB_HI	# init high reg.
 	dmtc0	a2, COP_0_TLB_LO0	# init low reg0.
 	dmtc0	a1, COP_0_TLB_LO1	# init low reg1.
@@ -684,6 +688,8 @@ LEAF(tlb_read, 0)
 	nop
 	nop
 	nop				# wait for PID active
+	li	a0, TLB_PAGE_MASK
+	mtc0	a0, COP_0_TLB_PG_MASK	# Restore default mask value.
 	mtc0	v1, COP_0_STATUS_REG	# Restore the status register
 	ITLBNOPFIX
 	sd	ta0, 0(a1)
@@ -729,3 +735,12 @@ LEAF(tlb_set_wired, 0)
 	j	ra
 	nop
 END(tlb_set_wired)
+
+/*
+ *	Initialize the TLB page mask.
+ */
+LEAF(tlb_set_page_mask, 0)
+	mtc0	a0, COP_0_TLB_PG_MASK
+	j	ra
+	nop
+END(tlb_set_page_mask)
diff --git a/sys/arch/sgi/include/param.h b/sys/arch/sgi/include/param.h
index 52fb6e26a5b..e955a483204 100644
--- a/sys/arch/sgi/include/param.h
+++ b/sys/arch/sgi/include/param.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: param.h,v 1.3 2004/08/10 21:11:42 pefo Exp $ */
+/*	$OpenBSD: param.h,v 1.4 2009/12/07 19:05:59 miod Exp $ */
 
 /*
  * Copyright (c) 2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -39,6 +39,8 @@
 
 #define MID_MACHINE	MID_MIPS64	/* None but has to be defined */
 
+#define	PAGE_SHIFT	12
+
 #include <mips64/param.h>
 
 #endif /* _MACHINE_PARAM_H_ */
diff --git a/sys/arch/sgi/sgi/ip30_machdep.c b/sys/arch/sgi/sgi/ip30_machdep.c
index 9d30c26480a..6b637e778d9 100644
--- a/sys/arch/sgi/sgi/ip30_machdep.c
+++ b/sys/arch/sgi/sgi/ip30_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip30_machdep.c,v 1.26 2009/12/02 01:42:14 syuu Exp $	*/
+/*	$OpenBSD: ip30_machdep.c,v 1.27 2009/12/07 19:05:59 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009 Miodrag Vallat.
@@ -400,6 +400,7 @@ hw_cpu_hatch(struct cpu_info *ci)
        Mips10k_ConfigCache();
 
        sys_config.cpu[cpuid].tlbwired = UPAGES / 2;
+	tlb_set_page_mask(TLB_PAGE_MASK);
        tlb_set_wired(0);
        tlb_flush(sys_config.cpu[cpuid].tlbsize);
        tlb_set_wired(sys_config.cpu[cpuid].tlbwired);
diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c
index 7ec8a85cace..b9f68be9280 100644
--- a/sys/arch/sgi/sgi/machdep.c
+++ b/sys/arch/sgi/sgi/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.92 2009/12/07 18:51:26 miod Exp $ */
+/*	$OpenBSD: machdep.c,v 1.93 2009/12/07 19:05:59 miod Exp $ */
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -478,6 +478,7 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 	delay(20*1000);		/* Let any UART FIFO drain... */
 
 	sys_config.cpu[0].tlbwired = UPAGES / 2;
+	tlb_set_page_mask(TLB_PAGE_MASK);
 	tlb_set_wired(0);
 	tlb_flush(sys_config.cpu[0].tlbsize);
 	tlb_set_wired(sys_config.cpu[0].tlbwired);
@@ -524,10 +525,8 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 		 * of the processor need it, but there is evidence
 		 * later versions also need it.
 		 *
-		 * This is also necessary on RM52x0; we test on the `rounded'
-		 * cputype value instead of sys_config.cpu[0].type; this
-		 * causes RM7k and RM9k to be included, just to be on the
-		 * safe side.
+		 * This is also necessary on RM52x0 and most RM7k/RM9k,
+		 * and is a documented errata for these chips.
 		 */
 		tlb_handler = (vaddr_t)&tlb_miss_err_r5k;
 		xtlb_handler = (vaddr_t)&xtlb_miss_err_r5k;