- fix some comments

- remove some unused fields from softc
- spacing

2 files changed, 187 insertions, 186 deletions

diff --git a/sys/dev/usb/if_urtw.c b/sys/dev/usb/if_urtw.c
index 9c5d9168ed0..8e1e1978204 100644
--- a/sys/dev/usb/if_urtw.c
+++ b/sys/dev/usb/if_urtw.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_urtw.c,v 1.10 2009/06/04 19:30:19 martynas Exp $	*/
+/*	$OpenBSD: if_urtw.c,v 1.11 2009/06/04 19:37:26 martynas Exp $	*/
 
 /*-
  * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
@@ -206,7 +206,7 @@ static struct urtw_pair urtw_8225_rf_part3[] = {
 	{ 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
 };
 
-static uint16_t urtw_8225_rxgain[] = {	
+static uint16_t urtw_8225_rxgain[] = {
 	0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
 	0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
 	0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
@@ -1040,7 +1040,7 @@ urtw_8225_isv2(struct urtw_softc *sc, int *ret)
 	usbd_delay_ms(sc->sc_udev, 500);
 
 	urtw_8225_write(sc, 0x0, 0x1b7);
-	
+
 	error = urtw_8225_read(sc, 0x8, &data);
 	if (error != 0)
 		goto fail;
@@ -1144,7 +1144,7 @@ urtw_get_macaddr(struct urtw_softc *sc)
 	struct ieee80211com *ic = &sc->sc_ic;
 	usbd_status error;
 	uint32_t data;
-	
+
 	error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
 	if (error != 0)
 		goto fail;
@@ -1551,7 +1551,7 @@ urtw_reset(struct urtw_softc *sc)
 		printf("%s: reset timeout\n", sc->sc_dev.dv_xname);
 		goto fail;
 	}
-	
+
 	error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
 	if (error)
 		goto fail;
@@ -1777,7 +1777,7 @@ urtw_led_blink(struct urtw_softc *sc)
 
 	sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
 	    URTW_LED_ON : URTW_LED_OFF;
-	
+
 	switch (sc->sc_gpio_ledstate) {
 	case URTW_LED_BLINK_NORMAL:
 		t.tv_sec = 0;
@@ -1856,7 +1856,7 @@ urtw_set_rate(struct urtw_softc *sc)
 	basic_rate = urtw_rate2rtl(48);
 	min_rr_rate = urtw_rate2rtl(12);
 	max_rr_rate = urtw_rate2rtl(48);
-	
+
 	urtw_write8_m(sc, URTW_RESP_RATE,
 	    max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
 	    min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
@@ -1912,7 +1912,7 @@ urtw_rx_setconf(struct urtw_softc *sc)
 		data = data | URTW_RX_FILTER_NICMAC;
 		data = data | URTW_RX_CHECK_BSSID;
 	}
-	
+
 	data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
 	data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY;
 	data = data &~ URTW_MAX_RX_DMA_MASK;
@@ -2579,7 +2579,7 @@ urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
 	uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
 	uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
 	usbd_status error;
-	
+
 	cck_pwrlvl_max = 11;
 	ofdm_pwrlvl_max = 25;	/* 12 -> 25  */
 	ofdm_pwrlvl_min = 10;
@@ -2598,12 +2598,12 @@ urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
 		    cck_pwltable[idx * 8 + i]);
 	}
 	usbd_delay_ms(sc->sc_udev, 1);
-	
+
 	/* OFDM power setting */
 	ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
 	    ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
 	ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
-	
+
 	idx = ofdm_pwrlvl % 6;
 	set = ofdm_pwrlvl / 6;
 
@@ -2677,7 +2677,7 @@ urtw_8225_rf_init(struct urtw_softc *sc)
 	urtw_8225_write(sc, 0x2, 0x44d);
 	usbd_delay_ms(sc->sc_udev, 200);
 	urtw_8225_write(sc, 0x0, 0x127);
-	
+
 	for (i = 0; i < 95; i++) {
 		urtw_8225_write(sc, 0x1, (uint8_t)(i + 1));
 		urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]);
@@ -2685,7 +2685,7 @@ urtw_8225_rf_init(struct urtw_softc *sc)
 
 	urtw_8225_write(sc, 0x0, 0x27);
 	urtw_8225_write(sc, 0x0, 0x22f);
-	
+
 	for (i = 0; i < 128; i++) {
 		urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
 		urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
@@ -2696,7 +2696,7 @@ urtw_8225_rf_init(struct urtw_softc *sc)
 		    urtw_8225_rf_part2[i].val);
 		usbd_delay_ms(sc->sc_udev, 1);
 	}
-	
+
 	error = urtw_8225_setgain(sc, 4);
 	if (error)
 		goto fail;
@@ -2712,7 +2712,7 @@ urtw_8225_rf_init(struct urtw_softc *sc)
 	error = urtw_8225_set_txpwrlvl(sc, 1);
 	if (error)
 		goto fail;
-	
+
 	urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
 	usbd_delay_ms(sc->sc_udev, 1);
 	urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
@@ -2749,7 +2749,7 @@ urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
 		urtw_write8_m(sc, URTW_SLOT, 0x9);
 	else
 		urtw_write8_m(sc, URTW_SLOT, 0x14);
-	
+
 	if (IEEE80211_IS_CHAN_G(c)) {
 		urtw_write8_m(sc, URTW_DIFS, 0x14);
 		urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
@@ -2774,14 +2774,14 @@ urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
 
 	if (sens > 4)
 		urtw_8225_write(sc, 0x0c, 0x850);
-	else	
+	else
 		urtw_8225_write(sc, 0x0c, 0x50);
 
 	sens = 6 - sens;
 	error = urtw_8225_setgain(sc, sens);
 	if (error)
 		goto fail;
-	
+
 	urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
 
 fail:
@@ -2882,7 +2882,7 @@ urtw_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status)
 		ifp->if_ierrors++;
 		goto skip;
 	}
-		
+
 	m = data->m;
 	data->m = mnew;
 	data->buf = mtod(mnew, uint8_t *);
@@ -2980,7 +2980,7 @@ urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
 	urtw_write8_m(sc, URTW_TX_GAIN_CCK,
 	    urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
 	usbd_delay_ms(sc->sc_udev, 1);
-	
+
 	/* OFDM power setting */
 	ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
 		ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
@@ -3091,7 +3091,7 @@ urtw_8225v2_rf_init(struct urtw_softc *sc)
 		urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
 		    urtw_8225v2_rf_part2[i].val);
 	}
-	
+
 	error = urtw_8225v2_setgain(sc, 4);
 	if (error)
 		goto fail;
@@ -3106,7 +3106,7 @@ urtw_8225v2_rf_init(struct urtw_softc *sc)
 	error = urtw_8225v2_set_txpwrlvl(sc, 1);
 	if (error)
 		goto fail;
-	
+
 	urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
 	urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
 
@@ -3142,7 +3142,7 @@ urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
 		urtw_write8_m(sc, URTW_SLOT, 0x9);
 	else
 		urtw_write8_m(sc, URTW_SLOT, 0x14);
-	
+
 	if (IEEE80211_IS_CHAN_G(c)) {
 		urtw_write8_m(sc, URTW_DIFS, 0x14);
 		urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
@@ -3169,7 +3169,7 @@ urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c)
 	if (chan == 0 || chan == IEEE80211_CHAN_ANY)
 		return;
 	/*
-	 * during changing th channel we need to temporarily be disable
+	 * During changing the channel we need to temporary be disable
 	 * TX.
 	 */
 	urtw_read32_m(sc, URTW_TX_CONF, &data);
@@ -3222,7 +3222,7 @@ urtw_task(void *arg)
 		urtw_set_chan(sc, ic->ic_bss->ni_chan);
 		timeout_add(&sc->scan_to, hz / 5);
 		break;
-	
+
 	case IEEE80211_S_AUTH:
 	case IEEE80211_S_ASSOC:
 		urtw_set_chan(sc, ic->ic_bss->ni_chan);
@@ -3238,7 +3238,7 @@ urtw_task(void *arg)
 		urtw_update_msr(sc);
 		/* XXX maybe the below would be incorrect.  */
 		urtw_write16_m(sc, URTW_ATIM_WND, 2);
-		urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);	
+		urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
 		urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
 		urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
 		error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
@@ -3255,3 +3255,4 @@ fail:
 		DPRINTF(("%s: error duing processing RUN state.",
 		    sc->sc_dev.dv_xname));
 }
+
diff --git a/sys/dev/usb/if_urtwreg.h b/sys/dev/usb/if_urtwreg.h
index 9b6f5ead4da..d7ed772be5d 100644
--- a/sys/dev/usb/if_urtwreg.h
+++ b/sys/dev/usb/if_urtwreg.h
@@ -1,4 +1,5 @@
-/*	$OpenBSD: if_urtwreg.h,v 1.3 2009/06/04 19:27:27 martynas Exp $	*/
+/*	$OpenBSD: if_urtwreg.h,v 1.4 2009/06/04 19:37:26 martynas Exp $	*/
+
 /*-
  * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
  *
@@ -15,164 +16,164 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#define URTW_CONFIG_NO			1
-#define URTW_IFACE_INDEX		0
+#define	URTW_CONFIG_NO			1
+#define	URTW_IFACE_INDEX		0
 
 /* for 8187  */
-#define URTW_MAC0			0x0000		/* 1 byte  */
-#define URTW_MAC1			0x0001		/* 1 byte  */
-#define URTW_MAC2			0x0002		/* 1 byte  */
-#define URTW_MAC3			0x0003		/* 1 byte  */
-#define URTW_MAC4			0x0004		/* 1 byte  */
-#define URTW_MAC5			0x0005		/* 1 byte  */
-#define URTW_BRSR			0x002c		/* 2 byte  */
-#define URTW_BRSR_MBR_8185		(0x0fff)
+#define	URTW_MAC0			0x0000		/* 1 byte  */
+#define	URTW_MAC1			0x0001		/* 1 byte  */
+#define	URTW_MAC2			0x0002		/* 1 byte  */
+#define	URTW_MAC3			0x0003		/* 1 byte  */
+#define	URTW_MAC4			0x0004		/* 1 byte  */
+#define	URTW_MAC5			0x0005		/* 1 byte  */
+#define	URTW_BRSR			0x002c		/* 2 byte  */
+#define	URTW_BRSR_MBR_8185		(0x0fff)
 #define	URTW_BSSID			0x002e		/* 6 byte  */
-#define URTW_RESP_RATE			0x0034		/* 1 byte  */
-#define URTW_RESP_MAX_RATE_SHIFT	(4)
-#define URTW_RESP_MIN_RATE_SHIFT	(0)
-#define URTW_EIFS			0x0035		/* 1 byte  */
-#define URTW_INTR_MASK			0x003c		/* 2 byte  */
-#define URTW_CMD			0x0037		/* 1 byte  */
-#define URTW_CMD_TX_ENABLE		(0x4)
-#define URTW_CMD_RX_ENABLE		(0x8)
-#define URTW_CMD_RST			(0x10)
-#define URTW_TX_CONF			0x0040		/* 4 byte  */
-#define URTW_TX_LOOPBACK_SHIFT		(17)
-#define URTW_TX_LOOPBACK_NONE		(0 << URTW_TX_LOOPBACK_SHIFT)
-#define URTW_TX_LOOPBACK_MAC		(1 << URTW_TX_LOOPBACK_SHIFT)
-#define URTW_TX_LOOPBACK_BASEBAND	(2 << URTW_TX_LOOPBACK_SHIFT)
-#define URTW_TX_LOOPBACK_CONTINUE	(3 << URTW_TX_LOOPBACK_SHIFT)
-#define URTW_TX_LOOPBACK_MASK		(0x60000)
-#define URTW_TX_DPRETRY_MASK		(0xff00)
-#define URTW_TX_RTSRETRY_MASK		(0xff)
-#define URTW_TX_DPRETRY_SHIFT		(0)
-#define URTW_TX_RTSRETRY_SHIFT		(8)
-#define URTW_TX_NOCRC			(0x10000)
-#define URTW_TX_MXDMA_MASK		(0xe00000)
-#define URTW_TX_MXDMA_1024		(6 << URTW_TX_MXDMA_SHIFT)
-#define URTW_TX_MXDMA_2048		(7 << URTW_TX_MXDMA_SHIFT)
-#define URTW_TX_MXDMA_SHIFT		(21)
-#define URTW_TX_CWMIN			(1 << 31)
-#define URTW_TX_DISCW			(1 << 20)
-#define URTW_TX_SWPLCPLEN		(1 << 24)
-#define URTW_TX_NOICV			(0x80000)
-#define URTW_RX				0x0044		/* 4 byte  */
-#define URTW_RX_9356SEL			(1 << 6)
-#define URTW_RX_FILTER_MASK			\
+#define	URTW_RESP_RATE			0x0034		/* 1 byte  */
+#define	URTW_RESP_MAX_RATE_SHIFT	(4)
+#define	URTW_RESP_MIN_RATE_SHIFT	(0)
+#define	URTW_EIFS			0x0035		/* 1 byte  */
+#define	URTW_INTR_MASK			0x003c		/* 2 byte  */
+#define	URTW_CMD			0x0037		/* 1 byte  */
+#define	URTW_CMD_TX_ENABLE		(0x4)
+#define	URTW_CMD_RX_ENABLE		(0x8)
+#define	URTW_CMD_RST			(0x10)
+#define	URTW_TX_CONF			0x0040		/* 4 byte  */
+#define	URTW_TX_LOOPBACK_SHIFT		(17)
+#define	URTW_TX_LOOPBACK_NONE		(0 << URTW_TX_LOOPBACK_SHIFT)
+#define	URTW_TX_LOOPBACK_MAC		(1 << URTW_TX_LOOPBACK_SHIFT)
+#define	URTW_TX_LOOPBACK_BASEBAND	(2 << URTW_TX_LOOPBACK_SHIFT)
+#define	URTW_TX_LOOPBACK_CONTINUE	(3 << URTW_TX_LOOPBACK_SHIFT)
+#define	URTW_TX_LOOPBACK_MASK		(0x60000)
+#define	URTW_TX_DPRETRY_MASK		(0xff00)
+#define	URTW_TX_RTSRETRY_MASK		(0xff)
+#define	URTW_TX_DPRETRY_SHIFT		(0)
+#define	URTW_TX_RTSRETRY_SHIFT		(8)
+#define	URTW_TX_NOCRC			(0x10000)
+#define	URTW_TX_MXDMA_MASK		(0xe00000)
+#define	URTW_TX_MXDMA_1024		(6 << URTW_TX_MXDMA_SHIFT)
+#define	URTW_TX_MXDMA_2048		(7 << URTW_TX_MXDMA_SHIFT)
+#define	URTW_TX_MXDMA_SHIFT		(21)
+#define	URTW_TX_CWMIN			(1 << 31)
+#define	URTW_TX_DISCW			(1 << 20)
+#define	URTW_TX_SWPLCPLEN		(1 << 24)
+#define	URTW_TX_NOICV			(0x80000)
+#define	URTW_RX				0x0044		/* 4 byte  */
+#define	URTW_RX_9356SEL			(1 << 6)
+#define	URTW_RX_FILTER_MASK			\
 	(URTW_RX_FILTER_ALLMAC | URTW_RX_FILTER_NICMAC | URTW_RX_FILTER_MCAST | \
 	URTW_RX_FILTER_BCAST | URTW_RX_FILTER_CRCERR | URTW_RX_FILTER_ICVERR | \
 	URTW_RX_FILTER_DATA | URTW_RX_FILTER_CTL | URTW_RX_FILTER_MNG |	\
 	(1 << 21) |							\
 	URTW_RX_FILTER_PWR | URTW_RX_CHECK_BSSID)
-#define URTW_RX_FILTER_ALLMAC		(0x00000001)
-#define URTW_RX_FILTER_NICMAC		(0x00000002)
-#define URTW_RX_FILTER_MCAST		(0x00000004)
-#define URTW_RX_FILTER_BCAST		(0x00000008)
-#define URTW_RX_FILTER_CRCERR		(0x00000020)
-#define URTW_RX_FILTER_ICVERR		(0x00001000)
-#define URTW_RX_FILTER_DATA		(0x00040000)
-#define URTW_RX_FILTER_CTL		(0x00080000)
-#define URTW_RX_FILTER_MNG		(0x00100000)
-#define URTW_RX_FILTER_PWR		(0x00400000)
-#define URTW_RX_CHECK_BSSID		(0x00800000)
-#define URTW_RX_FIFO_THRESHOLD_MASK	((1 << 13) | (1 << 14) | (1 << 15))
-#define URTW_RX_FIFO_THRESHOLD_SHIFT	(13)
-#define URTW_RX_FIFO_THRESHOLD_128	(3)
-#define URTW_RX_FIFO_THRESHOLD_256	(4)
-#define URTW_RX_FIFO_THRESHOLD_512	(5)
-#define URTW_RX_FIFO_THRESHOLD_1024	(6)
-#define URTW_RX_FIFO_THRESHOLD_NONE	(7 << URTW_RX_FIFO_THRESHOLD_SHIFT)
-#define URTW_RX_AUTORESETPHY		(1 << URTW_RX_AUTORESETPHY_SHIFT)
-#define URTW_RX_AUTORESETPHY_SHIFT	(28)
-#define URTW_MAX_RX_DMA_MASK		((1<<8) | (1<<9) | (1<<10))
-#define URTW_MAX_RX_DMA_2048		(7 << URTW_MAX_RX_DMA_SHIFT)
-#define URTW_MAX_RX_DMA_1024		(6)
-#define URTW_MAX_RX_DMA_SHIFT		(10)
-#define URTW_RCR_ONLYERLPKT		(1 << 31)
-#define URTW_INT_TIMEOUT		0x0048		/* 4 byte  */
-#define URTW_EPROM_CMD			0x0050		/* 1 byte  */
-#define URTW_EPROM_CMD_NORMAL		(0x0)
-#define URTW_EPROM_CMD_NORMAL_MODE				\
+#define	URTW_RX_FILTER_ALLMAC		(0x00000001)
+#define	URTW_RX_FILTER_NICMAC		(0x00000002)
+#define	URTW_RX_FILTER_MCAST		(0x00000004)
+#define	URTW_RX_FILTER_BCAST		(0x00000008)
+#define	URTW_RX_FILTER_CRCERR		(0x00000020)
+#define	URTW_RX_FILTER_ICVERR		(0x00001000)
+#define	URTW_RX_FILTER_DATA		(0x00040000)
+#define	URTW_RX_FILTER_CTL		(0x00080000)
+#define	URTW_RX_FILTER_MNG		(0x00100000)
+#define	URTW_RX_FILTER_PWR		(0x00400000)
+#define	URTW_RX_CHECK_BSSID		(0x00800000)
+#define	URTW_RX_FIFO_THRESHOLD_MASK	((1 << 13) | (1 << 14) | (1 << 15))
+#define	URTW_RX_FIFO_THRESHOLD_SHIFT	(13)
+#define	URTW_RX_FIFO_THRESHOLD_128	(3)
+#define	URTW_RX_FIFO_THRESHOLD_256	(4)
+#define	URTW_RX_FIFO_THRESHOLD_512	(5)
+#define	URTW_RX_FIFO_THRESHOLD_1024	(6)
+#define	URTW_RX_FIFO_THRESHOLD_NONE	(7 << URTW_RX_FIFO_THRESHOLD_SHIFT)
+#define	URTW_RX_AUTORESETPHY		(1 << URTW_RX_AUTORESETPHY_SHIFT)
+#define	URTW_RX_AUTORESETPHY_SHIFT	(28)
+#define	URTW_MAX_RX_DMA_MASK		((1<<8) | (1<<9) | (1<<10))
+#define	URTW_MAX_RX_DMA_2048		(7 << URTW_MAX_RX_DMA_SHIFT)
+#define	URTW_MAX_RX_DMA_1024		(6)
+#define	URTW_MAX_RX_DMA_SHIFT		(10)
+#define	URTW_RCR_ONLYERLPKT		(1 << 31)
+#define	URTW_INT_TIMEOUT		0x0048		/* 4 byte  */
+#define	URTW_EPROM_CMD			0x0050		/* 1 byte  */
+#define	URTW_EPROM_CMD_NORMAL		(0x0)
+#define	URTW_EPROM_CMD_NORMAL_MODE				\
 	(URTW_EPROM_CMD_NORMAL << URTW_EPROM_CMD_SHIFT)
-#define URTW_EPROM_CMD_LOAD		(0x1)
-#define URTW_EPROM_CMD_PROGRAM		(0x2)
-#define URTW_EPROM_CMD_PROGRAM_MODE				\
+#define	URTW_EPROM_CMD_LOAD		(0x1)
+#define	URTW_EPROM_CMD_PROGRAM		(0x2)
+#define	URTW_EPROM_CMD_PROGRAM_MODE				\
 	(URTW_EPROM_CMD_PROGRAM << URTW_EPROM_CMD_SHIFT)
-#define URTW_EPROM_CMD_CONFIG		(0x3)
-#define URTW_EPROM_CMD_SHIFT		(6)
-#define URTW_EPROM_CMD_MASK		((1 << 7) | (1 << 6))
-#define URTW_EPROM_READBIT		(0x1)
-#define URTW_EPROM_WRITEBIT		(0x2)
-#define URTW_EPROM_CK			(0x4)
-#define URTW_EPROM_CS			(0x8)
-#define URTW_CONFIG2			0x0053
-#define URTW_ANAPARAM			0x0054		/* 4 byte  */
-#define URTW_8225_ANAPARAM_ON		(0xa0000a59)
-#define URTW_MSR			0x0058		/* 1 byte  */
-#define URTW_MSR_LINK_MASK		((1 << 2) | (1 << 3))
-#define URTW_MSR_LINK_SHIFT		(2)
-#define URTW_MSR_LINK_NONE		(0 << URTW_MSR_LINK_SHIFT)
-#define URTW_MSR_LINK_ADHOC		(1 << URTW_MSR_LINK_SHIFT)
-#define URTW_MSR_LINK_STA		(2 << URTW_MSR_LINK_SHIFT)
-#define URTW_MSR_LINK_HOSTAP		(3 << URTW_MSR_LINK_SHIFT)
-#define URTW_CONFIG3			0x0059		/* 1 byte  */
-#define URTW_CONFIG3_ANAPARAM_WRITE	(0x40)
-#define URTW_CONFIG3_ANAPARAM_W_SHIFT	(6)
-#define URTW_PSR			0x005e		/* 1 byte  */
-#define URTW_ANAPARAM2			0x0060		/* 4 byte  */
-#define URTW_8225_ANAPARAM2_ON		(0x860c7312)
+#define	URTW_EPROM_CMD_CONFIG		(0x3)
+#define	URTW_EPROM_CMD_SHIFT		(6)
+#define	URTW_EPROM_CMD_MASK		((1 << 7) | (1 << 6))
+#define	URTW_EPROM_READBIT		(0x1)
+#define	URTW_EPROM_WRITEBIT		(0x2)
+#define	URTW_EPROM_CK			(0x4)
+#define	URTW_EPROM_CS			(0x8)
+#define	URTW_CONFIG2			0x0053
+#define	URTW_ANAPARAM			0x0054		/* 4 byte  */
+#define	URTW_8225_ANAPARAM_ON		(0xa0000a59)
+#define	URTW_MSR			0x0058		/* 1 byte  */
+#define	URTW_MSR_LINK_MASK		((1 << 2) | (1 << 3))
+#define	URTW_MSR_LINK_SHIFT		(2)
+#define	URTW_MSR_LINK_NONE		(0 << URTW_MSR_LINK_SHIFT)
+#define	URTW_MSR_LINK_ADHOC		(1 << URTW_MSR_LINK_SHIFT)
+#define	URTW_MSR_LINK_STA		(2 << URTW_MSR_LINK_SHIFT)
+#define	URTW_MSR_LINK_HOSTAP		(3 << URTW_MSR_LINK_SHIFT)
+#define	URTW_CONFIG3			0x0059		/* 1 byte  */
+#define	URTW_CONFIG3_ANAPARAM_WRITE	(0x40)
+#define	URTW_CONFIG3_ANAPARAM_W_SHIFT	(6)
+#define	URTW_PSR			0x005e		/* 1 byte  */
+#define	URTW_ANAPARAM2			0x0060		/* 4 byte  */
+#define	URTW_8225_ANAPARAM2_ON		(0x860c7312)
 #define	URTW_BEACON_INTERVAL		0x0070		/* 2 byte  */
 #define	URTW_ATIM_WND			0x0072		/* 2 byte  */
 #define	URTW_BEACON_INTERVAL_TIME	0x0074		/* 2 byte  */
 #define	URTW_ATIM_TR_ITV		0x0076		/* 2 byte  */
-#define URTW_RF_PINS_OUTPUT		0x0080		/* 2 byte  */
-#define URTW_BB_HOST_BANG_CLK		(1 << 1)
-#define URTW_BB_HOST_BANG_EN		(1 << 2)
-#define URTW_BB_HOST_BANG_RW		(1 << 3)
-#define URTW_RF_PINS_ENABLE		0x0082		/* 2 byte  */
-#define URTW_RF_PINS_SELECT		0x0084		/* 2 byte  */
-#define URTW_RF_PINS_INPUT		0x0086		/* 2 byte  */
-#define URTW_RF_PARA			0x0088		/* 4 byte  */
-#define URTW_RF_TIMING			0x008c		/* 4 byte  */
-#define URTW_GP_ENABLE			0x0090		/* 1 byte  */
-#define URTW_GPIO			0x0091		/* 1 byte  */
-#define URTW_TX_AGC_CTL			0x009c		/* 1 byte  */
-#define URTW_TX_AGC_CTL_PERPACKET_GAIN	(0x1)
-#define URTW_TX_AGC_CTL_PERPACKET_ANTSEL	(0x2)
-#define URTW_TX_AGC_CTL_FEEDBACK_ANT	(0x4)
-#define URTW_TX_GAIN_CCK		0x009d		/* 1 byte  */
-#define URTW_TX_GAIN_OFDM		0x009e		/* 1 byte  */
-#define URTW_TX_ANTENNA			0x009f		/* 1 byte  */
-#define URTW_WPA_CONFIG			0x00b0		/* 1 byte  */
-#define URTW_SIFS			0x00b4		/* 1 byte  */
-#define URTW_DIFS			0x00b5		/* 1 byte  */
-#define URTW_SLOT			0x00b6		/* 1 byte  */
-#define URTW_CW_CONF			0x00bc		/* 1 byte  */
-#define URTW_CW_CONF_PERPACKET_RETRY	(0x2)
-#define URTW_CW_CONF_PERPACKET_CW	(0x1)
-#define URTW_CW_VAL			0x00bd		/* 1 byte  */
-#define URTW_RATE_FALLBACK		0x00be		/* 1 byte  */
-#define URTW_TALLY_SEL			0x00fc		/* 1 byte  */
+#define	URTW_RF_PINS_OUTPUT		0x0080		/* 2 byte  */
+#define	URTW_BB_HOST_BANG_CLK		(1 << 1)
+#define	URTW_BB_HOST_BANG_EN		(1 << 2)
+#define	URTW_BB_HOST_BANG_RW		(1 << 3)
+#define	URTW_RF_PINS_ENABLE		0x0082		/* 2 byte  */
+#define	URTW_RF_PINS_SELECT		0x0084		/* 2 byte  */
+#define	URTW_RF_PINS_INPUT		0x0086		/* 2 byte  */
+#define	URTW_RF_PARA			0x0088		/* 4 byte  */
+#define	URTW_RF_TIMING			0x008c		/* 4 byte  */
+#define	URTW_GP_ENABLE			0x0090		/* 1 byte  */
+#define	URTW_GPIO			0x0091		/* 1 byte  */
+#define	URTW_TX_AGC_CTL			0x009c		/* 1 byte  */
+#define	URTW_TX_AGC_CTL_PERPACKET_GAIN	(0x1)
+#define	URTW_TX_AGC_CTL_PERPACKET_ANTSEL	(0x2)
+#define	URTW_TX_AGC_CTL_FEEDBACK_ANT	(0x4)
+#define	URTW_TX_GAIN_CCK		0x009d		/* 1 byte  */
+#define	URTW_TX_GAIN_OFDM		0x009e		/* 1 byte  */
+#define	URTW_TX_ANTENNA			0x009f		/* 1 byte  */
+#define	URTW_WPA_CONFIG			0x00b0		/* 1 byte  */
+#define	URTW_SIFS			0x00b4		/* 1 byte  */
+#define	URTW_DIFS			0x00b5		/* 1 byte  */
+#define	URTW_SLOT			0x00b6		/* 1 byte  */
+#define	URTW_CW_CONF			0x00bc		/* 1 byte  */
+#define	URTW_CW_CONF_PERPACKET_RETRY	(0x2)
+#define	URTW_CW_CONF_PERPACKET_CW	(0x1)
+#define	URTW_CW_VAL			0x00bd		/* 1 byte  */
+#define	URTW_RATE_FALLBACK		0x00be		/* 1 byte  */
+#define	URTW_TALLY_SEL			0x00fc		/* 1 byte  */
 
 /* for EEPROM  */
-#define URTW_EPROM_TXPW_BASE		0x05
-#define URTW_EPROM_RFCHIPID		0x06
-#define URTW_EPROM_RFCHIPID_RTL8225U	(5)
-#define URTW_EPROM_MACADDR		0x07
-#define URTW_EPROM_TXPW0		0x16 
-#define URTW_EPROM_TXPW2		0x1b
-#define URTW_EPROM_TXPW1		0x3d
-#define URTW_EPROM_SWREV		0x3f
-#define URTW_EPROM_CID_MASK		(0xff)
-#define URTW_EPROM_CID_RSVD0		(0x00)
-#define URTW_EPROM_CID_RSVD1		(0xff)
-#define URTW_EPROM_CID_ALPHA0		(0x01)
-#define URTW_EPROM_CID_SERCOMM_PS	(0x02)
-#define URTW_EPROM_CID_HW_LED		(0x03)
+#define	URTW_EPROM_TXPW_BASE		0x05
+#define	URTW_EPROM_RFCHIPID		0x06
+#define	URTW_EPROM_RFCHIPID_RTL8225U	(5)
+#define	URTW_EPROM_MACADDR		0x07
+#define	URTW_EPROM_TXPW0		0x16
+#define	URTW_EPROM_TXPW2		0x1b
+#define	URTW_EPROM_TXPW1		0x3d
+#define	URTW_EPROM_SWREV		0x3f
+#define	URTW_EPROM_CID_MASK		(0xff)
+#define	URTW_EPROM_CID_RSVD0		(0x00)
+#define	URTW_EPROM_CID_RSVD1		(0xff)
+#define	URTW_EPROM_CID_ALPHA0		(0x01)
+#define	URTW_EPROM_CID_SERCOMM_PS	(0x02)
+#define	URTW_EPROM_CID_HW_LED		(0x03)
 
 /* LED  */
-#define URTW_CID_DEFAULT		0
+#define	URTW_CID_DEFAULT		0
 #define	URTW_CID_8187_ALPHA0		1
 #define	URTW_CID_8187_SERCOMM_PS	2
 #define	URTW_CID_8187_HW_LED		3
@@ -200,16 +201,16 @@
 /* for extra area  */
 #define	URTW_EPROM_DISABLE		0
 #define	URTW_EPROM_ENABLE		1
-#define URTW_EPROM_DELAY		10
+#define	URTW_EPROM_DELAY		10
 #define	URTW_8187_GETREGS_REQ		5
 #define	URTW_8187_SETREGS_REQ		5
-#define URTW_8225_RF_MAX_SENS		6
-#define URTW_8225_RF_DEF_SENS		4
-#define URTW_DEFAULT_RTS_RETRY		7
-#define URTW_DEFAULT_TX_RETRY		7
-#define URTW_DEFAULT_RTS_THRESHOLD	2342U
+#define	URTW_8225_RF_MAX_SENS		6
+#define	URTW_8225_RF_DEF_SENS		4
+#define	URTW_DEFAULT_RTS_RETRY		7
+#define	URTW_DEFAULT_TX_RETRY		7
+#define	URTW_DEFAULT_RTS_THRESHOLD	2342U
 
-#define URTW_MAX_CHANNELS		15
+#define	URTW_MAX_CHANNELS		15
 
 struct urtw_tx_data {
 	struct urtw_softc	*sc;
@@ -229,10 +230,10 @@ struct urtw_rx_data {
 #define	URTW_MIN_RXBUFSZ						\
 	(sizeof(struct ieee80211_frame_min))
 
-#define URTW_RX_DATA_LIST_COUNT		1
-#define URTW_TX_DATA_LIST_COUNT		16
-#define URTW_RX_MAXSIZE			0x9c4
-#define URTW_TX_MAXSIZE			0x9c4
+#define	URTW_RX_DATA_LIST_COUNT		1
+#define	URTW_TX_DATA_LIST_COUNT		16
+#define	URTW_RX_MAXSIZE			0x9c4
+#define	URTW_TX_MAXSIZE			0x9c4
 
 struct urtw_rx_radiotap_header {
 	struct ieee80211_radiotap_header wr_ihdr;
@@ -242,7 +243,7 @@ struct urtw_rx_radiotap_header {
 	int8_t		wr_dbm_antsignal;
 } __packed;
 
-#define URTW_RX_RADIOTAP_PRESENT					\
+#define	URTW_RX_RADIOTAP_PRESENT					\
 	((1 << IEEE80211_RADIOTAP_FLAGS) |				\
 	 (1 << IEEE80211_RADIOTAP_CHANNEL) |				\
 	 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL))
@@ -255,7 +256,7 @@ struct urtw_tx_radiotap_header {
 	uint16_t	wt_chan_flags;
 } __packed;
 
-#define URTW_TX_RADIOTAP_PRESENT					\
+#define	URTW_TX_RADIOTAP_PRESENT					\
 	((1 << IEEE80211_RADIOTAP_FLAGS) |				\
 	 (1 << IEEE80211_RADIOTAP_CHANNEL))
 
@@ -267,7 +268,6 @@ struct urtw_softc {
 	usbd_device_handle		sc_udev;
 	usbd_interface_handle		sc_iface;
 
-	int				sc_debug;
 	int				sc_if_flags;
 	int				sc_flags;
 #define	URTW_INIT_ONCE			(1 << 1)
@@ -276,8 +276,8 @@ struct urtw_softc {
 	enum ieee80211_state		sc_state;
 	int				sc_arg;
 	int				sc_epromtype;
-#define URTW_EEPROM_93C46		0
-#define URTW_EEPROM_93C56		1
+#define	URTW_EEPROM_93C46		0
+#define	URTW_EEPROM_93C56		1
 	uint8_t				sc_crcmon;
 	uint8_t				sc_bssid[IEEE80211_ADDR_LEN];
 
@@ -287,7 +287,6 @@ struct urtw_softc {
 					    int);
 	usbd_status			(*sc_rf_set_sens)(struct urtw_softc *,
 					    int);
-	uint8_t				sc_rfchip;
 	uint32_t			sc_max_sens;
 	uint32_t			sc_sens;
 	/* for LED  */
@@ -308,7 +307,7 @@ struct urtw_softc {
 	usbd_pipe_handle		sc_txpipe_normal;
 #define	URTW_PRIORITY_LOW		0
 #define	URTW_PRIORITY_NORMAL		1
-#define URTW_DATA_TIMEOUT		10000		/* 10 sec  */
+#define	URTW_DATA_TIMEOUT		10000		/* 10 sec  */
 	struct urtw_rx_data		sc_rxdata[URTW_RX_DATA_LIST_COUNT];
 	struct urtw_tx_data		sc_txdata[URTW_TX_DATA_LIST_COUNT];
 	uint32_t			sc_tx_low_queued;
@@ -340,7 +339,8 @@ struct urtw_softc {
 		struct urtw_tx_radiotap_header th;
 		uint8_t pad[64];
 	}				sc_txtapu;
-#define sc_txtap	sc_txtapu.th
+#define	sc_txtap	sc_txtapu.th
 	int				sc_txtap_len;
 #endif
 };
+